CN219800136U

CN219800136U - Main unit device and main unit system of MBUS system

Info

Publication number: CN219800136U
Application number: CN202320889657.2U
Authority: CN
Inventors: 赵铮; 张佳一; 金芬
Original assignee: Hangzhou Ruimeng Technology Co ltd
Current assignee: Hangzhou Ruimeng Technology Co ltd
Priority date: 2023-04-20
Filing date: 2023-04-20
Publication date: 2023-10-03
Anticipated expiration: 2033-04-20

Abstract

The utility model discloses a host device of an MBUS system, which relates to the field of circuits. The logic control module completes the sending function of the host part by controlling the sending module, and completes the receiving function of the host part by controlling the receiving module. At the same time, the logic control module, sending module and receiving module are encapsulated in the tube shell, and the host part of the MBUS system is assembled in the form of a chip. It is used in the MBUS system as a host chip to better meet the application requirements on the basis of reducing application costs. requirements, it can also reduce the PCB area of the MBUS system during application, integrate and miniaturize the host part, the solution is simple and reliable, ensures the stability and reliability of the MBUS system, expands the application scope of the MBUS system, and is conducive to the further development of the MBUS system. develop. The utility model also discloses a host system of the MBUS system, which has the same beneficial effects as the host device of the above-mentioned MBUS system.

Description

Main unit device and main unit system of MBUS system

Technical Field

The utility model relates to the field of circuits, in particular to a host device of an MBUS system. The utility model also relates to a host system of the MBUS system.

Background

The M-Bus instrument Bus is a network system structure special for remote reading or related information reading of various instruments or devices, and is a Bus structure special for public utility instruments, namely Meter-Bus, which is called M-Bus for short. The M-Bus instrument Bus can meet the special requirements of the metering instrument powered by a battery or remotely. When the metering device receives the data transmission request, the data which is currently measured is transmitted to the master station, and the master station periodically reads the data of the metering device installed in a certain building. In general, the number of meters hooked up to a meter bus can be hundreds, and the data transmission distance can be thousands of meters. The data transferred over the bus has a high degree of integrity and rapidity. When in use, the MBUS system generally comprises a master machine part and a slave machine part, wherein the master machine part is the master station, and the slave machine part is the corresponding metering instrument, and the master machine part comprises a transmission mode and a receiving mode. In a transmitting mode, after receiving a signal, the host modulates the signal into a voltage signal corresponding to an MBUS protocol through an internal host module, and the slave generates TX output by sampling the voltage signal on the BUS BUS to finish the transmitting process of the host on the signal; in the receiving mode, the slave machine modulates the signal into an uplink current signal on the bus, the host machine analyzes the current signal to generate TXD output, and the receiving process of the host machine on the signal is completed.

In the prior art, for the host scheme of the MBUS protocol, a circuit built by discrete components is commonly adopted to realize the sending and receiving functions of the host, so that the device cost is high, the whole PCB area is large, and the quick development and wide application of the MBUS system are not facilitated.

Disclosure of Invention

The utility model aims to provide a host device and a host system of an MBUS system, wherein a logic control module, a sending module and a receiving module are packaged in a tube shell, a host part of the MBUS system is assembled into a chip, and the chip is used as the host chip to be applied to the MBUS system.

In order to solve the technical problems, the utility model provides a host device of an MBUS system, which comprises a tube shell, a logic control module, a transmitting module and a receiving module, wherein the logic control module is encapsulated in the tube shell;

the input end of the sending module is connected with a power supply, the control end of the sending module is connected with the output end of the logic control module, the output end of the sending module is connected with the BUSP of the BUS through a sending pin, the enabling end of the receiving module is connected with the output end of the logic control module, the input end of the receiving module is connected with the BUSN of the BUS through a receiving pin, the output end of the receiving module is connected with the processing module of the MBUS system through an output pin, and the input end of the logic control module is connected with the processing module of the MBUS system;

The logic control module is used for controlling the sending module and the receiving module based on the output signals of the processing module so that the host device enters different working modes, and the working modules comprise a sending mode and a receiving mode.

Preferably, the transmitting module includes: the first switching tube, the second switching tube and the diode; the power supply comprises a first power supply and a second power supply;

the control end of the first switching tube and the control end of the second switching tube are respectively connected with the output end of the logic control module, the anode of the diode is connected with the second power supply, the cathode of the diode is connected with the first end of the second switching tube, and the second end of the first switching tube and the second end of the second switching tube are connected and connected with the BUSP of the BUS through the sending pin.

Preferably, the host device further comprises a power supply module; the input end of the power supply module is connected with the first power supply, and the output end is used as a voltage output pin; for powering external devices.

Preferably, the host device further comprises a protection module and a protection switch; the input end of the protection module is respectively connected with the sending module and the receiving module, the output end of the protection module is respectively connected with the logic control module and the control end of the protection switch, the first end of the protection switch is grounded, and the second end of the protection switch is used as an error output pin;

The protection switch is used for being turned off when the host device meets the protection condition, and turned on when the host device does not meet the protection condition.

Preferably, the protection module comprises an overcurrent protection circuit, the input end of the overcurrent protection circuit is connected with the output end of the sending module, and the output end is respectively connected with the logic control module and the control end of the protection switch.

Preferably, the host device further comprises an oscillator, and an output end of the oscillator is connected with the logic control module and is used for outputting a preset oscillation signal.

Preferably, the receiving module includes: the device comprises a detection resistor, a conversion module, a bias current module, a conversion resistor and a difference detection module;

the first end of the detection resistor is respectively connected with the input end of the conversion module and the BUS to be detected, the second end of the detection resistor is grounded, the output end of the conversion module is respectively connected with the output end of the bias current module, the first end of the conversion resistor is connected with the input end of the difference detection module, the second end of the conversion resistor is grounded, the output end of the difference detection module is used as the output end of the current detection circuit, and the BUS to be detected is BUSN of the BUS BUS;

The detection resistor is used for converting the current signal of the bus to be detected into a first voltage signal;

the conversion module is used for converting the first voltage signal into a corresponding first current signal, the first current signal is in linear correlation with the first voltage signal, and the direction of the first current signal is consistent with the direction of the output current of the bias current module;

the conversion resistor is used for converting the first current signal into a corresponding second voltage signal;

the difference detection module is used for detecting the jump signal of the second voltage signal and outputting a third voltage signal corresponding to the second voltage signal based on the jump signal of the second voltage signal.

Preferably, the conversion module comprises a first operational amplifier module and a following module;

the input end of the first operational amplifier module is respectively connected with the first end of the detection resistor and the bus to be detected, the output end of the first operational amplifier module is connected with the input end of the following module, the output end of the following module is respectively connected with the output end of the bias current module, and the first end of the conversion resistor is connected with the input end of the difference detection module;

the first operational amplifier module is used for converting the first voltage signal into a corresponding second current signal, and the second current signal is in linear correlation with the first voltage signal;

The following module is used for converting the second current signal into a corresponding first current signal, the first current signal is in linear correlation with the second current signal, the direction of the second current signal is consistent with the direction of the first current signal, and the direction of the first current signal is consistent with the direction of the output current of the bias current module.

Preferably, the difference detection module includes: the device comprises a capacitor, a charging module, a discharging module and a differential amplifier;

the input end of the charging module is respectively connected with the output end of the conversion module, the output end of the bias current module is connected with the first end of the conversion resistor, the first output end of the charging module is respectively connected with the first end of the capacitor and the second input end of the differential amplifier, the second output end of the charging module is connected with the first input end of the differential amplifier, the second end of the capacitor is grounded, the discharging module is respectively connected with the first end of the capacitor and the second input end of the differential amplifier, and the output end of the differential amplifier is used as the output end of the current detection circuit;

the charging module is used for charging the capacitor when the second voltage signal is lower than a preset value;

And the discharging module is used for discharging the capacitor when the second voltage signal is higher than a preset value.

In order to solve the technical problem, the utility model also provides a host system of the MBUS system, which comprises a processing module and the host device of the MBUS system, wherein the processing module is connected with the host device of the MBUS system.

The utility model provides a host device of an MBUS system, which comprises a tube shell, a logic control module, a transmitting module and a receiving module, wherein the logic control module is encapsulated in the tube shell, the logic control module controls the transmitting module to complete the transmitting function of a host part, and the logic control module controls the receiving module to complete the receiving function of the host part. The logic control module, the sending module and the receiving module are packaged in the tube shell, the host part of the MBUS system is assembled into a chip, the chip is used as the host chip to be applied to the MBUS system, the application requirement can be better met on the basis of reducing the application cost, the PCB area of the MBUS system during application can be reduced, the host part is integrated and miniaturized, the scheme is simple and reliable, the stability and the reliability of the MBUS system are ensured, the application range of the MBUS system is expanded, and the further development of the MBUS system is facilitated.

The utility model also provides a host system of the MBUS system, which has the same beneficial effects as the host device of the MBUS system.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the drawings required in the prior art and the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present utility model, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic structural diagram of a host device of an MBUS system according to the present utility model;

FIG. 2 is a schematic diagram of an MBUS system according to the present utility model;

fig. 3 is a schematic signal waveform diagram of an MBUS system according to the present utility model in a transmission mode;

fig. 4 is a schematic signal waveform diagram of an MBUS system according to the present utility model in a receiving mode;

FIG. 5 is a schematic diagram of a host device of another MBUS system according to the present utility model;

fig. 6 is a schematic structural diagram of a transmitting module according to the present utility model;

fig. 7 is a schematic structural diagram of a receiving module according to the present utility model;

Fig. 8 is a schematic structural diagram of another receiving module according to the present utility model;

fig. 9 is a schematic structural diagram of a difference detection module in a receiving module according to the present utility model;

fig. 10 is a schematic signal waveform diagram of a difference detection module according to the present utility model;

FIG. 11 is a schematic diagram of a host device of an MBUS system according to the present utility model;

fig. 12 is a schematic signal waveform diagram of a host device of an MBUS system according to the present utility model;

fig. 13 is a schematic signal waveform diagram of a host device of an MBUS system according to the present utility model in a transmission mode;

fig. 14 is a schematic signal waveform diagram of a host device of an MBUS system according to the present utility model in a receiving mode;

fig. 15 is a schematic structural diagram of a host system of an MBUS system according to the present utility model.

Detailed Description

The utility model has the core of providing a host device and a host system of an MBUS system, wherein a logic control module, a transmitting module and a receiving module are packaged in a tube shell, a host part of the MBUS system is assembled into a chip, and the chip is used as a host chip to be applied to the MBUS system.

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present utility model more apparent, the technical solutions of the embodiments of the present utility model will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present utility model, and it is apparent that the described embodiments are some embodiments of the present utility model, but not all embodiments of the present utility model. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a host device of an MBUS system according to the present utility model; in order to solve the above technical problems, the present utility model provides a host device of an MBUS system, which includes a tube shell 14, a logic control module 11 encapsulated in the tube shell 14, a transmitting module 12 and a receiving module 13;

the input end of the sending module 12 is connected with a power supply, the control end is connected with the output end of the logic control module 11, the output end is connected with the BUSP of the BUS through a sending pin, the enabling end of the receiving module 13 is connected with the output end of the logic control module 11, the input end is connected with the BUSN of the BUS through a receiving pin, the output end is connected with the processing module of the MBUS system through an output pin, and the input end of the logic control module 11 is connected with the processing module of the MBUS system;

The logic control module 11 is configured to control the transmitting module 12 and the receiving module 13 based on output signals of the processing module so that the host device enters different operation modes, and the operation modules include a transmitting mode and a receiving mode.

Considering that the host part of the MBUS system has a plurality of working states, a logic control module 11 is provided to realize the conversion and control of different working states, the logic control module 11 receives signals from the processing module of the MBUS system and controls the host device to enter different working modes according to the received signals, so that the whole host device reaches different working states. The data communication between the logic control module 11 and the processing module may be implemented by providing a control pin on the host chip, or may directly receive a signal, and the present application is not limited in particular herein with respect to the data communication manner between the logic control module 11 and the processing module.

In particular, the processing module may include a processor and a memory, or may be a separate processor; may be a hand-held unit, computer or other data terminal; the specific implementation manner of the processing module, and the circuits and functions of other modules in the MBUS system are not particularly limited herein, and may be selected according to practical application requirements.

Specifically, referring to fig. 2, fig. 2 is a schematic structural diagram of an MBUS system according to the present utility model; referring to fig. 3, fig. 3 is a schematic signal waveform diagram of an MBUS system according to the present utility model in a transmission mode; referring to fig. 4, fig. 4 is a schematic signal waveform diagram of an MBUS system according to the present utility model in a receiving mode.

When the host device needs to enter a transmission mode, the logic control module 11 controls the transmission module 12 to work, and the receiving module 13 does not work; the sending process of the MBUS system is that the data transmission from the host part to the slave part is realized by adopting a voltage adjustment mode, as shown in fig. 3, VBUSH is the power supply voltage and corresponds to a data transmission 1 signal; VBUSL is also the supply voltage, corresponding to the data transfer 0 signal; VMARK is a modulation voltage, which must be greater than 8V at the slave end, and is more stable as the voltage is greater, but VBUSL cannot be lower than 10V, because the slave chip can work abnormally after being lower than 10V, and VMARK is generally designed around 12V in consideration of the condition that voltage drop exists in long-distance transmission voltage. The processing module 31 selects an MCU (Microcontrol ler Unit, micro control unit) implementation, the host device receives signals from the MCU, modulates the received signals into VBUS signals of the MBUS protocol through internal circuitry of the transmitting module 12, transmits the voltage signals through the BUS, and the slave device generates corresponding TX outputs by sampling the voltage signals on the BUS.

When the host device needs to enter a receiving mode, the logic control module 11 controls the sending module 12 to be not operated, and the receiving module 13 is operated; as shown in fig. 4, the slave unit part is usually implemented by using a slave chip such as MS721, and is used at the application end, and the receiving module 13 receives a signal from the RX end corresponding to the slave chip, modulates the signal into an uplink current signal on the BUS, and generates I on the basis of the original current IMS on the BUS _CS Is changed into IMS+I _CS I.e. I shown in FIG. 4 _MC ＝I _MDC +I _CS The receiving module 13 in the host device can analyze the current signal by sampling the sampling resistor, and has I _CS The current increases to a 1 signal, the current maintains the IMS unchanged to a 0 signal, and a TXD output may be generated based thereon.

It can be understood that the logic control module 11, the transmitting module 12 and the receiving module 13 are packaged in the package 14, that is, the host part of the MBUS system is manufactured into a chip form through a packaging form, and the chip is directly used as a host chip in the MBUS system, and the package 14, that is, a shell for mounting a semiconductor integrated circuit chip, not only plays roles in mounting, fixing, sealing, protecting the chip, enhancing the electrothermal performance and the like, but also is connected to pins of the package shell through wires for joints on the chip, and the pins are connected with other devices through wires on a printed circuit board, so that the connection between an internal chip and an external circuit is realized, and meanwhile, the isolation between the inside of the chip and the outside is ensured, so that the corrosion of impurities in the air to the chip circuit is prevented, and the electrical performance is reduced. The function of the host part of the MBUS system is completed through the host chip, so that the integrated and miniaturized host device of the MBUS system is realized. The application is not particularly limited herein with respect to the specific implementation of the encapsulation process, the form of encapsulation, the encapsulating material, etc.

Specifically, the specific circuit structures and implementation manners of the logic control module 11, the transmitting module 12 and the receiving module 13 are not limited herein, and may be selected according to actual application requirements. The logic control module 11 may be implemented by a logic gate circuit; the transmitting module 12 may be implemented by a circuit formed by a MOS transistor (Metal-Oxide-Semiconductor Field-Effect Trans istor), or by other means; the receiving module 13 may be implemented by a current detection circuit or the like. The utility model is not particularly limited in the specific implementation manner of the power supply, and various choices exist in the pin arrangement, circuit structure and the like of the final chip of the host device, and the utility model is not particularly limited in the specific implementation manner and can be arranged according to the actual application requirements.

The utility model provides a host device of an MBUS system, which comprises a tube shell 14, a logic control module 11, a transmitting module 12 and a receiving module 13, wherein the logic control module 11 controls the transmitting module 12 to complete the transmitting function of a host part, and the logic control module 11 controls the receiving module 13 to complete the receiving function of the host part. The logic control module 11, the sending module 12 and the receiving module 13 are packaged in the tube shell 14, the host part of the MBUS system is assembled into a chip, the chip is used as the host chip to be applied to the MBUS system, the application requirement can be better met on the basis of reducing the application cost, the PCB area of the MBUS system can be reduced during application, the host part is integrated and miniaturized, the scheme is simple and reliable, the stability and the reliability of the MBUS system are ensured, the application range of the MBUS system is expanded, and the further development of the MBUS system is facilitated.

On the basis of the above-described embodiments,

referring to fig. 5, fig. 5 is a schematic structural diagram of a host device of another MBUS system according to the present utility model;

referring to fig. 6, fig. 6 is a schematic structural diagram of a transmitting module 12 according to the present utility model;

as a preferred embodiment, the transmitting module 12 includes: a first switching tube M1, a second switching tube M2 and a diode D4; the power supply comprises a first power supply and a second power supply;

the control end of the first switching tube M1 and the control end of the second switching tube M2 are respectively connected with the output end of the logic control module 11, the first end of the first switching tube M1 is connected with a first power supply, the anode of the diode D4 is connected with a second power supply, the cathode of the diode D4 is connected with the first end of the second switching tube M2, the second end of the first switching tube M1 and the second end of the second switching tube M2 are connected, and the control end of the first switching tube M1 and the control end of the second switching tube M2 are connected with BUSP of the BUS through a sending pin.

Considering that the transmission process of the host device is mainly realized based on a voltage adjustment mode, a first switching tube M1 and a second switching tube M2 are arranged, the first ends of the first switching tube M1 and the second switching tube M2 are connected with voltages of different magnitudes to realize voltage adjustment, meanwhile, considering that the condition that current flows backward due to the connection of the second ends of the two switching tubes is caused, a diode D4 is arranged at the front end of the second switching tube M2, so that the current flowing backward condition is avoided.

It will be appreciated that as shown in FIG. 6, VBB and VBA are external power supplies, VBB is the VBUSH voltage, VBA is the VBUSL voltage, and VBB-VBA-VD is the VMARK voltage. Through the switch switching of the first switch tube M1 and the second switch tube M2, the corresponding BUSP pin outputs corresponding VBB or VB-VD voltage. The first switching tube M1 and the second switching tube M2 are integrated inside a chip, and the SW1 signal and the SW2 signal are output signals of the logic control module 11 and are controlled by the received output signals RXD of the processing module 31 and R/T signals of the mode conversion pins.

Specifically, the type, arrangement and implementation of the diode D4 are not particularly limited, and a schottky diode may be selected, and if the voltage value of the second power supply is large, the diode D4 needs to flow a current of hundreds of milliamperes, and the corresponding diode D4 has a large size, and in this case, considering that the area occupied by integrating the diode D4 into the chip is large, the diode D4 may not be integrated into the chip, and may be disposed outside the chip and connected through a corresponding pin.

In practical application, the first switching tube M1 and the second switching tube M2 may be selected from MOS transistors, or may be selected from switching devices such as transistors, but in order to ensure the practicability of the host device as a host chip, the preferred choice is a switching device with small size and easy integration, and the application is not limited in particular to the type and specific implementation of the first switching tube M1 and the second switching tube M2, and may be selected according to practical application requirements. The specific values and implementation manners of the first power supply and the second power supply are not particularly limited herein.

Specifically, the transmitting module 12 includes a first switching tube M1, a second switching tube M2 and a diode D4, and the power supply includes a first power supply and a second power supply, and outputs different voltages by switching the switching tubes, so as to implement the transmitting process of the host device, ensure the accurate implementation of the host device, have a simple and reliable circuit structure, are easy to integrate, and ensure the miniaturization of the integration of the host portion on the basis of reducing the application cost.

As a preferred embodiment, the host device further comprises a power supply module 15; the input end of the power supply module 15 is connected with a first power supply, and the output end is used as a voltage output pin; for powering external devices.

It should be noted that, the external device refers to a corresponding device in the peripheral circuit after the host device is assembled as a chip; the power module 15 mainly has a step-down function, and at the same time, needs to ensure the driving capability of the output voltage for the normal operation of the external device.

Considering that peripheral circuits and external devices are required to realize more functions after the host device is assembled into a chip, the power supply module 15 is additionally arranged to supply power to the external devices of the chip, the host device is further perfected, the application range and the functional requirements of the host device are expanded, and the further development of the MBUS system is facilitated.

As a preferred embodiment, the host device further comprises a protection module 16 and a protection switch; the input end of the protection module 16 is respectively connected with the sending module 12 and the receiving module 13, the output end is respectively connected with the logic control module 11 and the control end of the protection switch, the first end of the protection switch is grounded, and the second end is used as an error output pin;

the protection switch is used for being turned off when the host device meets the protection condition and being turned on when the host device does not meet the protection condition.

Considering that the internal circuit needs to be protected and monitored after the host device is assembled into a chip, so that a worker or a user can know the internal state of the chip in time, a protection module 16 and a corresponding protection switch are additionally arranged; the protection module 16 is used for monitoring a circuit inside the chip, and when the internal circuit has faults such as short circuit and/or open circuit, on the one hand, the protection module directly outputs signals to the logic control module 11, so that the logic control module 11 directly controls the host device to stop working, and further circuit damage and other conditions are avoided; on the other hand, the output signal controls the protection switch to be closed, so that the error output pin is grounded, the corresponding error output pin can be changed from the high level of the default output to the low level, and a worker or a user can determine whether the inside of the host chip can work normally according to the state of the error output pin.

It can be understood that, since the protection switch is grounded inside the chip, the error output pin needs to be connected with the pull-up resistor at the periphery of the chip to ensure accurate implementation of the protection switch, and meanwhile, in order to better achieve the monitoring and prompting effects, the host chip can be connected with the remote devices such as the prompting module and/or the processor through the error output pin, and the prompting module and/or the processor can execute the corresponding prompting strategy when the state of the error output pin changes, so as to achieve the more convenient prompting effect.

Specifically, the present application is not limited in particular to the type and specific implementation of the protection module 16 and the protection switch, and the protection module 16 may be an overcurrent protection circuit, or the like, and may be configured to implement protection of the host device from monitoring a single parameter such as current or voltage, or may be configured to implement protection of the host device from multiple parameters such as current and voltage; the protection switch can be realized by selecting MOS (metal oxide semiconductor) tubes or other switching devices, but in order to ensure the practicability of the host device finally serving as a host chip, the preferred choice is a switching device which is small in size and easy to integrate.

Considering that the internal circuit needs to be protected and monitored after the host device is assembled into a chip, so that a worker or a user can know the internal state of the chip in time, a protection module 16 and a corresponding protection switch are additionally arranged; the fault of the internal circuit of the chip can be timely found through the logic control module 11 and the error output pin, and the error working process is stopped, so that the accurate implementation of the host device is ensured, the fault can be timely found so that related personnel can rapidly overhaul, and the stability and the reliability of the host device are ensured.

As a preferred embodiment, the protection module 16 comprises an overcurrent protection circuit, the input of which is connected to the output of the transmission module 12, and the output is connected to the logic control module 11 and to the control of the protection switch, respectively.

Specifically, the protection module 16 may include an over-current protection circuit, so as to realize protection of the host device by monitoring the current inside the host device; the overcurrent protection circuit can be specifically realized through an overcurrent device such as a fuse, a protection circuit built by a component such as a triode and the like, the type and the specific implementation mode of the overcurrent protection circuit are not particularly limited, and the overcurrent protection circuit can be selected according to factors such as actual application requirements and host chip size requirements.

As a preferred embodiment, the host device further comprises an oscillator 17, and an output terminal of the oscillator 17 is connected to the logic control module 11 for outputting a preset oscillation signal.

It will be appreciated that after the host is assembled into a host chip, in order to ensure control of the chip and regular operation of the chip, an oscillator 17 is additionally provided, the oscillator 17 operates at a selected frequency to generate a clock pulse with stable frequency and constant amplitude, and the clock pulse is provided to each system in the chip, so that circuits with different structures and different functions operate in a mutually coordinated manner under the control of a clock according to a uniform rhythm, a data transmission rate and a specified time sequence, thereby completing the function of the whole host chip. Specifically, the type and implementation of the oscillator 17 are not particularly limited, and may be selected according to practical application requirements.

In consideration of the normal working process of the host chip, the oscillator 17 is additionally arranged, a preset oscillation signal is output to ensure the accurate work of each module inside the host chip, the accurate realization of the host device is ensured, the circuit structure is simple and reliable, the integration is easy, the integration miniaturization of the host part is ensured on the basis of reducing the application cost, and the stability and the reliability of the host device are ensured.

Referring to fig. 7 and 8, fig. 7 is a schematic structural diagram of a receiving module according to the present utility model; fig. 8 is a schematic structural diagram of another receiving module according to the present utility model;

as a preferred embodiment, the receiving module 13 includes: the device comprises a detection resistor, a conversion module, a bias current module, a conversion resistor and a difference detection module;

the first end of the detection resistor is connected with the input end of the conversion module and the BUS to be detected respectively, the second end of the detection resistor is grounded, the output end of the conversion module is connected with the output end of the bias current module respectively, the first end of the conversion resistor is connected with the input end of the difference detection module, the second end of the conversion resistor is grounded, the output end of the difference detection module is used as the output end of the current detection circuit, and the BUS to be detected is BUSN of the BUS BUS;

The detection resistor is used for converting a current signal of the bus to be detected into a first voltage signal;

the difference detection module is used for detecting a jump signal of the second voltage signal and outputting a third voltage signal corresponding to the second voltage signal based on the jump signal of the second voltage signal.

Specifically, the current signal detected on the BUSN of the BUS is connected to the first end of the detection resistor RSENSE, the detection resistor RSENSE converts the detected current signal into a voltage of the first end of the detection resistor RSENSE, that is, a first voltage signal, the first voltage signal is easily known to the characteristics of the resistor, the first voltage signal is connected to the first end of the detection resistor RSENSE at the input end of the conversion module 1, the first voltage signal is input into the conversion module 1, the conversion module 1 converts the first voltage signal into a first current signal, the output end of the conversion module 1 is connected to the output end of the bias current module 2, it can be understood that a part of the current output by the bias current module 2 flows into the conversion module 1 as the first current signal, the other part of the current flows through the conversion resistor R2, the conversion resistor R2 converts the first voltage signal into a voltage of the first end of the conversion resistor R2, that is easily known to the characteristics of the resistor, the second voltage signal is linearly related to the first current signal, and after the difference detection module 3 receives the second voltage signal, the second voltage signal can be converted into a second voltage signal according to the characteristics of the detected voltage signal, and then the second voltage signal can be analyzed by a person at the far end of the third device according to the detected voltage signal.

It can be understood that after the first voltage signal is received, the conversion module 1 may amplify and/or enhance the first voltage signal, and then convert the first voltage signal into the first current signal, so as to facilitate accuracy and stability of the subsequent second voltage signal and third voltage signal, and further ensure reliability and safety of the final output result. The conversion module 1 converts the first voltage signal into the first current signal, which is mainly convenient for transmission and conversion, the voltage signal is easy to distort in the transmission process, lost and is easy to be interfered by factors such as electromagnetism, obvious errors can be caused, and if the transmission path is longer, excessive pressure drop can be caused, so that the finally output signal has the problems of large loss degree, excessive loss, difficult detection and the like. The circuit structure, the specific implementation mode and the like of the conversion module 1 are not particularly limited, and can be adjusted according to actual application requirements.

Considering that the subsequent analysis process needs to calculate the current and/or voltage parameters in the circuit to determine the specific value thereof, the bias current module 2 is set to output a fixed current, so as to provide a current source for the conversion module 1, facilitate the conversion of the current signal into the voltage signal by the conversion resistor R2, and meanwhile, the known fixed current is beneficial to the subsequent specific calculation of the circuit parameters such as the first current signal, the second voltage signal and the like, and meanwhile, a static working point can be provided for devices in the circuit, thereby being convenient for realizing the control circuit and changing the parameters and other operations according to the actual requirements. The present application is not particularly limited herein with respect to the circuit configuration, the specific implementation, and the like of the bias current module 2. The specific value and implementation mode of the output bias current are not particularly limited herein, and can be adjusted manually; specifically, the bias current module 2 includes a reference current source Iref and a bias module 24; the receiving module 13 is provided with a fixed bias current so as to facilitate the conversion operation between the voltage and the current by the conversion module 1 and the conversion resistor R2, and the fixed reference current is beneficial to accurately analyzing the whole circuit, so that the circuit structure is simple and easy to realize.

Specifically, the first current signal may be calculated by the first voltage signal and the resistance value of the detection resistor RSENSE, and the current flowing through the conversion resistor R2 may be calculated according to the first current signal and the output current of the bias current module 2, and then the value of the second voltage signal may be calculated according to the resistance value of the conversion resistor R2. Further, the first voltage signal can be analyzed through the output second voltage signal, so that analysis and calculation of the current signal detected on the BUSN of the BUS BUS are realized.

Specifically, the difference detecting module 3 may amplify and/or enhance the second voltage signal, for the jump signal of the second voltage signal, the difference detecting module 3 may rapidly detect and amplify the jump signal, and finally output the amplified third voltage signal, but basically the third voltage signal is consistent with the second voltage signal, and may reversely push out the change condition of the current signal detected on the BUS sn of the BUS according to the third voltage signal, and due to the process of detecting and amplifying the jump signal, the third voltage signal may be more accurate, more obvious and clear, so as to effectively implement the detection process of the current signal detected on the BUS sn of the BUS, which is beneficial to the subsequent analysis process of the current signal detected on the BUS sn of the BUS. The circuit structure and the specific implementation of the difference detection module 3 are not particularly limited, and the application can be adjusted according to the actual application requirement and the situation of the current signal detected on the BUS, specifically, referring to fig. 8, the difference detection module 3 is composed of the difference signal detection circuit 23 and the capacitor Css, and the capacitor Css is usually larger in required value, so that the capacitor Css can be applied without being integrated into a chip based on cost consideration, but only by setting the pin CS and externally connecting a large capacitor.

It should be noted that, in the whole working process, the current signal detected on the BUS is converted between voltage and current, and is converted into a voltage signal, and the voltage signal can be amplified and/or signal-enhancing operation can be performed through devices such as an operational amplifier, so that the signal strength can be improved, the stability and reliability of the signal can be ensured, and the current signal can be converted into a current signal for more effective transmission, so that the current transmission is more accurate and reliable, safe and effective, and the current signal can be amplified through circuit structures such as a current mirror, so that the accuracy and the effectiveness of the final output signal can be ensured.

Specifically, the application is not particularly limited in terms of specific types and resistance values of the detection resistor RSENSE and the conversion resistor R2, and the application can be adjusted according to practical application requirements, specific circuit structures and the like, and generally, the types and the resistance values of the detection resistor RSENSE and the conversion resistor R2 can be the same or different, and under normal conditions, a fixed resistor is selected as the detection resistor RSENSE and the conversion resistor R2, and an adjustable resistor can be selected, so that the adjustable resistor is more convenient to adjust at any time to adapt to different application requirements, and the fixed resistor is more stable and reliable and is convenient to calculate.

The receiving module 13 provided in this embodiment can realize current detection under the condition of low-voltage power supply such as an integrated chip or an on-chip integrated circuit, so as to effectively detect small current in the integrated chip or the on-chip integrated circuit, especially a jump signal of the small current on an M-bus, and ensure accurate implementation of the receiving module after the host device is assembled into the host chip, thereby realizing a transmitting process of the host device, ensuring accurate implementation of the host device, ensuring clear and definite circuit structure, being easy to integrate, and ensuring integrated miniaturization of the host part on the basis of reducing application cost.

As a preferred embodiment, the conversion module 1 comprises a first op-amp module and a following module;

the input end of the first operational amplifier module is respectively connected with the first end of the detection resistor RSENSE and the BUSN of the BUS, the output end of the first operational amplifier module is connected with the input end of the following module, the output end of the following module is respectively connected with the output end of the bias current module 2, and the first end of the conversion resistor R2 is connected with the input end of the difference detection module 3;

The following module is used for converting the second current signal into a corresponding first current signal, the first current signal and the second current signal are in linear correlation, the direction of the second current signal is consistent with the direction of the first current signal, and the direction of the first current signal is consistent with the direction of the output current of the bias current module 2.

Specifically, the first operational amplifier module converts the first voltage signal into a corresponding second current signal, and before conversion, the first operational amplifier module can amplify and/or enhance the first voltage signal so as to obtain a more stable and reliable accurate signal later, and the first operational amplifier module converts the first voltage signal into the corresponding second current signal in consideration of the need of transmission operation of the follow-up module; the following module is mainly used for transmitting current, and can process the second current signal into the first current signal through operations such as amplification, and the first current signal and the second current signal are in linear correlation and can be equal or unequal. It will be appreciated that the following module simply amplifies and/or transmits the current, and does not change the direction of the current, so that the direction of the second current signal coincides with the direction of the first current signal and with the direction of the output current of the bias current module 2.

It can be understood that the first operational amplifier module can be realized by selecting a circuit structure with the combination of an operational amplifier and a resistor, the following module can be realized by selecting a current mirror structure formed by MOS (metal oxide semiconductor) tubes, and the application is not particularly limited in the circuit structure, the specific implementation mode and the like of the first operational amplifier module and the following module, and can be adjusted according to actual application requirements.

Specifically, the conversion module 1 includes a first operational amplifier module and a following module; the first operational amplifier module converts the first voltage signal into a corresponding second current signal; the following module is mainly used for transmitting current and can process the second current signal into the first current signal through operations such as amplification and the like; the function of the conversion module 1 is effectively realized through the first operational amplifier module and the following module, so that the circuit structure of the conversion module 1 is clearer and more definite, and the amplifying and/or enhancing effects on signals can be increased, so that the follow-up conversion resistor R2 and the difference detection module 3 are accurately realized, and the reliability and the safety of the receiving module 13 are ensured.

As shown in fig. 8, the first operational amplifier module includes a first operational amplifier 21, an operational amplifier switch NM3, and a voltage dividing resistor R1; the whole circuit forms a virtual short of the first operational amplifier 21, the voltage of the inverting input end of the first operational amplifier 21 is equal to the voltage of the non-inverting input end, the voltage of the first end of the voltage dividing resistor R1 is also equal to the voltage of the non-inverting input end, namely a first voltage signal, due to the fact that the inverting input end of the first operational amplifier 21 is connected with the first end of the voltage dividing resistor R1, meanwhile, the first voltage signal is converted into a current signal due to the characteristic of the voltage dividing resistor R1, and when the operational amplifier switch NM3 is conducted, the currents of the first end and the second end are equal, and therefore the current flowing through the voltage dividing resistor R1 is equal to the input current of the following module, namely a second current signal. The first operational amplifier 21 may also have a certain signal gain for the first voltage signal, so as to ensure the accuracy and reliability of the subsequent signal.

It will be appreciated that, for the specific types of the first operational amplifier 21, the operational amplifier switch NM3 and the voltage dividing resistor R1, the parameter values, implementation and the like are not limited herein, and may be selected according to practical application requirements, the operational amplifier switch NM3 may select switching devices such as N-type MOS transistors or triodes, and the voltage dividing resistor R1 may select fixed resistors or adjustable resistors.

Specifically, the first operational amplifier module includes a first operational amplifier 21, an operational amplifier switch NM3, and a voltage dividing resistor R1; the function of the first operational amplifier module is effectively realized by utilizing the virtual short of the first operational amplifier 21 and the conduction of the operational amplifier switch NM3, the circuit structure is simple, the implementation is easy, the application is convenient, the cost of the adopted devices is low, the integral implementation of the receiving module 13 is facilitated, the gain of the first voltage signal can be realized by the operational amplifier, the accurate implementation of the subsequent circuit is facilitated, and the safety and the reliability of the whole receiving module 13 are ensured.

As shown in fig. 8, the follower module includes a first PMOSPM1, a second PMOSPM2, a first nmosm 1, and a second nmosm 2; the first PMOSPM1 and the second PMOSPM2 form a pair of current mirrors, and the first NMOSNM1 and the second NMOSNM2 form a pair of current mirrors; in consideration of the effect of the following module on current transmission, in order to ensure the stable direction of the current, two pairs of current mirrors, also called mirror constant current sources, are arranged, the output current of the current mirrors is copied to the input current according to a certain proportion, the current mirrors have relatively high output resistance, the output current is kept constant regardless of the load condition, and the current transmission is effectively realized. Meanwhile, the amplification factor can be adjusted by adjusting the mirror proportion of the current mirror, so that the amplification of the second current signal is realized; the provision of two pairs of current mirrors also enables the second current signal to be amplified more effectively, and in the case of a very small first voltage signal the entire receiving module 13 to be realized.

It can be understood that, for the specific types of the first PMOSPM1, the second PMOSPM2, the first nmosm 1, the second nmosm 2, the parameter selection and implementation manner, etc. the present application is not limited in particular herein, and may be selected according to practical application requirements, and the adjustment of the mirror image proportion of the current mirror may be implemented by adjusting the width-to-length ratio of the four MOS transistors, or may be implemented in other manners.

Specifically, the following module is realized through two pairs of current mirrors consisting of the first PMOSPM1, the second PMOSPM2, the first NMOSNM1 and the second NMOSNM2, the circuit structure is simple, the implementation is easy, the application is convenient and fast, the function of the following module can be effectively realized, the current mirrors can ensure the accuracy and the stability of current transmission, and meanwhile, the amplification of current signals can be realized through adjusting the mirror image proportion, so that the accurate realization of the whole receiving module 13 is facilitated, and the safety and the reliability of the receiving module 13 are ensured.

As a preferred embodiment, further comprising: the second operational amplifier module; the input end of the second operational amplifier module is respectively connected with the output end of the bias current module 2, the first end of the conversion resistor R2 is connected with the output end of the conversion module 1, and the output end of the second operational amplifier module is connected with the input end of the difference detection module 3;

The second operational amplifier module is used for improving the driving capability of the second voltage signal.

Considering that the application scenario of the whole receiving module 13 is usually low-voltage power supply, there may be a situation that the driving capability of the second voltage signal is low, and a second operational amplifier module is additionally arranged in front of the difference detection module 3 to improve the driving capability of the second voltage signal, and the voltage signal with improved driving capability is output to the difference detection module 3 again, so that the difference detection module 3 can be effectively realized.

It can be understood that the specific implementation manner of the second operational amplifier module has various choices, and devices such as an operational amplifier or related circuit structures can be selected for implementation, so that the application is not particularly limited herein, and can be selected according to actual application requirements. Specifically, when the second operational amplifier module is implemented by using the second operational amplifier 22, the non-inverting input terminal of the second operational amplifier 22 is used as the input terminal of the second operational amplifier module, and the output terminal of the second operational amplifier 22 is connected to the inverting input terminal of the second operational amplifier 22 and the input terminal of the difference detection module 3, respectively.

Considering that the application scene of the whole receiving module 13 is the condition of low-voltage power supply in a chip, the condition that the driving capability of the second voltage signal is lower possibly exists, a second operational amplifier module is additionally arranged in front of the difference detecting module 3, the driving capability of the second voltage signal is improved, the effective implementation of the difference detecting module 3 is ensured, the accuracy and the reliability of the difference detecting module 3 can be further improved by improving the driving capability of the signal, the accurate implementation of the whole receiving module 13 is ensured, and the accuracy and the reliability of the whole receiving module 13 are further ensured.

As a preferred embodiment, the difference detection module 3 includes: a capacitor Css, a charging module, a discharging module and a differential amplifier 25;

the input end of the charging module is respectively connected with the output end of the conversion module 1, the output end of the bias current module 2 and the first end of the conversion resistor R2, the first output end of the charging module is respectively connected with the first end of the capacitor Css and the second input end of the differential amplifier 25, the second output end of the charging module is connected with the first input end of the differential amplifier 25, the second end of the capacitor Css is grounded, the discharging module is respectively connected with the first end of the capacitor Css and the second input end of the differential amplifier 25, and the output end of the differential amplifier 25 serves as the output end of the receiving module 13;

the charging module is used for charging the capacitor Css when the second voltage signal is lower than a preset value;

the discharging module is used for discharging the capacitor Css when the second voltage signal is higher than a preset value.

Considering that the current detection process needs to accurately monitor the current change process, the difference detection module 3 realizes accurate detection of the jump of the second voltage signal through the charge-discharge process of the capacitor Css, finally outputs a third voltage signal corresponding to the second voltage signal based on the jump signal, integrally plays a role of amplifying the signal and enhancing the signal, and ensures that small jump can be detected through the further amplified jump signal of the differential amplifier 25, and compared with the second voltage signal, the third voltage signal is easier to analyze, thereby being beneficial to the follow-up analysis of the current signal detected on the BUSN of the BUS based on the third voltage signal and realizing the current detection process.

In the initial stage of the difference detection module 3, an initial setup time is required, in which the capacitor Css is charged first, and then after entering a working state, the voltages at two ends of the capacitor Css are stabilized near a preset voltage value; when the second voltage signal is a smaller voltage value, the voltage at the two ends of the capacitor Css needs to be reduced from a preset value to a voltage value corresponding to the second voltage signal, the capacitor Css can enter a discharging process, and is discharged through a discharging module, and when the second voltage signal jumps to a larger voltage value, the first input end of the differential amplifier 25 can respond instantly and is stabilized to the voltage value corresponding to the second voltage signal; the second input end is connected with the first end of the capacitor Css, so that the voltage at the two ends of the capacitor Css cannot be suddenly changed, a charging process is required, and the capacitor Css is charged through the charging module until the voltage value corresponding to the current second voltage signal is reached; because of the difference in time between the two voltage changes, the first input terminal can be considered to be a real-time response signal change, and the second input terminal is a voltage signal similar to a direct current state, and thus the jump signal of the second voltage signal can be accurately detected by the differential amplifier 25 of the subsequent stage, and the output of the corresponding third voltage signal can be generated.

Specifically, the specific types and implementation manners of the capacitor Css, the charging module, the discharging module, the differential amplifier 25, and the like are not particularly limited herein, and various parameters of the capacitor Css are also selected, the capacitor Css is not particularly limited herein, and can be selected according to actual application requirements, and the capacitor Css is generally selected to have a polar capacitor Css or can be selected to have a non-polar capacitor Css; the charging module can be realized by an RC charging circuit or other circuit structures; the discharging module can be realized through a structure of grounding a fixed resistor, and other modes can be selected; the differential amplifier 25 may be implemented as a direct selection comparator or may be of another type.

Specifically, the difference detection module 3 includes a capacitor Css, a charging module, a discharging module, and a differential amplifier 25; the amplification and accurate detection of the jump signal are realized through the charge and discharge process of the capacitor Css, the effect of the difference detection module 3 is effectively realized, the circuit structure is simple, the implementation is easy, the application is convenient, the detection process of the current is further realized through the jump signal of the detection voltage, the detection process of the current can also be realized under the condition of low-voltage power supply, so that the follow-up related staff can effectively judge the current state under the condition of low-voltage power supply, the application range of the current detection technology is expanded, and the further development of the power technology is facilitated.

Specifically, the charging module comprises a first unidirectional conduction module D1, a second unidirectional conduction module D2 and a charging resistor R5; the positive pole of first unidirectional conduction module D1 is connected with the output of conversion module 1 respectively, the output of bias current module 2 and the first end of converting resistor R2, and the negative pole of first unidirectional conduction module D1 is connected with the positive pole of second unidirectional conduction module D2 and the first input of differential amplifier 25 respectively, and the negative pole of second unidirectional conduction module D2 is connected with the first end of charging resistor R5, and the second end of charging resistor R5 is connected with the first end of electric capacity Css and the second input of differential amplifier 25 respectively.

Considering that the voltage at the first end of the capacitor Css fluctuates in the charging and discharging process of the capacitor Css, in order to avoid the situation that current flows backwards possibly caused by the voltage fluctuation at the first end of the capacitor Css, meanwhile, in order to avoid the capacitor Css discharging through the charging resistor R5, the charging module is provided with a first unidirectional conduction module D1 and a second unidirectional conduction module D2, the current flowing direction in the charging process is regulated, and the charging resistor R5 can play a role of voltage division and current limitation, so that a circuit can be protected better; meanwhile, the voltage at the first end of the capacitor Css can not drop to a very low state after discharging due to the arrangement of the unidirectional conduction module, so that the finally output signal amplitude is prevented from being too large, the capacitor Css can be effectively protected, and the whole circuit is protected.

It can be understood that, for the specific types of the first unidirectional conduction module D1, the second unidirectional conduction module D2, the charging resistor R5, the parameter selection and implementation manner are not particularly limited herein, and may be selected according to the actual application requirements and the specific value of the capacitor Css; the first unidirectional conduction module D1 and the second unidirectional conduction module D2 can be realized by selecting diodes, other unidirectional conduction devices such as unidirectional silicon can also be adopted, the charging resistor R5 can be selected to be a fixed resistor, and the method is low in cost and easy to realize.

Specifically, the charging module comprises a first unidirectional conduction module D1, a second unidirectional conduction module D2 and a charging resistor R5; the first unidirectional conduction module D1 and the second unidirectional conduction module D2 prescribe the current flowing direction in the charging process, so that the condition of current backflow is avoided, and the charging resistor R5 can better protect a circuit; the circuit structure is simple and easy to realize, the cost of the used devices is low, the function of the charging module is effectively realized, the accurate realization of the difference detection module 3 is ensured, and the safety and reliability of the whole receiving module 13 are improved.

Specifically, the discharging module comprises a third unidirectional conduction module D3, a first discharging resistor R3 and a second discharging resistor R4; the first end of the first discharging resistor R3 is grounded, the second end is respectively connected with the negative electrode of the first unidirectional conduction module D1, the positive electrode of the second unidirectional conduction module D2 and the negative electrode of the third unidirectional conduction module D3, the positive electrode of the third unidirectional conduction module D3 is respectively connected with the first end of the capacitor Css, the second input end of the differential amplifier 25 is connected with the first end of the second discharging resistor R4, and the second end of the second discharging resistor R4 is grounded.

Considering that the voltage at the first end of the capacitor Css fluctuates during the charging and discharging process of the capacitor Css, in order to avoid the situation that current flows backwards possibly caused by the voltage fluctuation at the first end of the capacitor Css, the discharging module is provided with a third unidirectional conduction module D3 for avoiding discharging the capacitor Css through the charging resistor R5, the current flowing direction during the discharging process is regulated, the discharging of the capacitor Css through the charging resistor R5 is avoided, the first discharging resistor R3 and the second discharging resistor R4 can play a role in voltage division and current limiting, and a better protection circuit can be realized; meanwhile, the voltage at the first end of the capacitor Css can not drop to a very low state after discharging due to the arrangement of the unidirectional conduction module, so that the finally output signal amplitude is prevented from being too large, the capacitor Css can be effectively protected, and the whole circuit is protected.

It can be understood that, for the third unidirectional conduction module D3, specific types of the first discharging resistor R3 and the second discharging resistor R4, parameter selection, implementation manner, and the like are not particularly limited herein, and may be selected according to actual application requirements and specific values of the capacitor Css; the third unidirectional conduction module D3 can be realized by selecting a diode, other unidirectional conduction devices such as unidirectional silicon can also be adopted, the first discharging resistor R3 and the second discharging resistor R4 can be fixed resistors, and the method is low in cost and easy to realize.

Specifically, the discharging module comprises a third unidirectional conduction module D3, a first discharging resistor R3 and a second discharging resistor R4; the third unidirectional conduction module D3 prescribes the current flowing direction in the discharging process, so that the discharging process is avoided through the charging resistor R5, and the first discharging resistor R3 and the second discharging resistor R4 can be better protected; the circuit structure is simple and easy to realize, the cost of the used devices is low, the effect of the discharging module is effectively realized, the accurate realization of the difference detection module 3 is ensured, and the safety and reliability of the whole receiving module 13 are improved.

As a specific embodiment, as shown in fig. 8, IBUS represents a current signal detected on BUSN of the BUS, VBUSN represents a first voltage signal, and TXD is an output terminal of the receiving module 13.

Specifically, the current signal detected on the BUSN of the BUS is converted to the first voltage signal VBUSN by flowing to ground through the detection resistor RSENSE. Is sampled and converted into a first current signal I1 by a first operational amplifier 21, andwhen the mirror image proportion of the current mirror is 1:1, I is realized through the current mirror image relationship ₄ ＝I ₁ Current I flowing through the switching resistor R2 ₅ The method comprises the following steps:The voltage at the first end of the conversion resistor R2, i.e. the second voltage signal V2 is: The second voltage signal is followed by the voltage signal V3 after the driving capability is improved through the second operational amplifier module.

Taking the MBUS bus as an example, upon receiving data 0,the current IBUS is IMDC, and after receiving data 1, the current IBUS becomes imdc+ics, and at this time Δvbusn=ics×rsense is generated, corresponding toWhen this jump signal occurs, the difference detection module 3 is able to detect and generate a corresponding output.

Referring to fig. 9 and fig. 10, fig. 9 is a schematic structural diagram of a difference detection module in a receiving module according to the present utility model; fig. 10 is a schematic signal waveform diagram of a difference detection module according to the present utility model.

Taking the MBUS bus as an example, the difference detection module 3 may convert a jump signal into an output rail-to-rail digital signal. When the module starts to work, a set-up time is needed to charge the capacitor Css, and the voltage VCS at the first end of the capacitor Css can be stabilized to be fluctuated at a certain middle level; when the voltage V3 at the input end of the differential detection module 3 is at a lower level, due to the presence of the first unidirectional conduction module D1, the second unidirectional conduction module D2, and the third unidirectional conduction module D3, the voltage VCS at the first end of the capacitor Css will be discharged through R4, and the capacitance value of the capacitor Css is larger, the resistance value of the second discharge resistor R4 is also larger, the voltage drop at the end of the duration of this stage is smaller, the voltage V4 at the first input end of the differential amplifier 25 is discharged through R1, the resistance of R1 is smaller, the node capacitance is smaller, the discharge speed is very fast, and the discharge is always clamped to the voltage that is relatively larger of V3-Vd and VCS-Vd. When the voltage V3 at the input of the differential detection module 3 jumps from a lower level to a higher level, the voltage V4 node at the first input of the differential amplifier 25 can instantaneously respond and stabilize at the V3-Vd voltage, while the voltage VCS node at the first terminal of the capacitor Css needs to be charged due to the presence of the capacitor Css, and the voltage rise at the end of this phase duration is relatively small.

Because of the difference in time between the two voltage changes, one end is considered to be a real-time response signal change, and the other end is considered to be a level similar to a direct current state, and at the intermediate level of the jump signal, the voltage jump signal can be detected by the later comparator, and a corresponding output signal TXD is generated.

As a specific embodiment, please refer to fig. 11, fig. 11 is a schematic diagram of a pin of a host device of an MBUS system according to the present utility model; referring to fig. 12, fig. 12 is a schematic signal waveform diagram of a host device of an MBUS system according to the present utility model; referring to fig. 13, fig. 13 is a schematic diagram of signal waveforms of a host device of an MBUS system according to the present utility model in a transmission mode; in fig. 13, t1 and t2 represent a certain processing delay existing in practical application; referring to fig. 14, fig. 14 is a schematic signal waveform diagram of a host device of an MBUS system according to the present utility model in a receiving mode; in fig. 14, t3, t4 and t5 represent certain processing delays existing in practical applications.

As shown in fig. 11, fig. 11 provides an application pin arrangement for a host chip; pin 1 is CS pin, the I/O port is used, it is the connection port of difference detection circuit 23 and capacitor CSs, can choose to connect a 0.6 muF capacitor, connect to GND port again; pin 2 is TXD pin, the adopted O port is a data output port, and the default is high level when idle; pin 3 is NSLEEP pin, the I port is adopted, is a sleep mode control port, can be set up when receiving the low level signal, the host chip enters the sleep mode, can be connected with 520kΩ pull-down resistor in the chip while using; the pin 4 is an R/T pin, adopts an I port and is a working mode control port, and can be set to enter a receiving module when a host chip receives a low-level signal and enter a transmitting mode when the host chip receives a high-level signal, and can be connected with a 192k omega pull-up resistor in the chip when in application; pin 5 is RXD pin, I port is adopted, data input port is adopted, and the output signal of the processing module 31 is received in the transmitting mode, and is in high level when the processing module is generally idle; pin 6 is BUSN pin, the I port is adopted, is BUS BUS input end; pin 7 is the NFAULT pin, which is an OD gate and is the error output port; pin 8 is GND pin, which is the ground terminal; pin 9 is a VIO pin, which is the power port of the logic control module 11; pin 10 is a V3P3 pin, adopts an O port and is a voltage output port, and can output 3.3V voltage; pin 11 is VBB pin, is the power supply port; pin 12 is BUSP pin, the O port is adopted, and the output end of BUS BUS is adopted; pin 13 is a VB pin, is a power supply port, and VBB-VB is more than or equal to 12V; the EPAD is a schematic representation of the heat sink of the host chip being grounded.

Referring to fig. 15, fig. 15 is a schematic structural diagram of a host system of an MBUS system according to the present utility model. In order to solve the above technical problems, the present utility model further provides a host system of the MBUS system, which includes a processing module 31 and a host device 32 of the MBUS system as described above, where the processing module 31 is connected to the host device 32 of the MBUS system.

It will be appreciated that the utility model is not particularly limited herein with respect to the particular type and implementation of the processing module 31; there are also various options for the connection between the processing module 31 and the host device 32 of the MBUS system, and the present utility model is not limited herein, and may be selected according to practical application requirements. The BUS BUS can adopt common twisted pair wires, polarity is not needed to be distinguished when the BUS BUS is connected, wiring construction can be carried out according to any topological structure, the system wiring construction is simple, the expansion is flexible, and the construction cost and the difficulty are greatly reduced.

For an introduction of the host system of the MBUS system provided by the present utility model, refer to an embodiment of the host device of the MBUS system, and the disclosure is not repeated herein.

It should also be noted that in this specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present utility model. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the utility model. Thus, the present utility model is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. The host device of the MBUS system is characterized by comprising a tube shell, a logic control module, a transmitting module and a receiving module, wherein the logic control module, the transmitting module and the receiving module are packaged in the tube shell;

The logic control module is used for controlling the sending module and the receiving module based on the output signals of the processing module so that the host device enters different working modes, wherein the working modes comprise a sending mode and a receiving mode.

2. The host device of the MBUS system according to claim 1, characterized in that the transmitting module includes: the first switching tube, the second switching tube and the diode; the power supply comprises a first power supply and a second power supply;

the control end of the first switching tube and the control end of the second switching tube are respectively connected with the output end of the logic control module, the first end of the first switching tube is connected with the first power supply, the anode of the diode is connected with the second power supply, the cathode of the diode is connected with the first end of the second switching tube, the second end of the first switching tube is connected with the second end of the second switching tube, and the second switching tube is connected with the BUSP of the BUS through a transmitting pin.

3. The host device of the MBUS system according to claim 2, characterized in that the host device further comprises a power supply module; the input end of the power supply module is connected with the first power supply, and the output end is used as a voltage output pin; for powering external devices.

4. The host device of the MBUS system according to claim 1, characterized in that the host device further comprises a protection module and a protection switch; the input end of the protection module is respectively connected with the sending module and the receiving module, the output end of the protection module is respectively connected with the logic control module and the control end of the protection switch, the first end of the protection switch is grounded, and the second end of the protection switch is used as an error output pin;

5. The host device of the MBUS system according to claim 4, wherein the protection module includes an overcurrent protection circuit, an input end of the overcurrent protection circuit is connected to an output end of the transmission module, and the output end is connected to the logic control module and a control end of the protection switch, respectively.

6. The host device of the MBUS system according to claim 1, characterized in that the host device further comprises an oscillator, an output end of which is connected to the logic control module for outputting a preset oscillation signal.

7. The host device of the MBUS system according to any one of claims 1 to 6, characterized in that the receiving module comprises: the device comprises a detection resistor, a conversion module, a bias current module, a conversion resistor and a difference detection module;

The first end of the detection resistor is respectively connected with the input end of the conversion module and the BUS to be detected, the second end of the detection resistor is grounded, the output end of the conversion module is respectively connected with the output end of the bias current module, the first end of the conversion resistor is connected with the input end of the difference detection module, the second end of the conversion resistor is grounded, the output end of the difference detection module is used as the output end of the receiving module, and the BUS to be detected is BUSN of the BUS BUS;

8. The host device of the MBUS system according to claim 7, characterized in that the conversion module includes a first op-amp module and a following module;

9. The host device of the MBUS system according to claim 7, characterized in that the difference detection module includes: the device comprises a capacitor, a charging module, a discharging module and a differential amplifier;

The input end of the charging module is respectively connected with the output end of the conversion module, the output end of the bias current module is connected with the first end of the conversion resistor, the first output end of the charging module is respectively connected with the first end of the capacitor and the second input end of the differential amplifier, the second output end of the charging module is connected with the first input end of the differential amplifier, the second end of the capacitor is grounded, the discharging module is respectively connected with the first end of the capacitor and the second input end of the differential amplifier, and the output end of the differential amplifier is used as the output end of the receiving module;

10. A host system of an MBUS system, characterized by comprising a processing module and a host device of an MBUS system according to any one of claims 1-9, said processing module being connected to the host device of said MBUS system.