CN219066706U - Relay device - Google Patents

Abstract

The utility model provides a relay device, which comprises a light emitting element, a photoelectric conversion element, a transistor unit and a wire. The light emitting element is configured to emit a light signal. The photoelectric conversion element is configured to receive an optical signal and generate a voltage. The transistor cell is configured to be controlled by a voltage for switching operations. The conductive wire is electrically connected with the transistor unit. The transistor unit includes a silicon carbide substrate, a first metal layer, an insulating layer, and a second metal layer. The first metal layer is arranged on the silicon carbide substrate. The insulating layer is arranged on the first metal layer. The second metal layer is disposed on the insulating layer and is configured to be bonded with a wire.

Description

Relay device

technical field

The utility model relates to a relay device.

Background technique

In the current relay device, the surface of the transistor structure often has uneven pits, so many problems (such as uneven or voids in the interface metal layer (IMC)) often occur in the subsequent wiring, so that , will adversely affect the reliability of the relay device.

Utility model content

The utility model provides a relay device, the reliability of which can be effectively improved.

A relay device of the utility model comprises a light emitting element, a photoelectric conversion element, a transistor unit and a wire. The light emitting element is configured to emit a light signal. The photoelectric conversion element is configured to receive an optical signal and generate a voltage. The transistor unit is configured to switch under voltage control. The wires are electrically connected to the transistor units. The transistor unit includes a silicon carbide substrate, a first metal layer, an insulating layer and a second metal layer. The first metal layer is disposed on the silicon carbide substrate. The insulating layer is disposed on the first metal layer. The second metal layer is disposed on the insulating layer and configured to be bonded with wires.

In an embodiment of the present invention, the bonding interface between the above-mentioned second metal layer and the wire has a metal alloy layer.

In an embodiment of the present invention, the thickness of the above-mentioned metal alloy layer ranges from 1 micron to 5 microns.

In an embodiment of the present invention, the above-mentioned insulating layer includes an opening, and the second metal layer fills up the opening.

In an embodiment of the present invention, the above-mentioned second metal layer is electrically connected to the first metal layer through the insulating layer.

In an embodiment of the present invention, the above-mentioned second metal layer is in direct contact with the first metal layer.

In an embodiment of the present invention, the above-mentioned second metal layer covers the inner sidewall of the insulating layer.

In an embodiment of the present invention, the above-mentioned silicon carbide substrate is electrically connected to the wire through the first metal layer and the second metal layer.

In an embodiment of the present invention, there is no interface between the above-mentioned first metal layer and the second metal layer.

In an embodiment of the present invention, the above-mentioned transistor unit further includes a metal silicide layer disposed between the silicon carbide substrate and the first metal layer.

Based on the above, the relay device of the present invention improves the transistor unit, and introduces the design of the insulating layer and the second metal layer in the transistor unit to improve the surface flatness of the bonding interface of the welding pad metal layer for wire bonding, so The reliability of the relay device can be effectively improved.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.

Description of drawings

FIG. 1 is a schematic diagram of a relay device according to an embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view of the transistor unit area in FIG. 1 .

FIG. 3 is a schematic cross-sectional view of an intermediate process of manufacturing the transistor unit of FIG. 2 .

FIG. 4 is a schematic cross-sectional view of an alternative embodiment of FIG. 2 .

Detailed ways

Parts of the embodiments of the present invention will be described in detail with reference to the accompanying drawings. For the referenced element symbols in the following description, when the same element symbols appear in different drawings, they will be regarded as the same or similar elements. These embodiments are only a part of the utility model, and do not disclose all possible implementation modes of the utility model. More precisely, these embodiments are only examples in the patent application scope of the present utility model.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs.

Unless otherwise stated, the term "between" used in this specification to define a numerical range is intended to cover a range equal to and between the stated endpoint values, such as a size range between the first value and the second value Between means that the size range can cover the first value, the second value and any value between the first value and the second value.

FIG. 1 is a schematic diagram of a relay device according to an embodiment of the present invention. FIG. 2 is a schematic cross-sectional view of the transistor unit area in FIG. 1 . FIG. 3 is a schematic cross-sectional view of an intermediate process of manufacturing the transistor unit of FIG. 2 . FIG. 4 is a schematic cross-sectional view of an alternative embodiment of FIG. 2 .

Please refer to FIG. 1 and FIG. 2. In this embodiment, the relay device 10 includes a light emitting element 12, a photoelectric conversion element 14, a transistor unit 100, and a wire 16, wherein the light emitting element 12 is configured to emit a light signal, and the photoelectric conversion element 14 is configured to transmit an optical signal. The transistor unit 100 is configured to receive an optical signal and generate a voltage. The transistor unit 100 is configured to perform switching operation under the control of the voltage, and the wire 16 is electrically connected to the transistor unit 100 .

In addition, the transistor unit 100 includes a silicon carbide (SiC) substrate 110, a first metal layer 120, an insulating layer 130, and a second metal layer 140, wherein the first metal layer 120 is disposed on the SiC substrate 110, and the insulating layer 130 is disposed on the second metal layer 140. On the first metal layer 120 , the second metal layer 140 is disposed on the insulating layer 130 and configured to be bonded to the wire 16 . Accordingly, the relay device 10 of the present utility model improves the transistor unit 100, and introduces the design of the insulating layer 130 and the second metal layer 140 into the transistor unit 100, so as to improve the bonding interface of the bonding pad metal layer for wire bonding. The flatness of the surface, and thus the reliability of the relay device 10 can be effectively improved. Here, the wire 16 can be used for electrical connection between the transistor unit 100 and other components in the relay device 10 , which is not limited by the present invention.

Further, the bonding interface between the second metal layer 140 and the wire 16 has a metal alloy layer 18. For example, when the second metal layer 140 is made of aluminum and the wire 16 is made of gold, ultrasonic welding is performed during wire bonding. When gold and aluminum will interpenetrate and form a metal alloy layer 18 (eutectic interface metal layer) composed of gold and aluminum alloys, and in this embodiment, since the surface flatness of the joint interface is improved, the formed metal alloy layer can be improved. The thickness uniformity and continuity of the metal alloy layer 18 can effectively improve the reliability of the relay device 10 .

In some embodiments, the metal alloy layer 18 has a thickness ranging from 1 micron to 5 microns, wherein the thickness may be the distance from the bottom surface to the top surface, but the invention is not limited thereto.

In some embodiments, the transistor unit 100 can be a power MOSFET chip and is composed of multiple active cells. Generally speaking, the more active cells, the larger the area of the active area of the chip, and the higher the current that can be carried. In the current technology, in order to meet the requirements of the metal layer of the wire bonding interface, the part below the wire bonding is often removed at the wire bonding position to achieve a leveling effect, so the space for placing the active area will be lost. , it is necessary to increase the chip size and there will be a problem of high cost, and this problem will be more noticeable in silicon carbide chips with a high unit price. In this embodiment, the first metal layer 120, the insulating layer 130 and the second metal layer Layers 140 and other layers are superimposed on the silicon carbide substrate 110 to achieve a leveling effect, avoiding the method of sacrificing the active area by removing the part below the wire bonding, so the relay device 10 of this embodiment meets the wire bonding interface The requirement of the metal layer can be more advantageous in terms of cost at the same time.

In some embodiments, the light emitting element 12 is a light emitting diode (light emitting diode, LED), and can be connected to the input terminal T1 and the input terminal T2 of the relay 10 to receive a current signal, and generate a light signal according to the current signal (usually is infrared light). In addition, the photoelectric conversion element 14 includes a photodetector diode array (not shown), and is connected to the gate G of the transistor unit 100, and its drain D is connected to the output terminal T3 and the output terminal T4 of the relay 10, and the source The pole S will also extend outward to the ground terminal GND, so after the photodetection diode array of the photoelectric conversion element 14 receives the light signal from the light emitting element 12, a voltage change (that is, a voltage drop) will occur, which will affect the conduction of the transistor unit 100. On-state, and then control the current flowing through the transistor unit 100, but the present invention is not limited thereto.

In some embodiments, the transistor unit 100 may be fabricated, for example, by the following steps. First, please refer to FIG. 3 , a silicon carbide substrate 110 including a first-type doped region 112 and a second-type doped region 114 is provided, wherein the first-type doped region 112 may be an N-type doped region, and the second-type doped region The doped region 114 may be a P-type doped region, but the invention is not limited thereto. Here, it should be noted that other unillustrated regions (such as well regions) of the silicon carbide substrate 110 are required components that anyone with ordinary knowledge in the technical field can set according to actual design requirements, and will not repeat them here. . Next, the metal silicide layer 101 can be formed on the silicon carbide substrate 110, so the metal silicide layer 101 can be disposed between the silicon carbide substrate 110 and the first metal layer 120, wherein the metal silicide layer 101 can further improve the transistor unit 100's of performance. Then, suitable dielectric layer 102 , dielectric layer 103 , semiconductor layer 104 , dielectric layer 105 , first metal layer 120 and insulating layer 130 can be sequentially formed on the silicon carbide substrate 110 .

Afterwards, please refer to FIG. 2 , an opening can be formed in the insulating layer 130, and then a second metal layer 140 is formed on the silicon carbide substrate 110, so that the second metal layer 140 fills the opening of the insulating layer 130, so the second metal layer 140 The insulating layer 130 can be electrically connected to the first metal layer 120 , that is, the second metal layer 140 can be in direct contact with the first metal layer 120 , and the second metal layer 140 can cover the inner sidewall of the insulating layer 130 . After the above process, the fabrication of the transistor unit 100 of this embodiment can be substantially completed. Therefore, in this embodiment, the silicon carbide substrate 110 can be electrically connected to the wire 16 via the first metal layer 120 and the second metal layer 140, But the utility model is not limited thereto.

Further, in this embodiment, no further planarization process (such as CMP process) is performed after the insulating layer 130 is formed, so the top surface of the insulating layer 130 has a depression, but the utility model is not limited thereto, in an alternative embodiment Among them, as shown in FIG. 4 , after forming the insulating layer 130A of the transistor unit 100A, a planarization process (such as a CMP process) can be further performed, so that the second metal layer 140 subsequently formed thereon has better surface flatness. It should be noted that the planarization process is optional, that is, even without the planarization process, the surface flatness of the second metal layer 140 can be effectively improved by introducing the design of the insulating layer 130 .

In some embodiments, the dielectric layer 102, the dielectric layer 103, the dielectric layer 105, and the insulating layer 130 may be oxides, such as silicon oxide, the semiconductor layer 104 may be polysilicon, and the first metal layer 130 and the second metal layer 140 may be aluminum, but the present invention is not limited thereto, and the materials of the aforementioned film layers may be determined according to actual design requirements. Further, when both the first metal layer 130 and the second metal layer 140 are aluminum, there may be no interface between the first metal layer 130 and the second metal layer 140 .

It should be noted that the above-mentioned manufacturing process and the film layers shown in the accompanying drawings are only illustrative, and the present invention is not limited, as long as the transistor unit 100 of the relay device 10 includes a silicon carbide substrate 110, a first metal layer 120 , the insulating layer 130 and the second metal layer 140 all belong to the protection scope of the present invention.

To sum up, the relay device of the present invention improves the transistor unit, and introduces the design of the insulating layer and the second metal layer into the transistor unit, so as to improve the surface flatness of the bonding interface of the bonding pad metal layer for wire bonding , so the reliability of the relay device can be effectively improved.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present utility model, and are not intended to limit it; although the present utility model has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand : It is still possible to modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements to some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions depart from the various embodiments of the present invention Scope of technical solutions.

Claims (10)

1. A relay device, comprising:

a light emitting element configured to emit an optical signal;

a photoelectric conversion element configured to receive the optical signal and generate a voltage;

a transistor unit configured to perform a switching operation under the control of the voltage; and

the wire is electrically connected with the transistor unit, and the transistor unit comprises:

a silicon carbide substrate;

the first metal layer is arranged on the silicon carbide substrate;

an insulating layer arranged on the first metal layer; and

a second metal layer disposed on the insulating layer and configured to be bonded with the wire.

2. The relay device of claim 1, wherein the bonding interface of the second metal layer and the wire has a metal alloy layer.

3. The relay device of claim 2, wherein the metal alloy layer has a thickness ranging between 1 micron and 5 microns.

4. The relay device of claim 1, wherein the insulating layer includes an opening, and the second metal layer fills the opening.

5. The relay device of claim 1, wherein the second metal layer is electrically connected to the first metal layer through the insulating layer.

6. The relay device of claim 1, wherein the second metal layer is in direct contact with the first metal layer.

7. The relay device of claim 1, wherein the second metal layer covers an inner sidewall of the insulating layer.

8. The relay device of claim 1, wherein the silicon carbide substrate is electrically connected to the wire via the first metal layer and the second metal layer.

9. The relay device of claim 1, wherein the first metal layer and the second metal layer have no interface therebetween.

10. The relay device of claim 1, wherein the transistor cell further comprises a metal silicide layer disposed between the silicon carbide substrate and the first metal layer.

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