CN218006137U

CN218006137U - Laser scanning motor drive circuit and laser radar scanning system

Info

Publication number: CN218006137U
Application number: CN202222355780.4U
Authority: CN
Inventors: 张海武; 杨野; 疏达
Original assignee: Benewake Beijing Co Ltd
Current assignee: Benewake Beijing Co Ltd
Priority date: 2022-09-05
Filing date: 2022-09-05
Publication date: 2022-12-09
Anticipated expiration: 2032-09-05

Abstract

The application provides a laser scanning motor drive circuit and laser radar scanning system relates to laser scanning technical field. This application is through establishing ties each other with external working power supply's first power semiconductor device and grounded second power semiconductor device, by first, the power semiconductor device that second power drive circuit respectively connects or breaks off according to external pulse width modulation signal control connection under external power supply effect, make first bootstrap circuit can be according to the respective break-make situation of two power semiconductor devices, charge under external power supply effect, or directly supply power to first power semiconductor device through first power drive circuit, with drive control to target laser scanning motor, thereby carry out non-isolated bootstrap drive through the power semiconductor device to laser scanning motor, effectively reduce motor drive control circuit's occupation volume and realization cost, be convenient for laser radar scanning system's manufacturing, popularization and use.

Description

Laser scanning motor drive circuit and laser radar scanning system

Technical Field

The application relates to the technical field of laser scanning, in particular to a laser scanning motor driving circuit and a laser radar scanning system.

Background

With the continuous development of scientific technology, the application of laser scanning technology is becoming more extensive, wherein the construction and application of a laser radar scanning system are an important research direction of laser scanning technology. At present, for a laser radar scanning system, it is often necessary to provide a driving power source to a power Semiconductor device (e.g., a Metal-Oxide-Semiconductor Field-Effect Transistor (MOS) tube or an Insulated Gate Bipolar Transistor (IGBT)) used for driving a laser scanning motor (e.g., a mirror motor or a prism motor) of the laser radar scanning system by using an isolated power source chip, so that the isolated power source chip can isolate and drive the power Semiconductor device, and the power Semiconductor device achieves a driving control Effect on the laser scanning motor. It is worth noting that the existing isolation power supply chip has the problems of large size and high cost, so that the driving control circuit of the whole laser scanning motor has the phenomena of large occupied size and high implementation cost, and the manufacturing, popularization and use of a laser radar scanning system are not facilitated.

SUMMERY OF THE UTILITY MODEL

In view of this, an object of the present application is to provide a laser scanning motor driving circuit and a laser radar scanning system, which can perform non-isolated bootstrap driving on a power semiconductor device of a laser scanning motor through an integrated circuit, so as to effectively reduce the occupied volume and the implementation cost of a motor driving control circuit, and facilitate the manufacture, popularization and use of the corresponding laser radar scanning system.

In order to achieve the above purpose, the embodiments of the present application employ the following technical solutions:

in a first aspect, the present application provides a laser scanning motor driving circuit, which includes a first power driving circuit, a second power driving circuit, a first power semiconductor device, a second power semiconductor device, and a first bootstrap circuit;

the first power semiconductor device is externally connected with a working power supply, the second power semiconductor device is grounded, and an electric connection point between the first power semiconductor device and the second power semiconductor device which are connected in series with each other is electrically connected with a target laser scanning motor and is used for driving and controlling the target laser scanning motor;

the first power driving circuit is externally connected with a power supply and a first pulse width modulation signal, is electrically connected with the first power semiconductor device, and is used for controlling the first power semiconductor device to be switched on or switched off under the action of the power supply according to the first pulse width modulation signal;

the second power driving circuit is externally connected with the power supply and a second pulse width modulation signal, is electrically connected with the second power semiconductor device, and is used for controlling the second power semiconductor device to be switched on or switched off under the action of the power supply according to the second pulse width modulation signal;

the first bootstrap circuit is externally connected with the power supply and is electrically connected with the electric connection point and the first power driving circuit; the power supply is used for charging the first bootstrap circuit when the first power semiconductor device is switched off and the second power semiconductor device is switched on; the first bootstrap circuit supplies power to the first power semiconductor device through the first power driving circuit when the first power semiconductor device is turned on and the second power semiconductor device is turned off.

In an optional embodiment, in a case that the first power semiconductor device and the second power semiconductor device are respectively an N-channel MOS transistor or an N-channel IGBT transistor, a drain of the first power semiconductor device is externally connected to the operating power supply, a source of the first power semiconductor device is electrically connected to a drain of the second power semiconductor device, and a source of the second power semiconductor device is grounded, where the electrical connection point is located on an electrical connection line between the source of the first power semiconductor device and the drain of the second power semiconductor device;

the first input end of the first power driving circuit is externally connected with the power supply, the second input end of the first power driving circuit is externally connected with the first pulse width modulation signal, the first output end of the first power driving circuit is electrically connected with the grid electrode of the first power semiconductor device, and the second output end of the first power driving circuit is electrically connected with the source electrode of the first power semiconductor device;

the first input end of the second power driving circuit is externally connected with the power supply, the second input end of the second power driving circuit is externally connected with the second pulse width modulation signal, the first output end of the second power driving circuit is electrically connected with the grid electrode of the second power semiconductor device, and the second output end of the second power driving circuit is electrically connected with the source electrode of the second power semiconductor device.

In an alternative embodiment, each power driving circuit includes a first P-type semiconductor switching device, a second P-type semiconductor switching device, an N-type semiconductor switching device, a bias diode, a bias resistor, a protection capacitor, and a driving resistor;

a second input end of the power driving circuit is constructed by a P area terminal of the N-type semiconductor switching device through a driving resistor, a first N area terminal of the N-type semiconductor switching device is electrically connected with an N area terminal of the first P-type semiconductor switching device through a driving resistor, and a second N area terminal of the N-type semiconductor switching device is grounded;

the first P-region terminal of the first P-type semiconductor switching device is electrically connected with the N-region terminal of the first P-type semiconductor switching device through a bias resistor, wherein the first P-region terminal of the first P-type semiconductor switching device serves as a first input end of the power driving circuit;

the N-region terminal of the second P-type semiconductor switching device is electrically connected with the second P-region terminal of the first P-type semiconductor switching device, the N-region terminal of the second P-type semiconductor switching device is electrically connected with the anode of the bias diode, the cathode of the bias diode is electrically connected with the first P-region terminal of the second P-type semiconductor switching device through a bias resistor, and the N-region terminal of the second P-type semiconductor switching device is electrically connected with the second P-region terminal of the second P-type semiconductor switching device through a bias resistor;

one end of the protection capacitor is electrically connected with the first P-region terminal of the second P-type semiconductor switch device to construct a first output end of the power driving circuit, and the other end of the protection capacitor is electrically connected with the second P-region terminal of the second P-type semiconductor switch device to construct a second output end of the power driving circuit.

In an optional embodiment, when the signal delay of the pulse width modulation signal externally connected to the power driving circuit is greater than or equal to 2 μ s, both the first P-type semiconductor switching device and the second P-type semiconductor switching device included in the power driving circuit are PNP-type triodes, and the N-type semiconductor switching device included in the power driving circuit is an NPN-type triode;

under the condition that the signal time delay of a pulse width modulation signal externally connected with the power driving circuit is less than 2 mu s, a first P-type semiconductor switching device and a second P-type semiconductor switching device included in the power driving circuit are both P-channel MOS tubes, and an N-type semiconductor switching device included in the power driving circuit is an N-channel MOS tube.

In an optional embodiment, an input end of the first bootstrap circuit is externally connected to the power supply, a first output end of the first bootstrap circuit is electrically connected to a first input end of the first power driving circuit, and a second output end of the first bootstrap circuit is electrically connected to the electrical connection point.

In an optional embodiment, the first bootstrap circuit includes a first bootstrap diode, a first bootstrap capacitor, and a first bootstrap resistor;

an anode of the first bootstrap diode serves as an input terminal of the first bootstrap circuit;

the first bootstrap resistor and the first bootstrap capacitor are connected in parallel, a cathode of the first bootstrap diode is electrically connected with one end of the first bootstrap capacitor, the cathode of the first bootstrap diode serves as a first output end of the first bootstrap circuit, and the other end of the first bootstrap capacitor serves as a second output end of the first bootstrap circuit.

In an alternative embodiment, the motor drive circuit further comprises a phase current sampling circuit;

the electric connection point is electrically connected with the target laser scanning motor through the phase current sampling circuit, wherein the phase current sampling circuit is externally connected with the power supply and is used for carrying out phase current sampling processing on the target laser scanning motor.

In an optional embodiment, the motor driving circuit further includes a second bootstrap circuit, and the phase current sampling circuit includes an analog-to-digital conversion unit and a phase current sampling resistor;

the electric connection point is connected with the target laser scanning motor in series with the phase current sampling resistor, and two sampling ends of the analog-to-digital conversion unit are respectively connected with two ends of the phase current sampling resistor;

the input end of the second bootstrap circuit is externally connected with the power supply, the control end of the second bootstrap circuit is electrically connected with the electric connection point, and two output ends of the second bootstrap circuit are respectively electrically connected with two voltage input ends of the analog-to-digital conversion unit; wherein the power supply charges the second bootstrap circuit when the first power semiconductor device is turned off and the second power semiconductor device is turned on; the second bootstrap circuit supplies power to the analog-to-digital conversion unit when the first power semiconductor device is turned on and the second power semiconductor device is turned off.

In an optional embodiment, the second bootstrap circuit includes a second bootstrap diode, a second bootstrap resistor and a second bootstrap capacitor;

an anode of the second bootstrap diode serves as an input terminal of the second bootstrap circuit;

the second bootstrap resistor and the second bootstrap capacitor are connected in parallel, one end of the second bootstrap resistor is electrically connected to the cathode of the second bootstrap diode, the other end of the second bootstrap resistor serves as a control end of the second bootstrap circuit, and two ends of the second bootstrap capacitor serve as an output end of the second bootstrap circuit respectively.

In a second aspect, the present application provides a laser radar scanning system, the radar scanning system includes target laser radar and any one of the foregoing embodiments laser scanning motor drive circuit, laser scanning motor drive circuit with target laser scanning motor electric connection that target laser radar includes is used for right target laser scanning motor carries out drive control.

In this case, the beneficial effects of the embodiments of the present application may include the following:

according to the laser scanning system, the first power semiconductor device and the second power semiconductor device are connected in series, the first power semiconductor device is externally connected with a working power supply, the second power semiconductor device is grounded, the first power semiconductor device is controlled to be switched on or switched off by the first power driving circuit under the action of an external power supply according to an external first pulse width modulation signal, the second power semiconductor device is controlled to be switched on or switched off by the second power driving circuit under the action of an external power supply according to an external second pulse width modulation signal, a first bootstrap circuit which is connected with an electric connection point between the two power semiconductor devices and the first power driving circuit can be charged under the action of the external power supply or directly supplies power to the first power semiconductor device through the first power driving circuit, so that a target laser scanning motor electrically connected with the electric connection point is driven and controlled according to respective on-off conditions of the two power semiconductor devices, and accordingly, non-isolated driving can be performed on the power semiconductor devices of the laser scanning motor through an integrated circuit, the occupied volume of the motor driving control circuit is effectively reduced, the realization cost is convenient to manufacture, the bootstrap scanning system and the laser scanning system which is convenient to use.

In order to make the aforementioned objects, features and advantages of the present application more comprehensible, preferred embodiments accompanied with figures are described in detail below.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained from the drawings without inventive effort.

Fig. 1 is a schematic diagram of a laser scanning motor driving circuit according to an embodiment of the present disclosure;

fig. 2 is a schematic diagram illustrating a power driving circuit according to an embodiment of the present disclosure;

fig. 3 is a second schematic diagram illustrating a driving circuit of a laser scanning motor according to an embodiment of the present disclosure;

fig. 4 is a third schematic diagram illustrating a laser scanning motor driving circuit according to an embodiment of the present disclosure;

fig. 5 is a fourth schematic diagram illustrating a driving circuit of a laser scanning motor according to an embodiment of the present disclosure;

fig. 6 is a fifth schematic diagram illustrating a laser scanning motor driving circuit according to an embodiment of the present disclosure.

An icon: 10-laser scanning motor drive circuit; 11-a first power driver circuit; 12-a second power driving circuit; 13-a first power semiconductor device; 14-a second power semiconductor device; 15-a first bootstrap circuit; 16-phase current sampling circuit; 17-a second bootstrap circuit; 20-a target laser scanning motor; a 31-N type semiconductor switching device; 32-a first P-type semiconductor switching device; 33-a second P-type semiconductor switching device; 34-a biased diode; 35-a bias resistor; 36-a protection capacitance; 37-drive resistance; 151-a first bootstrap diode; 152-a first bootstrap capacitance; 153-a first bootstrap resistance; 161-analog-to-digital conversion unit; 162-phase current sampling resistance; 171-a second bootstrap diode; 172-a second bootstrap resistance; 173-second bootstrap capacitance.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.

Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without making any creative effort belong to the protection scope of the present application.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.

In the description of the present application, it is to be understood that relational terms such as the terms first and second, and the like, are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising one of 8230; \8230;" 8230; "does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises the element. The specific meaning of the above terms in this application will be understood to be a specific case for those of ordinary skill in the art.

In the description of the present application, it is further noted that, unless expressly stated or limited otherwise, the terms "disposed," "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in this application will be understood to be a specific case for those of ordinary skill in the art.

Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. The embodiments and features of the embodiments described below can be combined with each other without conflict.

Referring to fig. 1, fig. 1 is a schematic diagram illustrating a laser scanning motor driving circuit 10 according to an embodiment of the present disclosure. In the embodiment of the present application, laser scanning motor driving circuit 10 can carry out non-isolated bootstrap drive to the power semiconductor device of laser scanning motor through the integrated circuit, effectively reduces motor drive control circuit's occupation volume and realization cost, is convenient for correspond laser radar scanning system's manufacturing, popularization and use.

In this embodiment, the laser scanning motor driving circuit 10 may include a first power driving circuit 11, a second power driving circuit 12, a first power semiconductor device 13, a second power semiconductor device 14, and a first bootstrap circuit 15, where the first power semiconductor device 13 and the second power semiconductor device 14 are connected in series to form a bridge arm power control circuit, the bridge arm power control circuit is electrically connected to a target laser scanning motor 20 through an electrical connection point on an electrical connection line between the first power semiconductor device 13 and the second power semiconductor device 14, and the bridge arm power control circuit drives and controls the target laser scanning motor 20 during normal operation, and at this time, the electrical connection point may be regarded as a power output port of the bridge arm power control circuit. The target laser scanning motor 20 may be, but is not limited to, a galvanometer motor, a prism motor, etc.

The first power driving circuit 11 is configured to adjust a switching status of the first power semiconductor device 13, the second power driving circuit 12 is configured to adjust a switching status of the first power semiconductor device 13, the first bootstrap circuit 15 is configured to charge the second power semiconductor device 14 when the first power semiconductor device 13 is turned on and the second power semiconductor device 14 is turned off, and the first bootstrap circuit 15 is configured to supply power to the first power semiconductor device 13 when the first power semiconductor device 13 is turned on and the second power semiconductor device 14 is turned off, so that the bridge arm power control circuit performs drive control on the target laser scanning motor 20, thereby achieving a non-isolated bootstrap drive effect on the bridge arm power control circuit without using an isolation chip, effectively reducing an occupied volume and an implementation cost of the motor drive control circuit, and facilitating manufacture, popularization, and use of a corresponding laser radar scanning system.

In this embodiment, the first power semiconductor device 13 is externally connected to an operating power supply, and the second power semiconductor device 14 is grounded. The first power semiconductor device 13 may be an N-channel MOS transistor (including an enhancement MOS transistor and a depletion MOS transistor), or an N-channel IGBT; the second power semiconductor device 14 may be an N-channel MOS transistor (including an enhancement MOS transistor and a depletion MOS transistor), or an N-channel IGBT. A drain (i.e., a D port) of the first power semiconductor device 13 is externally connected to a working power supply (HVDD), a source (i.e., an S port) of the first power semiconductor device 13 is electrically connected to a drain (i.e., a D port) of the second power semiconductor device 14, a source (i.e., an S port) of the second power semiconductor device 14 is grounded, and at this time, an electrical connection point between the first power semiconductor device 13 and the second power semiconductor device 14 is located on an electrical connection line between the source (i.e., the S port) of the first power semiconductor device 13 and the drain (i.e., the D port) of the second power semiconductor device 14.

In this embodiment, the first power driving circuit 11 is externally connected to a power supply (i.e., VCC) and a first pwm signal, and is electrically connected to the first power semiconductor device 13, and configured to control the first power semiconductor device 13 to be turned on or off according to the first pwm signal under the action of the power supply. Wherein the first power semiconductor device 13 is controlled to be turned off by the first power driving circuit 11 when the signal level of the first pulse width modulation signal is a low level; when the signal level of the first pulse width modulation signal is at a high level, the first power semiconductor device 13 is controlled to be turned on by the first power driving circuit 11.

A first input end (i.e., the 1I port) of the first power driving circuit 11 is externally connected to the power supply (i.e., VCC), a second input end (i.e., the 2I port) of the first power driving circuit 11 is externally connected to the first pwm signal, a first output end (i.e., the 1O port) of the first power driving circuit 11 is electrically connected to a gate (i.e., the G port) of the first power semiconductor device 13, and a second output end (i.e., the 2O port) of the first power driving circuit 11 is electrically connected to a source (i.e., the S port) of the first power semiconductor device 13, so as to control the first power semiconductor device 13 to be turned on or off according to the first pwm signal.

In this embodiment, the second power driving circuit 12 is externally connected to the power supply (i.e. VCC) and a second pwm signal, and is electrically connected to the second power semiconductor device 14, for controlling the second power semiconductor device 14 to be turned on or off according to the second pwm signal under the action of the power supply. Wherein the second power semiconductor device 14 is controlled by the second power driving circuit 12 to be turned off when the signal level of the second pwm signal is at a low level; when the signal level of the second pwm signal is at a high level, the second power semiconductor device 14 is controlled to be turned on by the second power driving circuit 12.

The first input end (i.e., the 1I port) of the second power driving circuit 12 is externally connected to the power supply (i.e., VCC), the second input end (i.e., the 2I port) of the second power driving circuit 12 is externally connected to the second pwm signal, the first output end (i.e., the 1O port) of the second power driving circuit 12 is electrically connected to the gate (i.e., the G port) of the second power semiconductor device 14, and the second output end (i.e., the 2O port) of the second power driving circuit 12 is electrically connected to the source (i.e., the S port) of the second power semiconductor device 14, so as to control the second power semiconductor device 14 to be turned on or off according to the second pwm signal.

In this embodiment, the first bootstrap circuit 15 is externally connected to the power supply (i.e. VCC), and is electrically connected to the electrical connection point and the first power driving circuit 11, and is configured to perform charging under the action of the external power supply according to the on/off status of the first power semiconductor device 13 and the second power semiconductor device 14, or directly supply power to the first power semiconductor device 13 through the first power driving circuit 11, so as to drive the target laser scanning motor 20 to operate. When the first power semiconductor device 13 is turned off and the second power semiconductor device 14 is turned on, the power supply, the first bootstrap circuit 15 and the second power semiconductor device 14 form a current path, and at this time, the power supply is used for charging the first bootstrap circuit 15; when the first power semiconductor device 13 is turned on and the second power semiconductor device 14 is turned off, the first bootstrap circuit 15, the first power driving circuit 11, the first power semiconductor device 13, the electrical connection point, and the target laser scanning motor 20 form a current path, and at this time, the first bootstrap circuit 15 can supply power to the first power semiconductor device 13 through the first power driving circuit 11, so as to drive and control the target laser scanning motor 20 electrically connected to the electrical connection point.

The input end (i.e., the IN port) of the first bootstrap circuit 15 is externally connected to the power supply (i.e., VCC), the first output end (i.e., the 1O port) of the first bootstrap circuit 15 is electrically connected to the first input end (i.e., the 1I port) of the first power driving circuit 11, and the second output end (i.e., the 2O port) of the first bootstrap circuit 15 is electrically connected to the electrical connection point. Therefore, when the first bootstrap circuit 15 is IN the charging state, the second output terminal (i.e. the 2O port) of the first bootstrap circuit 15 may be regarded as being grounded, and at this time, the power supply may directly charge the first bootstrap circuit 15 through the input terminal (i.e. the IN port) of the first bootstrap circuit 15; when the first bootstrap circuit 15 is in an external discharge state, the first bootstrap circuit 15, the first power driving circuit 11, and the first power semiconductor device 13 form a loop, and at this time, the first output terminal (i.e., the 1O port) of the first bootstrap circuit 15 can directly supply power to the first power semiconductor device 13 through the first input terminal (i.e., the 1I port) and the first input terminal (i.e., the 1O port) of the first power driving circuit 11.

From this, the concrete constitution of laser scanning motor drive circuit 10 that this application accessible fig. 1 is shown utilizes the integrated circuit to replace current isolation power chip to carry out non-isolation formula bootstrapping drive to laser scanning motor's power semiconductor device, thereby effectively reduce motor drive control circuit's occupation volume and realization cost, be convenient for to correspond laser radar scanning system's manufacturing, popularization and use.

Optionally, referring to fig. 2, fig. 2 is a schematic composition diagram of a power driving circuit provided in an embodiment of the present application. In this embodiment, the first power driving circuit 11 and the second power driving circuit 12 may be formed by the same circuit configuration, where a single power driving circuit may include an N-type semiconductor switching device 31, a first P-type semiconductor switching device 32, a second P-type semiconductor switching device 33, a bias diode 34, a bias resistor 35, a protection capacitor 36, and a driving resistor 37, where the N-type semiconductor switching device is an electronic semiconductor switching device, which may be an NPN-type triode or an N-channel MOS transistor; the P-type semiconductor switch device is a hole-type semiconductor switch device, which can be a PNP type triode or a P-channel MOS tube.

In this embodiment, the P terminal (i.e., P port) of the N-type semiconductor switch device 31 constitutes the second input terminal (i.e., 2I port) of the corresponding power driving circuit via a driving resistor 37, the first N terminal (i.e., 1N port) of the N-type semiconductor switch device 31 is electrically connected to the N terminal (i.e., N port) of the first P-type semiconductor switch device 32 via a driving resistor 37, and the second N terminal (i.e., 2N port) of the N-type semiconductor switch device 31 is grounded.

The first P terminal (i.e., 1P port) of the first P-type semiconductor switch device 32 is electrically connected to the N terminal (i.e., N port) of the first P-type semiconductor switch device 32 through a bias resistor 35, wherein the first P terminal (i.e., 1P port) of the first P-type semiconductor switch device 32 serves as a first input terminal (i.e., 1I port) of the corresponding power driving circuit.

An N region terminal (i.e., N port) of the second P-type semiconductor switching device 33 is electrically connected to a second P region terminal (i.e., 2P port) of the first P-type semiconductor switching device 32, an N region terminal (i.e., N port) of the second P-type semiconductor switching device 33 is electrically connected to an anode of the bias diode 34, a cathode of the bias diode 34 is electrically connected to a first P region terminal (i.e., 1P port) of the second P-type semiconductor switching device 33 through a bias resistor 35, and an N region terminal (i.e., N port) of the second P-type semiconductor switching device 33 is electrically connected to a second P region terminal (i.e., 2P port) of the second P-type semiconductor switching device 33 through a bias resistor 35.

One end of the protection capacitor 36 is electrically connected to the first P region terminal (i.e. 1P port) of the second P-type semiconductor switch device 33 to construct a first output end (i.e. 1O port) of the corresponding power driving circuit; the other end of the protection capacitor 36 is electrically connected to the second P-region terminal (i.e. 2P port) of the second P-type semiconductor switch device 33 to construct a second output terminal (i.e. 2O port) of the corresponding power driving circuit. The protection capacitor 36 cooperates with the second P-type semiconductor switch device 33 to achieve an overvoltage protection effect on the power driving circuit.

In this embodiment, when the signal level of the pulse width modulation signal externally connected to a power driving circuit is low, the N-type semiconductor switching device 31 and the first P-type semiconductor switching device 32 included in the power driving circuit will be kept in an off state under the action of the corresponding external level, and at this time, the power driving circuit will correspondingly drive the power semiconductor device connected to the power driving circuit to be turned off; when the signal level of the pulse width modulation signal externally connected to a power driving circuit is at a high level, the N-type semiconductor switching device 31 and the first P-type semiconductor switching device 32 included in the power driving circuit will be kept in a conducting state under the action of the corresponding external level, and at this time, the power driving circuit will correspondingly drive the power semiconductor device connected to the power driving circuit to be conducted.

In this embodiment, if the N-type semiconductor switching device is an NPN-type transistor, the first N-region terminal (i.e., 1N port) of the N-type semiconductor switching device is a collector (i.e., a C-pole) of the NPN-type transistor, the P-region terminal (i.e., a P-port) of the N-type semiconductor switching device is a base (i.e., a B-pole) of the NPN-type transistor, and the second N-region terminal (i.e., 2N port) of the N-type semiconductor switching device is an emitter (i.e., an E-pole) of the NPN-type transistor;

if the N-type semiconductor switching device is an N-channel MOS transistor, the first N-region terminal (i.e., 1N-port) of the N-type semiconductor switching device is a drain (i.e., D-pole) of the N-channel MOS transistor, the P-region terminal (i.e., P-port) of the N-type semiconductor switching device is a gate (i.e., G-pole) of the N-channel MOS transistor, and the second N-region terminal (i.e., 2N-port) of the N-type semiconductor switching device is a source (i.e., S-pole) of the N-channel MOS transistor.

In this embodiment, if the P-type semiconductor switching device is a PNP type transistor, the first P-region terminal (i.e. 1P port) of the P-type semiconductor switching device is an emitter (i.e. E pole) of the PNP type transistor, the N-region terminal (i.e. N port) of the P-type semiconductor switching device is a base (i.e. B pole) of the PNP type transistor, and the second P-region terminal (i.e. 2P port) of the P-type semiconductor switching device is a collector (i.e. C pole) of the PNP type transistor;

if the P-type semiconductor switching device is a P-channel MOS transistor, the first P-region terminal (i.e., 1P port) of the P-type semiconductor switching device is a source (i.e., an S pole) of the P-channel MOS transistor, the N-region terminal (i.e., an N port) of the P-type semiconductor switching device is a gate (i.e., a G pole) of the P-channel MOS transistor, and the second P-region terminal (i.e., a 2P port) of the P-type semiconductor switching device is a drain (i.e., a D pole) of the P-channel MOS transistor.

In the embodiment of the present application, in the case that the signal delay of the pwm signal externally connected to a single power driver circuit is greater than or equal to 2 μ s, the first P-type semiconductor switching device 32 and the second P-type semiconductor switching device 33 included in the power driver circuit are both PNP-type transistors, and the N-type semiconductor switching device 31 included in the power driver circuit is an NPN-type transistor, so as to ensure that the operating condition of the power driver circuit substantially matches the signal delay of the connected pwm signal.

Under the condition that the signal time delay of a pulse width modulation signal externally connected with a single power driving circuit is less than 2 mu s, a first P-type semiconductor switching device 32 and a second P-type semiconductor switching device 33 included in the power driving circuit are both P-channel MOS tubes, and an N-type semiconductor switching device 31 included in the power driving circuit is an N-channel MOS tube, so that the operation condition of the power driving circuit is substantially matched with the signal time delay of the connected pulse width modulation signal.

In the embodiment of the present application, when the first power driving circuit 11 drives the first power semiconductor device 13 to be turned on and the first bootstrap circuit 15 is in an external discharging state, the first bootstrap circuit 15 will provide electric energy to the first power semiconductor device 13 through the first P-type semiconductor switch device 32, the bias diode 34 and the bias resistor 35 connected to the gate (i.e. G port) of the first power semiconductor device 13 of the first power driving circuit 11.

Optionally, referring to fig. 3, fig. 3 is a second schematic diagram of a laser scanning motor driving circuit 10 according to an embodiment of the present disclosure. In this embodiment, the first bootstrap circuit 15 may include a first bootstrap diode 151, a first bootstrap capacitor 152, and a first bootstrap resistor 153.

An anode of the first bootstrap diode 151 serves as an input terminal (i.e., an IN port) of the first bootstrap circuit 15, the first bootstrap resistor 153 and the first bootstrap capacitor 152 are connected IN parallel, a cathode of the first bootstrap diode 151 is electrically connected to one end of the first bootstrap capacitor 152, a cathode of the first bootstrap diode 151 serves as a first output terminal (i.e., a 1O port) of the first bootstrap circuit 15, and another end of the first bootstrap capacitor 152 serves as a second output terminal (i.e., a 2O port) of the first bootstrap circuit 15.

Therefore, when the first power semiconductor device 13 is turned off and the second power semiconductor device 14 is turned on, the first bootstrap circuit 15 is in a charging state, the power supply (i.e., VCC) can supply power to the turned-on second power semiconductor device 14 through the first bootstrap diode 151, the first bootstrap capacitor 152, and the electrical connection point, and transmit the power to the ground, and at this time, the first bootstrap capacitor 152 accumulates electric energy by the power supply.

When the first power semiconductor device 13 is turned on and the second power semiconductor device 14 is turned off, the first bootstrap circuit 15 is in an external discharge state, and the first bootstrap capacitor 152, which stores electric energy, supplies the electric energy to the first power semiconductor device 13 through the first P-type semiconductor switching device 32 of the first power driving circuit 11, the bias diode 34, and the bias resistor 35 connected to the gate (i.e., G-port) of the first power semiconductor device 13.

It can be understood that, when the first power semiconductor device 13 and the second power semiconductor device 14 are both in the off state, the first bootstrap circuit 15 is correspondingly in the internal discharging state, and the first bootstrap capacitor 152 storing the electric energy at this time is matched with the first bootstrap resistor 153 to form a self-return path, and the first bootstrap capacitor 152 discharges through the first bootstrap resistor 153.

In this process, the larger the capacitance value of the first bootstrap capacitor 152 is, the longer the chargeable time of the first bootstrap capacitor 152 is, and the smaller the voltage drop rate of the first bootstrap capacitor 152 during discharging is. The voltage value of the first bootstrap capacitor 152 during the charging period may reach VCC-0.7V, and the voltage value of the first bootstrap capacitor 152 during the discharging period may be maintained at a state of not less than 0.9 x (VCC-0.7V).

Therefore, the present application can implement the voltage bootstrap function of the first bootstrap circuit 15 through the specific composition of the first bootstrap circuit 15.

Optionally, referring to fig. 4, fig. 4 is a third schematic diagram of a composition of the laser scanning motor driving circuit 10 according to the embodiment of the present disclosure. In this embodiment, the laser scanning motor driving circuit 10 may further include a phase current sampling circuit 16, where the electrical connection point (i.e., the power output port of the bridge arm power control circuit) is electrically connected to the target laser scanning motor 20 through the phase current sampling circuit 16, and the phase current sampling circuit 16 is externally connected to the power supply (i.e., VCC) and is configured to perform phase current sampling processing on the target laser scanning motor 20 under the action of the power supply.

Optionally, referring to fig. 5, fig. 5 is a fourth schematic view of a composition of the laser scanning motor driving circuit 10 according to an embodiment of the present disclosure. In the embodiment of the present application, the phase current sampling circuit 16 may include an analog-to-digital conversion unit 161 and a phase current sampling resistor 162, and the laser scanning motor driving circuit 10 may further include a second bootstrap circuit 17 for the analog-to-digital conversion unit 161.

The electrical connection point is connected in series with the phase current sampling resistor 162 and connected to the target laser scanning motor 20, and two sampling ends of the analog-to-digital conversion unit 161 are respectively connected to two ends of the phase current sampling resistor 162, so as to directly perform phase current acquisition processing on the phase current sampling resistor 162 in a normal power supply state, thereby improving current sampling precision and current sampling efficiency.

An input end (i.e., an IN port) of the second bootstrap circuit 17 is externally connected to the power supply (i.e., VCC), a control end (i.e., a CON port) of the second bootstrap circuit 17 is electrically connected to the electrical connection point, and two output ends (i.e., a 1O port and a 2O port) of the second bootstrap circuit 17 are electrically connected to two voltage input ends of the analog-to-digital conversion unit 161, respectively.

When the first power semiconductor device 13 is turned off and the second power semiconductor device 14 is turned on, the power supply supplies power to the turned on second power semiconductor device 14 through the second bootstrap circuit 17 and the electrical connection point and transmits the power to the ground, and at this time, the second bootstrap circuit 17 is in a charging state, and the power supply charges the second bootstrap circuit 17.

When the first power semiconductor device 13 is turned on and the second power semiconductor device 14 is turned off, the second bootstrap circuit 17 and the analog-to-digital conversion unit 161 form a self-loop circuit, and at this time, the second bootstrap circuit 17 is in an external discharge state, and the second bootstrap circuit 17 supplies power to the analog-to-digital conversion unit 161.

Therefore, the phase current sampling circuit 16 can realize a non-isolated bootstrap driving effect through the second bootstrap circuit 17, so that the occupied volume and the realization cost of the motor driving circuit are further reduced, and the laser radar scanning system is convenient to manufacture, popularize and use.

It is understood that the analog-to-digital conversion unit 161 may be formed by connecting an LDO (Low Dropout regulator) regulator and an analog-to-digital converter in series, wherein the LDO regulator is provided as a front-end device of the analog-to-digital converter; the analog-to-digital conversion unit 161 may also be an analog-to-digital converter having the function of an LDO regulator.

Optionally, referring to fig. 6, fig. 6 is a fifth schematic diagram illustrating a composition of the laser scanning motor driving circuit 10 according to an embodiment of the present disclosure. In this embodiment, the second bootstrap circuit 17 may include a second bootstrap diode 171, a second bootstrap resistor 172 and a second bootstrap capacitor 173.

An anode of the second bootstrap diode 171 serves as an input end (i.e., an IN port) of the second bootstrap circuit 17, the second bootstrap resistor 172 and the second bootstrap capacitor 173 are connected IN parallel, one end of the second bootstrap resistor 172 is electrically connected to a cathode of the second bootstrap diode 171, the other end of the second bootstrap resistor 172 serves as a control end (i.e., a CON port) of the second bootstrap circuit 17, and two ends of the second bootstrap capacitor 173 respectively serve as an output end (i.e., a 1O port or a 2O port) of the second bootstrap circuit 17.

Thus, when the first power semiconductor device 13 is turned off and the second power semiconductor device 14 is turned on, the second bootstrap circuit 17 is in a charging state, the power supply (i.e., VCC) can supply power to the turned-on second power semiconductor device 14 through the second bootstrap diode 171, the second bootstrap capacitor 173, and the electrical connection point, and transmit the power to the ground, and at this time, the second bootstrap capacitor 173 accumulates electric energy by the power supply.

When the first power semiconductor device 13 is turned on and the second power semiconductor device 14 is turned off, the second bootstrap circuit 17 is in an external discharge state, the first bootstrap capacitor 152 storing the electric energy forms a self-circulation path with the analog-to-digital conversion unit 161, and at this time, the first bootstrap capacitor 152 directly provides the electric energy to the analog-to-digital conversion unit 161.

It can be understood that when the first power semiconductor device 13 and the second power semiconductor device 14 are both in the off state, the second bootstrap circuit 17 is in the internal discharging state, and the second bootstrap capacitor 173 storing the electric energy at this time cooperates with the second bootstrap resistor 172 to form a self-return path, and the second bootstrap capacitor 173 discharges through the second bootstrap resistor 172.

In this process, the larger the capacitance of the second bootstrap capacitor 173, the longer the chargeable time of the second bootstrap capacitor 173 is, and the smaller the voltage drop rate of the second bootstrap capacitor 173 when discharging. The voltage value of the second bootstrap capacitor 173 during the charging period may reach VCC-0.7V, and the voltage value of the second bootstrap capacitor 173 during the discharging period may be maintained at a state not lower than 0.9 × VCC-0.7V.

Therefore, the present application can implement the voltage bootstrap function of the second bootstrap circuit 17 through the specific composition of the second bootstrap circuit 17.

In this application, the embodiment of this application still provides a laser radar scanning system, laser radar scanning system includes target laser radar and the laser scanning motor drive circuit 10 of any one of the above-mentioned, laser scanning motor drive circuit 10 with the 20 electric connection of target laser scanning motor that target laser radar includes is used for right target laser scanning motor 20 carries out drive control, thereby realizes laser radar scanning system's laser scanning function.

In summary, in the laser scanning motor driving circuit and the laser radar scanning system provided in the embodiments of the present application, the first power semiconductor device and the second power semiconductor device are connected in series, so that the first power semiconductor device is externally connected to a working power supply, and the second power semiconductor device is grounded, then the first power driving circuit controls the first power semiconductor device to be turned on or off according to an externally connected first pulse width modulation signal under the action of an externally connected power supply, and the second power driving circuit controls the second power semiconductor device to be turned on or off according to an externally connected second pulse width modulation signal under the action of an externally connected power supply, so that a first bootstrap circuit connecting a power point between the two power semiconductor devices and the first power driving circuit can be charged under the action of the externally connected power supply according to respective on-off conditions of the two power semiconductor devices, or directly supplies power through the first power semiconductor device, so as to drive and control a target laser scanning motor electrically connected to the power semiconductor devices, thereby achieving the bootstrap driving of the laser scanning motor through the power semiconductor device, and achieving the effective volume reduction and the integration of the laser scanning system.

The above description is only for various embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of changes or substitutions within the technical scope of the present application, and all such changes or substitutions are included in the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A laser scanning motor driving circuit is characterized in that the motor driving circuit comprises a first power driving circuit, a second power driving circuit, a first power semiconductor device, a second power semiconductor device and a first bootstrap circuit;

the first power semiconductor device is externally connected with a working power supply, the second power semiconductor device is grounded, and an electric connection point between the first power semiconductor device and the second power semiconductor device which are mutually connected in series is electrically connected with a target laser scanning motor and is used for driving and controlling the target laser scanning motor;

2. The motor driving circuit according to claim 1, wherein in a case that the first power semiconductor device and the second power semiconductor device are N-channel MOS transistors or N-channel IGBT transistors, respectively, a drain of the first power semiconductor device is externally connected to the working power supply, a source of the first power semiconductor device is electrically connected to a drain of the second power semiconductor device, a source of the second power semiconductor device is grounded, and the electrical connection point is located on an electrical connection line between the source of the first power semiconductor device and the drain of the second power semiconductor device;

3. The motor drive circuit according to claim 2, wherein each power drive circuit includes a first P-type semiconductor switching device, a second P-type semiconductor switching device, an N-type semiconductor switching device, a bias diode, a bias resistor, a protection capacitor, and a drive resistor;

the N-region terminal of the second P-type semiconductor switch device is electrically connected with the second P-region terminal of the first P-type semiconductor switch device, the N-region terminal of the second P-type semiconductor switch device is electrically connected with the anode of the bias diode, the cathode of the bias diode is electrically connected with the first P-region terminal of the second P-type semiconductor switch device through a bias resistor, and the N-region terminal of the second P-type semiconductor switch device is electrically connected with the second P-region terminal of the second P-type semiconductor switch device through a bias resistor;

4. The motor driving circuit according to claim 3, wherein when the signal delay of the pulse width modulation signal externally connected to the power driving circuit is greater than or equal to 2 μ s, the first P-type semiconductor switching device and the second P-type semiconductor switching device included in the power driving circuit are both PNP-type transistors, and the N-type semiconductor switching device included in the power driving circuit is an NPN-type transistor;

under the condition that the signal time delay of a pulse width modulation signal externally connected with the power driving circuit is smaller than 2 mu s, a first P-type semiconductor switch device and a second P-type semiconductor switch device included by the power driving circuit are both P-channel MOS tubes, and an N-type semiconductor switch device included by the power driving circuit is an N-channel MOS tube.

5. The motor driving circuit according to claim 2, wherein an input terminal of the first bootstrap circuit is externally connected to the power supply, a first output terminal of the first bootstrap circuit is electrically connected to the first input terminal of the first power driving circuit, and a second output terminal of the first bootstrap circuit is electrically connected to the electrical connection point.

6. The motor drive circuit according to claim 5, wherein the first bootstrap circuit includes a first bootstrap diode, a first bootstrap capacitor, and a first bootstrap resistor;

7. The motor drive circuit according to any one of claims 1 to 6, further comprising a phase current sampling circuit;

8. The motor driving circuit according to claim 7, further comprising a second bootstrap circuit, wherein the phase current sampling circuit comprises an analog-to-digital conversion unit and a phase current sampling resistor;

the input end of the second bootstrap circuit is externally connected with the power supply, the control end of the second bootstrap circuit is electrically connected with the electric connection point, and two output ends of the second bootstrap circuit are respectively electrically connected with two voltage input ends of the analog-to-digital conversion unit; the power supply is used for charging the second bootstrap circuit when the first power semiconductor device is switched off and the second power semiconductor device is switched on; the second bootstrap circuit supplies power to the analog-to-digital conversion unit when the first power semiconductor device is turned on and the second power semiconductor device is turned off.

9. The motor drive circuit of claim 8, wherein the second bootstrap circuit comprises a second bootstrap diode, a second bootstrap resistor and a second bootstrap capacitor;

10. A laser radar scanning system, wherein the radar scanning system comprises a target laser radar and the laser scanning motor driving circuit of any one of claims 1 to 9, and the laser scanning motor driving circuit is electrically connected to a target laser scanning motor included in the target laser radar and configured to drive and control the target laser scanning motor.