CN216411817U - Liquid crystal display device with dot inversion - Google Patents

Abstract

The application discloses a liquid crystal display device with dot inversion, which comprises a plurality of data lines and a plurality of sub-pixels. Each sub-pixel comprises a first thin film transistor, a second thin film transistor and a capacitor which are sequentially arranged in different areas, the drain electrode of the first thin film transistor is connected with one end of the capacitor connected with an alternating current common voltage, and the first thin film transistor and the second thin film transistor are arranged in the same direction. The adjacent sub-pixels in the same row have the same structure, the adjacent sub-pixels in the same row have the inverted structure, and the source electrodes of the first and second thin film transistors of the sub-pixels in the same row are connected with the same data line. The second thin film transistor of the sub-pixel in the same row and odd column is connected with the first thin film transistor of the sub-pixel in the even column through a grid, and the first thin film transistor of the sub-pixel in the same row and odd column is connected with the second thin film transistor of the sub-pixel in the even column through a grid.

Description

Liquid crystal display device with dot inversion

technical field

The present application relates to a liquid crystal display device, and more particularly, to a liquid crystal display device with dot inversion.

Background technique

Existing methods for driving a liquid crystal display device include an alternating current common voltage (AC-Vcom) driving mode and a direct current common voltage (DC-Vcom) driving mode. In the DC common voltage driving mode, the magnitude of the common voltage (Vcom) is kept fixed, only by changing the magnitude of the data drive signal, for example, the magnitude of the common voltage is 5 volts (Voltage, V) and the difference between the data drive signal The size is 10V or 0V, which achieves the voltage difference (ie 5V) of the display electrode and the positive and negative polarity. In the AC common voltage driving mode, the magnitudes of the common voltage and the data driving signal are changed. For example, when the common voltage is 0V, the data driving signal is 5V or the data driving signal is 5V when the common voltage is 5V. It is 0V, and the voltage difference between the display electrodes (ie, 5V) and the positive and negative polarities can be achieved by the voltages between the two.

It can be seen from the above that the size of the data driving signal required by the DC common voltage driving mode is large, which means that the power consumption is also large, and the corresponding integrated circuit (Integrated Circuit, IC) design will also be more complicated. Therefore, the AC common voltage driving mode has better application advantages.

However, the reflective, micro-reflective or transflective display panel based on the AC common voltage driving mode can only realize frame inversion due to the limitation of the voltage of the data signal in the original pixel arrangement. With row inversion, it is easy for the human eye to detect obvious scan lines in the face of extremely low refresh rates.

Therefore, how to provide a liquid crystal display device based on the AC common voltage driving mode, which can achieve dot inversion with the best visual effect and eliminate the problem of visual reflection scanning pattern, is an urgent problem to be solved in the industry.

Utility model content

The main purpose of the present application is to provide a liquid crystal display device with dot inversion, which solves the problem that the liquid crystal display device based on the AC common voltage driving mode in the prior art has the problem of visual reflection scanning pattern when facing an extremely low refresh frequency. question.

In order to achieve the above purpose, this application is implemented as follows:

The present application provides a liquid crystal display device with dot inversion, comprising: M data lines, a plurality of sub-pixels, N first gate lines and N second gate lines, and the plurality of sub-pixels are arranged in M columns and N lines, M and N are positive integers. Each sub-pixel includes: a first thin film transistor disposed in a first area, a second thin film transistor disposed in a second area, and a capacitor disposed in a third area, wherein the second area is disposed in the first area and the third area In between, the arrangement direction of the first thin film transistor and the second thin film transistor is the same, the source of the first thin film transistor is electrically connected to the source of the second thin film transistor, the drain of the first thin film transistor is electrically connected to one end of the capacitor, the capacitor The other end is electrically connected to the AC common voltage. The arrangement structure of adjacent sub-pixels located in the same column is the same, and the arrangement structure of any sub-pixel located in the same row after being vertically flipped along the horizontal direction is the same as the arrangement structure of its adjacent sub-pixels. The source electrodes of the first thin film transistors and the source electrodes of the second thin film transistors of the sub-pixels located in the same column are connected to the same data line. The N first gate lines are used to respectively connect the gates of the second thin film transistors of the sub-pixels in the same row and the odd-numbered columns with the gates of the first thin-film transistors of the sub-pixels in the even columns, and the N second gate lines are used for The gates of the first thin film transistors of the sub-pixels in the odd-numbered columns and the gates of the second thin-film transistors of the sub-pixels in the even-numbered columns are respectively connected.

In this application, the liquid crystal display device with dot inversion is designed by the configuration layout of two-cut three sub-pixels (that is, each sub-pixel includes a first thin film transistor disposed in the first area, a second thin film disposed in the second area transistors and capacitors arranged in the third region, wherein the first thin film transistor and the second thin film transistor are arranged in the same direction), the arrangement structure of adjacent sub-pixels in the same column is the same, and the rows of adjacent sub-pixels in the same row are arranged in the same direction. The cloth structure is in an inverted configuration, so that the gates of the second thin film transistors of the sub-pixels in the same row and odd-numbered columns are connected to the gates of the first thin-film transistors of the sub-pixels in the even-numbered columns and the first thin film transistors of the sub-pixels in the same row and odd-numbered columns are connected. The gate of a thin film transistor is connected to the gate of the second thin film transistor of the even-numbered sub-pixels (the layout design of the gate line can shorten the length of the gate line and avoid the overlap between the gate lines ), in order to achieve the point inversion with the best visual effect in the AC common voltage driving mode with low frequency and low power consumption, which can improve the problem of visual reflection scanning pattern caused by low frequency driving, and does not increase the number of process channels and masks.

Description of drawings

The drawings described herein are used to provide further understanding of the present application and constitute a part of the present application. The schematic embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation of the present application. In the attached image:

FIG. 1 is a schematic layout diagram of an embodiment of a liquid crystal display device with dot inversion according to the present application;

Fig. 2 is a schematic cross-sectional view along line AA' of Fig. 1;

3 is a schematic diagram of waveforms of the AC common voltage and the gate driving signal of the liquid crystal display device with dot inversion of FIG. 1 during a frame period;

FIG. 4 is a schematic diagram of pixel polarities of an embodiment of the liquid crystal display device with dot inversion of FIG. 1 for displaying a frame of images;

FIG. 5 is a schematic diagram of pixel polarities of an embodiment of the liquid crystal display device with dot inversion of FIG. 1 to display another frame; and FIG.

FIG. 6 is a schematic layout diagram of another embodiment of the liquid crystal display device with dot inversion according to the present application.

Detailed ways

The embodiments of the present utility model will be described below with reference to the relevant drawings. In the figures, the same reference numbers refer to the same or similar components or method flows.

It must be understood that words such as "comprising" and "including" used in this specification are used to indicate the existence of specific technical features, values, method steps, operation processes, components and/or components, but do not exclude the possibility of Plus more technical features, values, method steps, job processes, components, components, or any combination of the above.

It must be understood that when an element is described as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, and intervening elements may be present. In contrast, when a component is described as being "directly connected" or "directly coupled" to another component, there are no intervening components present.

Please refer to FIG. 1 , which is a schematic layout diagram of an embodiment of a liquid crystal display device with dot inversion according to the present application. As shown in FIG. 1 , in this embodiment, the liquid crystal display device 100 with dot inversion includes: M data lines 110 , a plurality of sub-pixels 120 arranged in M columns and N rows, and N first gate lines 130 and N second gate lines 140, where M and N are positive integers. The liquid crystal display device 100 with dot inversion in FIG. 1 includes 8 sub-pixels 120 (ie, a 2×4 array, 4 columns and 2 rows, M is 4, and N is 2), 4 data lines 110 and 2 A first gate line 130 and two second gate lines 140 are taken as an example for description. The actual data lines 110, the number of the first gate line 130 and the second gate line 140, the number of the sub-pixels 120 and the Its arrangement can be adjusted according to actual needs. In addition, the plurality of sub-pixels 120 may be, but not limited to, reflective sub-pixels, but this embodiment is not intended to limit the present application; for example, the plurality of sub-pixels 120 may include micro-reflective sub-pixels, reflective sub-pixels Pixels, transflective sub-pixels, or a combination of the above. It should be noted that, in order to present the arrangement structure of the plurality of sub-pixels 120 , FIG. 1 omits drawing the substrate, organic layer, transparent conductive layer and reflective layer that the liquid crystal display device 100 with dot inversion may include.

In addition, four data lines 110, eight sub-pixels 120, two first gate lines 130 and two second gate lines 140 are disposed on the substrate. The substrate may include a flexible light-transmitting material, such as: acryl-based resin, methacryl-based resin, polyisoprene, vinyl-based resin -based resin), epoxy-based resin, urethane-based resin, siloxane-based resin, polyimide-based resin resin) or polyamide-based resin, or a rigid light-transmitting material, such as a glass substrate or a quartz substrate.

Please refer to FIGS. 1 and 2. FIG. 2 is a schematic cross-sectional view along line AA' of FIG. 1, wherein FIG. 2 is a cross-sectional view of the sub-pixel 120 of FIG. 1 along the vertical direction of the drawing of FIG. 1 according to an embodiment. As shown in FIGS. 1 and 2 , each sub-pixel 120 includes: a first thin film transistor 50 disposed in the first area 210 , a second thin film transistor 60 disposed in the second area 220 , and a capacitor disposed in the third area 230 70. In each sub-pixel 120, the second region 220 is disposed between the first region 210 and the third region 230, the arrangement direction of the first thin film transistor 50 and the second thin film transistor 60 are the same, and the first thin film transistor 50 includes a source electrode S1, the drain D1 and the gate G1, the second thin film transistor 60 includes a source S2, a drain D2 and a gate G2, the source S1 of the first thin film transistor 50 is electrically connected to the source S2 of the second thin film transistor 60, The drain D1 of the first thin film transistor 50 is electrically connected to one end of the capacitor 70 , and the other end of the capacitor 70 is electrically connected to the AC common voltage Vcom through the voltage line 10 . The arrangement direction of the first thin film transistor 50 is that the connection line between the source S1 and the drain D1 points to the capacitor 70, and the arrangement direction of the second thin film transistor 60 is that the connection line between the source S2 and the drain D2 points to the capacitance 70 direction.

In this embodiment, the plurality of sub-pixels 120 include a plurality of red sub-pixels, a plurality of green sub-pixels, and a plurality of blue sub-pixels, and each sub-pixel 120 is a bisected three sub-pixels (that is, each sub-pixel 120 It includes a first thin film transistor 50 disposed in the first area 210, a second thin film transistor 60 disposed in the second area 220, and a capacitor 70 disposed in the third area 230) for displaying grayscale images.

In each sub-pixel 120, the gate G1 and the gate G2 may be formed by the same patterned conductive layer, and the materials of the gate G1 and the gate G2 may include aluminum, platinum, silver, titanium, molybdenum, zinc, tin and/or combinations thereof, but not limited thereto. The source S1, the drain D1, the source S2, the drain D2, and the thin plate conductor 71 of the capacitor 70 connected to the drain D1 may be formed of the same patterned conductive layer, and may include the same pattern as the gate G1 and the gate G2 same or different material. In addition, the first thin film transistor 50 may further include a channel layer SE1 and a gate insulating layer GI1, and the second thin film transistor 60 may further include a channel layer SE2 and a gate insulating layer GI2; the channel layer SE1 and the channel layer SE2 may be patterned from the same layer The material of the channel layer SE1 and the channel layer SE2 can include silicon (for example: amorphous silicon, polysilicon, single crystal silicon), oxide semiconductor (for example: indium oxide, gallium oxide, zinc oxide, indium gallium oxide, Indium zinc oxide, indium tin oxide or indium gallium zinc oxide), organic semiconductor or other semiconductor materials; the dielectric DE of the capacitor 70, the gate insulating layer GI1 and the gate insulating layer GI2 can be formed by the same patterned conductive layer. For forming, the dielectric DE of the capacitor 70, the materials of the gate insulating layer GI1 and the gate insulating layer GI2 may include inorganic materials (eg, silicon nitride, silicon oxide, silicon oxynitride), organic materials (eg, polyimide Amine, polyester, polymethylmethacrylate (PMMA), poly(4-vinylphenol, PVP), polyvinyl alcohol (PVA), polytetrafluoroethene (PTFE) ), but not limited to this.

In one embodiment, the liquid crystal display device 100 with dot inversion may further include an organic layer OL, a transparent conductive layer PE and a reflective layer RE, and the organic layer OL is disposed on the first thin film transistor 50 , the second thin film transistor 60 and the capacitor 70 . A plurality of contact holes 90 are arranged on the upper surface, the transparent conductive layer PE is arranged on the organic layer OL, and the reflective layer RE is arranged on the transparent conductive layer PE and the arrangement position is the same as that of the transparent conductive layer PE. The material of the organic layer OL may include polyimide resin, epoxy resin or acrylic resin, the material of the transparent conductive layer PE may include indium tin oxide or indium zinc oxide, and the material of the reflective layer RE may include metal, Metal nitride or epoxy.

In one embodiment, the plurality of data lines 110 and the source S1 and the drain D1 of the first thin film transistor 50 and the source S2 and the drain D2 of the second thin film transistor 60 of each sub-pixel 120 can be made of the same The plurality of first gate lines 130 , the plurality of second gate lines 140 and the gate G1 of the first thin film transistor 50 of each sub-pixel 120 and the second thin film transistor The gate G2 of 60 may be formed by the same patterned conductive layer.

In one embodiment, the plurality of first thin film transistors 50 and the plurality of second thin film transistors 60 may be oxide thin film transistors or polysilicon thin film transistors, respectively.

In one embodiment, the plurality of capacitors 70 are respectively storage capacitors.

In this embodiment, the arrangement structure of adjacent sub-pixels 120 located in the same column is the same (that is, the arrangement structure of adjacent sub-pixels 120 in the vertical direction P in the drawing is the same), and any sub-pixel 120 located in the same row The arrangement structure after being vertically flipped along the horizontal direction H is the same as the arrangement structure of its adjacent sub-pixels 120 (that is, in the sub-pixels 120 in the same row, the arrangement structure of any sub-pixel 120 is that the adjacent sub-pixels 120 have the same arrangement structure. The arrangement structure of 120 is reversed by 180 degrees, so that in the sub-pixels 120 in the same row, the first area 210 of any sub-pixel 120 is side by side with the third area 230 of the adjacent sub-pixel 120, and the adjacent sub-pixels 120 are arranged side by side. The second regions 220 of the sub-pixels 120 are arranged side by side, the arrangement direction of the first thin film transistors 50 of any sub-pixel 120 is opposite to the arrangement direction of the first thin-film transistors 50 of the adjacent sub-pixels 120, and the second thin film transistors 50 of any sub-pixel 120 The arrangement direction of the thin film transistors 60 is opposite to the arrangement direction of the second thin film transistors 60 of the adjacent sub-pixels 120 ), the source S1 of the first thin film transistor 50 and the source of the second thin film transistor 60 of the sub-pixels 120 located in the same column The pole S2 is connected to the same data line 110 .

In this embodiment, the two first gate lines 130 are used to connect the gates G2 of the second thin film transistors 60 of the sub-pixels 120 in the same row and the odd-numbered columns and the first thin-film transistors 50 of the sub-pixels 120 in the even columns, respectively. The gate G1; two second gate lines 140 are used to respectively connect the gate G1 of the first thin film transistor 50 of the sub-pixels 120 in the same row and odd-numbered columns and the second thin-film transistors 60 of the sub-pixels 120 in the even-numbered columns. Gate G2. The two first gate lines 130 may be the first control line 310 and the fourth control line 340 respectively, and the two second gate lines 140 may be the second control line 320 and the third control line 330 respectively.

In one embodiment, the two first gate lines 130 and the two second gate lines 140 are arranged in a detour manner (as shown in FIG. 1 ).

In one embodiment, two adjacent sub-pixels 120 located in the same column form a unit 80 , and the liquid crystal display device 100 with dot inversion includes a plurality of units 80 arranged in an array.

In one embodiment, the liquid crystal display device 100 with dot inversion may further include: a gate driving circuit 150 , a data driving circuit 160 and a common voltage generating circuit 170 , and the gate driving circuit 150 is electrically connected to the two first gates The line 130 and the two second gate lines 140 are used to respectively provide four gate driving signals to the two first gate lines 130 and the two second gate lines 140 (specifically, the gate driving circuit 150 depends on the The gate driving signal is output to the two first gate lines 130 and the two second gate lines 140 respectively at the preset timing, please refer to the related description of FIG. 3 for details); the data driving circuit 160 is electrically connected to the four data lines The lines are used to respectively provide four data driving signals to the four data lines; the common voltage generating circuit 170 is electrically connected to the plurality of capacitors 70 through the voltage lines 10 to provide the AC common voltage Vcom. It should be noted that, the voltage line 10 , the first gate line 130 and the second gate line 140 are the wiring configurations of different metal layers in the manufacturing process. In an example, the gate driving circuit 150 may include a plurality of sub-gate driving circuits (not shown), which are respectively disposed on one side, two sides or around the liquid crystal display device 100 with dot inversion, that is, the gate The driver circuit 150 may be in a distributed configuration.

Please refer to FIG. 1 and FIG. 3 . FIG. 3 is a schematic diagram of waveforms of the AC common voltage and the gate driving signal of the liquid crystal display device with dot inversion in FIG. 1 during one frame. As shown in FIG. 3 , the AC common voltage Vcom is transposed every half frame period; the first control line 310 , the second control line 320 , the third control line 330 and the fourth control line 340 are in sequence Turn on (ie, the first control line 310 , the second control line 320 , the third control line 330 and the fourth control line 340 receive the gate driving signal in sequence). It should be noted that the data driving signal Data received by the data line 110 is the same as the data of the existing liquid crystal display device (in the existing liquid crystal display device, the circuit layout of all adjacent sub-pixels is the same) driven by the AC common voltage Vcom. The driving signals are the same, so they are not described here. The first control line 310 and the second control line 320 receive the gate driving signal during the period when the AC common voltage Vcom is at a low voltage, so that the second thin film transistor 60 connected to the first control line 310 and the first thin film transistor 50 and The connected capacitor 70, the second thin film transistor 60 connected to the second control line 320, the first thin film transistor 50 and the connected capacitor 70 are lit based on the received data driving signal Data; when the AC common voltage Vcom is high During the voltage period, the third control line 330 and the fourth control line 340 receive the gate driving signal, so that the second thin film transistor 60 and the first thin film transistor 50 connected to the third control line 330 and the capacitor 70 connected to the third control line 330 and the fourth thin film transistor 50 The second thin film transistor 60 and the first thin film transistor 50 connected to the control line 340 and the capacitor 70 connected thereto are lit up based on the received data driving signal Data, therefore, dot inversion with the best visual effect can be achieved.

Through the configuration layout design of the two-cut three sub-pixels and the routing layout design of the gate lines shown in FIG. 1, combined with the low-frequency AC common voltage driving mode and the turn-on sequence of the control lines shown in FIG. 3, each sub-pixel 120 can be The polarity of the first area 210 is the same as the polarity of the third area 230, and the polarity of the first area 210 and the third area 230 of each sub-pixel 120 is opposite to that of the second area 220, as shown in FIG. 4 or FIG. 5 (FIG. 4 is a schematic diagram of an example pixel polarity of the liquid crystal display device with dot inversion in FIG. 1 displaying one frame of picture, and FIG. 5 is the liquid crystal display device with dot inversion in FIG. 1 displaying another frame of picture. Schematic diagram of pixel polarity in an embodiment example). Therefore, the liquid crystal display device 100 with dot inversion of FIG. 1 can realize dot inversion under the premise of a low-power display panel structure that uses two-cut three sub-pixels to display grayscale images and a low-frequency AC common voltage, which can improve low-frequency driving. visual scan pattern problem.

Please refer to FIG. 6 , which is a schematic layout diagram of another embodiment of the liquid crystal display device with dot inversion according to the present application. As shown in FIG. 6 , the difference between the liquid crystal display device 200 with dot inversion in this embodiment and the liquid crystal display device 100 with dot inversion in FIG. 1 is that the two first gate lines 430 in this embodiment are The two second gate lines 440 are arranged in a straight line. Specifically, the arrangement directions of the first thin film transistors 50 and the second thin film transistors 60 along two sides of the two first gate lines 430 and the two second gate lines 440 are opposite, by increasing the The method of the area of the gate and the area of the gate of the second thin film transistor 60 (that is, increasing the area of the black area corresponding to the first thin film transistor 50 and the second thin film transistor 60 in the drawing), so that two first gates The line 430 and the two second gate lines 440 can be configured in a non-circumferential manner, which can shorten the length of the first gate line 430 and the second gate line 440 .

To sum up, the liquid crystal display device with dot inversion according to the embodiments of the present application is designed by the configuration layout of the three sub-pixels in two (that is, each sub-pixel includes a first thin film transistor disposed in the first area, a The second thin film transistor in the area and the capacitor arranged in the third area, wherein the arrangement direction of the first thin film transistor and the second thin film transistor is the same), the arrangement structure of the adjacent sub-pixels in the same column is the same, and the adjacent sub-pixels in the same row are adjacent to each other. The arrangement structure of the sub-pixels is in a reverse configuration, so that the gates of the second thin film transistors of the sub-pixels in the same row and odd-numbered columns are connected to the gates of the first thin-film transistors of the sub-pixels in the even-numbered columns and are located in the same row and odd-numbered columns. The gates of the first thin film transistors of the sub-pixels are connected to the gates of the second thin film transistors of the even-numbered sub-pixels (the layout design of the gate lines can shorten the length of the gate lines, and avoid the gap between the gate lines. In order to realize the point inversion in the AC common voltage driving mode with low frequency and low power consumption, the problem of visual reflection scanning pattern caused by low frequency driving can be improved (that is, the visual reflection pattern can be directly eliminated in the circuit layout design. depending on the reflection scan pattern). In addition, the configuration layout design and wiring layout design of the sub-pixels in the embodiments of the present application are the same as the existing array mask manufacturing process, so the number of process lanes and the number of masks are not increased.

Although the above-described components are included in the drawings of the present application, it is not excluded that more other additional components can be used to achieve better technical effects without violating the spirit of the present invention.

Although the present invention is described by using the above embodiments, it should be noted that these descriptions are not intended to limit the present invention. On the contrary, this invention covers modifications and similar arrangements apparent to those skilled in the art. Therefore, the scope of the claims is to be construed in the broadest manner so as to encompass all obvious modifications and similar arrangements.

Claims (9)

1. A liquid crystal display device with dot inversion, characterized in that, comprising: M data lines, M is a positive integer; a plurality of sub-pixels, arranged in M columns and N rows, each of the plurality of sub-pixels includes: a first thin film transistor disposed in the first region, a second thin film transistor disposed in the second region, and a third thin film transistor disposed in the third region capacitance; in each of the plurality of sub-pixels, the second region is disposed between the first region and the third region, the first thin film transistor and the second thin film transistor The arrangement direction is the same, the source of the first thin film transistor is electrically connected to the source of the second thin film transistor, the drain of the first thin film transistor is electrically connected to one end of the capacitor, and the other end of the capacitor Electrically connected to the AC common voltage; wherein, the arrangement structure of adjacent sub-pixels located in the same column is the same, and the arrangement structure of any sub-pixel located in the same row is vertically flipped along the horizontal direction and the arrangement of its adjacent sub-pixels The structure is the same; the multiple sources of the multiple first thin film transistors of the multiple sub-pixels located in the same column and the multiple source electrodes of the multiple second thin film transistors are connected to the same data line, N is a positive integer; The N first gate lines are used to respectively connect the gates of the second thin film transistors of the sub-pixels in the odd-numbered columns in the same row and the gates of the sub-pixels in the even-numbered columns. a plurality of gates of the first thin film transistor; and N second gate lines for connecting the gates of the first thin film transistors of the sub-pixels in the odd-numbered columns in the same row and the gates of the sub-pixels in the even-numbered columns respectively a plurality of gates of the second thin film transistor. 2 . The liquid crystal display device with dot inversion according to claim 1 , wherein the N first gate lines and the N second gate lines are arranged in a detour manner. 3 . 3 . The liquid crystal display device with dot inversion according to claim 1 , wherein the N first gate lines and the N second gate lines are arranged in a straight line. 4 . 4 . The liquid crystal display device with dot inversion according to claim 1 , wherein two adjacent sub-pixels located in the same row constitute a unit, and the liquid crystal display device with dot inversion comprises an array arranged in an array. 5 . A plurality of said units of cloth. 5. The liquid crystal display device with dot inversion according to claim 1, wherein the liquid crystal display device with dot inversion further comprises: A gate driving circuit, electrically connecting the N first gate lines and the N second gate lines, for respectively providing 2N gate driving signals to the N first gate lines and the N second gate lines the N second gate lines; a data driving circuit, electrically connected to the M data lines, for respectively providing M data driving signals to the M data lines; and The common voltage generating circuit is electrically connected to a plurality of the capacitors for providing the AC common voltage. 6 . The liquid crystal display device with dot inversion according to claim 1 , wherein the plurality of first thin film transistors and the plurality of second thin film transistors are respectively oxide thin film transistors or polysilicon thin film transistors. 7 . 7 . The liquid crystal display device with dot inversion according to claim 1 , wherein the plurality of capacitors are respectively storage capacitors. 8 . 8 . The liquid crystal display device with dot inversion according to claim 1 , wherein the plurality of sub-pixels comprise micro-reflective sub-pixels, reflective sub-pixels, transflective sub-pixels, or the aforementioned sub-pixels. 9 . combination. 9 . The liquid crystal display device with dot inversion according to claim 1 , wherein, in each of the plurality of sub-pixels, the polarity of the first region and the polarity of the third region are different. 10 . Likewise, the polarities of the first region and the third region are opposite to the polarities of the second region.

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