CN203951451U - A kind of circuit that detects clock source failure - Google Patents

Abstract

The utility model discloses a circuit for detecting clock source faults, which comprises: a first timer for cycle timing, the timing period of the first timer is greater than or equal to the clock period of a low-frequency pulse signal; The first register connected to the timer, the first register is used to latch the low-frequency pulse signal generated by the clock source at the start timing point of each timing cycle; the detection unit connected to the clock source, the first timer and the first register respectively; the detection unit It is used to detect whether the current low-frequency pulse signal generated by the clock source is always the same as the latched low-frequency pulse signal within the timing period; if so, output the first indication signal to indicate that the low-frequency pulse signal is lost; if not, The second indication signal is output to indicate that the low-frequency pulse signal is not lost. The utility model realizes the detection of whether the clock source fails by determining whether the low-frequency pulse signal is lost.

Description

A circuit for detecting clock source failure

technical field

The utility model relates to the technical field of electric power automation, in particular to a circuit for detecting clock source faults. the

Background technique

In the field of power automation technology, communication equipment generally transmits information through pulse signals. For a certain communication equipment, there are generally multiple clock sources. If the currently used clock source fails, it can Switch to another backup clock source. the

From the above description, it can be seen that whether the currently used clock source fails has become an important issue for the normal operation of communication equipment. Therefore, how to detect the clock source to ensure its performance is an urgent technical problem to be solved by those skilled in the art. . the

Utility model content

In view of this, the utility model provides a circuit for detecting a clock source failure, so as to detect whether the currently used clock source fails. the

In order to achieve the above object, the utility model provides the following technical solutions:

A circuit for detecting a clock source failure, the clock source is used to generate a low-frequency pulse signal, the circuit includes:

A first timer for cycle timing, the timing period of the first timer is greater than or equal to the clock period of the low-frequency pulse signal;

A first register connected to the clock source and the first timer respectively, the first register is used to latch the low-frequency pulse signal generated by the clock source at the start timing point of each timing cycle;

A detection unit connected to the clock source, the first timer and the first register respectively;

Wherein, the detection unit is used to detect whether the current low-frequency pulse signal generated by the clock source is always the same as the latched low-frequency pulse signal within the timing period; if so, output a first indication signal, and the first indication signal It is used to indicate that the low-frequency pulse signal is lost; if not, a second indication signal is output, and the second indication signal is used to indicate that the low-frequency pulse signal is not lost. the

Preferably, the detection unit includes:

A logic circuit in which the first input end is connected to the clock source and the second input end is connected to the first register, and the logic circuit is used to compare the current low-frequency pulse signal generated by the clock source with the latched low-frequency pulse Whether the signals are the same, and output the first signal according to the comparison result;

The second register connected to the output terminal of the logic circuit and the first timer respectively, the output signal of the second register is set as the second signal when the timing point of each timing cycle is started;

The second register is used to output a third signal when it is recorded that the first signal output by the logic circuit is different from the latched low-frequency pulse signal during the timing period; It is recorded that the first signal output by the logic circuit is used to always indicate that the current low-frequency pulse signal is the same as the latched low-frequency pulse signal, and keep outputting the second signal;

The third register connected to the first timer and the second register is used to latch the signal output by the second register at the start timing point of each timing cycle, and when the latched signal is When the signal is the second signal, the first indication signal is output, and when the latched signal is the third signal, the second indication signal is output. the

Preferably, it also includes a second timer connected to the detection unit;

The second timer is used to start timing when the detection unit outputs the first indication signal;

When the detection unit outputs the second indication signal, it is cleared. the

Preferably, the logic circuit is an XOR gate logic circuit;

When the current low-frequency pulse signal is the same as the latched low-frequency pulse signal, the first signal is a low-level signal;

When the current low-frequency pulse signal is different from the latched low-frequency pulse signal, the first signal is a high-level signal;

The second signal is a high level signal; the third signal is a low level signal;

Or, the logic circuit is an NOR gate logic circuit;

When the current low-frequency pulse signal is the same as the latched low-frequency pulse signal, the first signal is a high-level signal;

When the current low-frequency pulse signal is different from the latched low-frequency pulse signal, the first signal is a low-level signal;

The second signal is a low level signal; the third signal is a high level signal. the

A circuit for detecting a clock source failure, including a processor, the processor has an input terminal and an output terminal, the input terminal is used to be connected to the clock source, and the clock source is used to generate a low-frequency pulse signal; the The output terminal is used to output the indication signal;

The processor is used to latch the low-frequency pulse signal generated by the clock source at the start timing point of each timing cycle; and detect whether the current low-frequency pulse signal generated by the clock source is consistent with the latched low-frequency pulse signal within the timing cycle. The pulse signals are the same; if so, output a first indication signal, and the first indication signal is used to indicate that the low-frequency pulse signal is lost; if not, output a second indication signal, and the second indication signal is used to indicate that the low-frequency pulse signal is lost. The pulse signal is not lost;

Wherein, the timing period is greater than or equal to the clock period of the low-frequency pulse signal. the

Preferably, the first indication signal output by the processor is specifically:

The processor outputs a first indication signal when the current low-frequency pulse signal generated by the clock source lasts for the same time as the latched low-frequency pulse signal for a preset time. the

It can be known from the above technical solutions that, compared with the prior art, the embodiment of the present invention discloses a circuit for detecting clock source faults, including a processor, the input end of the processor is used to connect with the clock source, and the output end is used to In outputting the indication signal, by latching the low-frequency pulse signal generated by the clock source at the start timing point of each timing cycle; and in the timing cycle, detecting whether the current low-frequency pulse signal generated by the clock source is always consistent with the The low-frequency pulse signals are the same; if so, output a first indication signal, the first indication signal is used to indicate that the low-frequency pulse signal is lost, and when the low-frequency pulse signal is lost, it can be determined that the clock source has failed; if not, output The second indication signal, the second indication signal is used to indicate that the low-frequency pulse signal is not lost. When the low-frequency pulse signal is not lost, it can be determined that the clock source has not failed. It can be seen that the utility model determines Whether the low-frequency pulse signal is lost realizes the detection of whether the clock source fails. the

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the accompanying drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description It is only an embodiment of the utility model, and those skilled in the art can also obtain other drawings according to the provided drawings without creative work. the

Fig. 1 is a schematic structural diagram of an embodiment of a circuit for detecting a clock source failure disclosed in an embodiment of the present invention;

Fig. 2 is a schematic structural diagram of another embodiment of a circuit for detecting a clock source failure disclosed in an embodiment of the present invention;

Fig. 3 is a schematic structural diagram of another embodiment of a circuit for detecting a clock source failure disclosed in an embodiment of the present invention;

FIG. 4 is a schematic structural diagram of an embodiment of another circuit for detecting a clock source failure disclosed in an embodiment of the present invention. the

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. example. Based on the embodiments of the present utility model, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the scope of protection of the present utility model. the

The utility model discloses a circuit for detecting the failure of a clock source, wherein the clock source is the current clock source of communication equipment and is used to generate a low-frequency pulse signal. The utility model does not limit the clock frequency of the low-frequency pulse signal, for example, The low-frequency pulse signal can be a second pulse signal. the

As shown in Figure 1, the circuit may include: a first timer 200, a first register 300, and a detection unit 400, wherein:

The first timer 200 is used for cyclic timing, wherein the timing period of the first timer is greater than or equal to the clock period of the low-frequency pulse signal; The sum of the maximum frequency offsets generated by the clock source can be specifically set according to actual conditions, and the present invention does not limit it. the

For example, the clock period of the low-frequency pulse signal is 1 second, and the maximum frequency deviation allowed by the clock source is 10% of the clock period, then the timing period is 1.1 seconds. the

The first register 300 is connected with the first timer 200 and the clock source respectively, and the first register is used for latching the low-frequency pulse signal produced by the clock source at the start timing point of each timing cycle; The low-frequency pulse signal generated by the clock source is latched at the start timing point of each timing cycle of the timer. the

The detection unit 400 is connected to the first timer 200, the first register 300 and the clock source respectively;

Wherein, after the first register latches the low-frequency pulse signal generated by the clock source, it will send the latched low-frequency pulse signal to the detection unit; and the detection unit is used to detect whether the current low-frequency pulse signal generated by the clock source is It is always the same as the latched low-frequency pulse signal; if yes, output the first indication signal; if not, output the second indication signal. the

It should be noted that the clock source will not lose the low-frequency pulse signal in the normal working state, that is, in the case of no failure, that is, the clock source will generate a low-level pulse signal and a high-level pulse signal in each clock cycle. pulse signal; then, the current low-frequency pulse signal will not always be the same as the latched low-frequency pulse signal, and may be different from the latched low-frequency pulse signal. the

For example, in a certain clock cycle, the latched low-frequency pulse signal is a low-level pulse signal, and in this clock cycle, the current low-frequency pulse signal generated by the clock source is first a low-level pulse signal and then a high-level pulse signal. Pulse signal. the

However, when the clock source is in an abnormal working state, that is, in the event of a failure, some low-frequency pulse signals will be lost, that is, the clock source may only generate low-level pulse signals or only high-level pulses in certain clock cycles. signal, in this case, the current low-frequency pulse signal will always be the same as the latched low-frequency pulse signal. the

For example, in a certain clock cycle, the latched low-frequency pulse signal is a low-level pulse signal, and in this clock cycle, the current low-frequency pulse signal generated by the clock source is always a low-level pulse signal. the

Therefore, the detection unit can determine whether the low-frequency pulse signal generated by the clock source is lost by detecting whether the current low-frequency pulse signal generated by the clock source is always the same as the latched low-frequency pulse signal within the timing period. the

Wherein, the first indication signal is used to indicate that the low-frequency pulse signal is lost, and the second indication signal is used to indicate that the low-frequency pulse signal is not lost. the

In the embodiment of the present utility model, the circuit for detecting the failure of the clock source may include a first register, a first timer and a detection unit, the first timer is used for cycle timing, and the first register is used for latching the start timing point of each timing cycle The low-frequency pulse signal generated by the clock source; the detection unit is used to detect whether the current low-frequency pulse signal generated by the clock source is always the same as the latched low-frequency pulse signal in the timing cycle; if so, output the first indication signal, and the The first indication signal is used to indicate that the low-frequency pulse signal is lost, and when the low-frequency pulse signal is lost, it can be confirmed that the clock source has failed; if not, a second indication signal is output, and the second indication signal is used to indicate the The low-frequency pulse signal is not lost. When the low-frequency pulse signal is not lost, it can be confirmed that the clock source has not failed. It can be seen that the utility model realizes whether the clock source fails by determining whether the low-frequency pulse signal is lost. detection. the

Another embodiment of the utility model also provides a circuit for detecting clock source failure, as shown in Figure 2, the circuit may include a first timer 200, a first register 300, and a detection unit 400; the detection unit 400 includes a logic circuit 401, the second register 402, and the third register 403; wherein:

The first timer 200 is used for cyclic timing, wherein the timing period of the first timer is greater than or equal to the clock period of the low-frequency pulse signal; The sum of the maximum frequency offsets generated by the clock source can be specifically set according to actual conditions, and the present invention does not limit it. the

The first register 300 is connected with the first timer 200 and the clock source respectively, and the first register is used for latching the low-frequency pulse signal produced by the clock source at the start timing point of each timing cycle; The low-frequency pulse signal generated by the clock source is latched at the start timing point of each timing cycle of the timer. the

The first input terminal of the logic circuit 401 is connected to the clock source, and the second input terminal is connected to the first register 300; the logic circuit is used to compare whether the current low-frequency pulse signal generated by the clock source is the same as the latched low-frequency pulse signal, and Outputting the first signal according to the comparison result;

Wherein, the specific implementation form of the logic circuit is not limited, for example, it may be an exclusive OR gate logic circuit or an exclusive OR gate logic circuit;

If the logic circuit is an XOR gate logic circuit, then, when the XOR gate logic circuit compares the current low-frequency pulse signal with the latched low-frequency pulse signal to be the same, the first output signal is a low-level signal; When the circuit compares the current low-frequency pulse signal with the latched low-frequency pulse signal, the first output signal is a high-level signal;

If the logic circuit is a NOR logic circuit, then, when the NOR logic circuit compares the current low-frequency pulse signal with the latched low-frequency pulse signal, the output first signal is a high-level signal; When the circuit compares that the current low-frequency pulse signal is different from the latched low-frequency pulse signal, the output first signal is a low-level signal. the

The second register 402 is respectively connected with the output terminal of the logic circuit and the first timer;

The output signal of the second register is set as the second signal at the start timing point of each timing cycle;

Wherein, the second register is used to record the first signal output by the logic circuit in the timing cycle to output the third signal when the current low-frequency pulse signal is different from the latched low-frequency pulse signal; record to the logic circuit The first output signal is used to always indicate that when the current low-frequency pulse signal is the same as the latched low-frequency pulse signal, keep outputting the second signal;

Wherein, the specific implementation form of the second signal and the third signal is not limited in the present invention, and can be set according to the actual situation;

For example, if the first signal is a low-level signal, it is used to indicate that the current low-frequency pulse signal is the same as the locked low-frequency pulse signal; when the first signal is a high-level signal, it is used to indicate that the current low-frequency pulse signal is the same as the locked low-frequency pulse signal. The stored low-frequency pulse signals are different; then, the second signal can be a high-level signal, and the third signal can be a low-level signal;

Or, if the first signal is a high-level signal, it is used to indicate that the current low-frequency pulse signal is the same as the locked low-frequency pulse signal; when the first signal is a low-level signal, it is used to indicate that the current low-frequency pulse signal is the same as the locked low-frequency pulse signal. The stored low-frequency pulse signals are different; then, the second signal can be a low-level signal, and the third signal can be a high-level signal. the

It should be noted that, when the clock source is in a normal working state, that is, when no fault occurs, the clock source will generate a high-level pulse signal and a low-level pulse signal in each clock cycle; then, the current low-frequency pulse signal does not It will always be the same as the latched low-frequency pulse signal, and may be different from the latched low-frequency pulse signal. In this case, the first signal output by the logic circuit changes, that is, the first signal not only indicates that the current low-frequency pulse signal is the same as the latched low-frequency pulse signal, but also indicates that the current low-frequency pulse signal is the same as the latched low-frequency pulse signal. The low-frequency pulse signal is different. Therefore, when the second register records that the first signal is used to indicate that the current low-frequency pulse signal is different from the latched low-frequency pulse signal, it outputs the third signal. the

For example, if the first signal is a low-level signal, it is used to indicate that the current low-frequency pulse signal is the same as the locked low-frequency pulse signal; when the first signal is a high-level signal, it is used to indicate that the current low-frequency pulse signal is the same as the locked low-frequency pulse signal. The stored low-frequency pulse signals are different; then, when the second register records that the first signal is an over-high level signal, the third signal is output. the

It should be noted that when the clock source is in an abnormal working state, that is, when a fault occurs, the clock source will only generate a high-level pulse signal or a low-level pulse signal in some clock cycles, then the current low-frequency pulse signal will always be consistent with The latched low-frequency pulse signals are the same. In this case, the first signal output by the logic circuit does not change, that is, the first signal always indicates that the current low-frequency pulse signal is the same as the latched low-frequency pulse signal. Therefore, when the second register records that the first signal is used to always represent that the current low-frequency pulse signal is the same as the latched low-frequency pulse signal, it keeps outputting the second signal. the

For example, if the first signal is a low-level signal, it is used to indicate that the current low-frequency pulse signal is the same as the locked low-frequency pulse signal; when the first signal is a high-level signal, it is used to indicate that the current low-frequency pulse signal is the same as the locked low-frequency pulse signal. The stored low-frequency pulse signals are different; then, when the second register records that the first signal is always a low-level signal, it keeps outputting the second signal. the

The third register 403 is connected to the second register 402 and the first timer 200 respectively;

Wherein, the third register is used to latch the signal output by the second register at the start timing point of each timing cycle, and when the latched signal is the second signal, output the first indication signal to indicate the occurrence of the low-frequency pulse signal When the latched signal is the third signal, a second indication signal is output to indicate that the low-frequency pulse signal is not lost. the

It should be noted that there is a delay when the register jumps, so even if the second register is set to the second signal by the third signal at the start timing point of the timing cycle, the third register can also be latched at the start timing point of the timing cycle to the third signal. the

In practical applications, the circuit for detecting clock source failure may have different sensitivities to different low-frequency pulse signals. Therefore, in the utility model, the criteria for determining whether the low-frequency pulse signal is lost are also different;

When the circuit for detecting the failure of the clock source is highly sensitive to the low-frequency pulse signal, it can be determined whether the low-frequency pulse signal is lost through the detection unit outputting the first indication signal or the second indication signal. the

When the circuit for detecting clock source failure has low sensitivity to low-frequency pulse signals, the circuit can also include a second timer, as shown in Figure 3, the circuit can include: a first timer 200, a first register 300, a detection unit 400, the second timer 500, wherein:

The first timer 200 is used for cycle timing. the

The first register 300 is connected to the first timer 200 and the clock source respectively, and the first register is used to latch the low-frequency pulse signal generated by the clock source at the start timing point of each timing cycle;

The detection unit 400 is connected to the first timer 200, the first register 300 and the clock source respectively;

Wherein, after the first register latches the low-frequency pulse signal generated by the clock source, it will send the latched low-frequency pulse signal to the detection unit; and the detection unit is used to detect whether the current low-frequency pulse signal generated by the clock source is It is always the same as the latched low-frequency pulse signal; if yes, output the first indication signal; if not, output the second indication signal; 

The second timer 500 is connected with the detection unit 400;

Wherein, the second timer is used to start timing when the detection unit outputs the first indication signal;

When the detection unit outputs the second indication signal, it is cleared to zero. the

It should be noted that the circuit corresponding to FIG. 3 may also include a second timer. Then, the second timer may be connected with the third register for timing when the third register outputs the first indication signal. When the third register outputs the second indication signal, it is cleared. the

Specifically, the second timer starts counting when the detection unit outputs the first indication signal. If the detection unit outputs the first indication signal for a plurality of consecutive counting cycles, then the second timer will continue counting. When the counting time reaches the predetermined When setting the time, it can be determined that the low-frequency pulse signal is lost, and then it can be determined that the clock source is faulty. the

And before the second timing time does not reach the preset time, if within a certain timing period, the detection unit outputs the second indication signal, then the second timer is cleared, at this time, it can be determined that the low-frequency pulse signal is not lost, In turn, it can be determined that the clock source has not failed. the

The embodiment of the utility model also discloses another circuit for detecting clock source failure, as shown in Figure 4, the circuit may include a processor 100, the processor has an input terminal 101 and an output terminal 102, wherein:

The input end 101 of the processor 100 is used to be connected with the clock source, and this clock source is the current clock source of communication equipment, is used for generating the low-frequency pulse signal; The utility model does not limit the clock frequency of the low-frequency pulse signal, for example, low-frequency pulse The signal can be a second pulse signal. the

The output terminal 100 of the processor 100 is used to output an indication signal, and the indication signal can indicate whether the low-frequency pulse signal generated by the clock source is lost. the

Specifically, the processor is used to latch the low-frequency pulse signal generated by the clock source at the start timing point of each timing cycle;

Wherein, the processor can be cyclically timed, and the timing period is greater than or equal to the clock period of the low-frequency pulse signal. It should be noted that the timing period can be the sum of the clock period of the clock source and the maximum frequency deviation allowed to be generated by the clock source. Specifically It can be set according to the actual situation, and the utility model does not limit it. the

For example, the clock period of the low-frequency pulse signal is 1 second, and the maximum frequency deviation allowed by the clock source is 10% of the clock period, then the timing period is 1.1 seconds. the

After the processor is used to latch the low-frequency pulse signal generated by the clock source at the start timing point of each timing cycle, it can detect whether the current low-frequency pulse signal generated by the clock source is always the same as the latched low-frequency pulse signal within the timing cycle; If yes, output the first indication signal; if not, output the second indication signal;

It should be noted that the clock source will not lose the low-frequency pulse signal in the normal working state, that is, in the case of no failure, that is, the clock source will generate a low-level pulse signal and a high-level pulse signal in each clock cycle. pulse signal; then, the current low-frequency pulse signal will not always be the same as the latched low-frequency pulse signal, and may be different from the latched low-frequency pulse signal. the

For example, in a certain clock cycle, the latched low-frequency pulse signal is a low-level pulse signal, and in this clock cycle, the current low-frequency pulse signal generated by the clock source is first a low-level pulse signal and then a high-level pulse signal. Pulse signal. the

While the clock source is in an abnormal working state, that is, in the event of a failure, some low-frequency pulse signals will be lost, that is, the clock source may only generate low-level pulse signals or only high-level pulses in certain clock cycles pulse signal, in this case, the current low-frequency pulse signal will always be the same as the latched low-frequency pulse signal. the

For example, in a certain clock cycle, the latched low-frequency pulse signal is a low-level pulse signal, and in this clock cycle, the current low-frequency pulse signal generated by the clock source is always a low-level pulse signal. the

Therefore, the processor can determine whether the low-frequency pulse signal generated by the clock source is lost by detecting whether the current low-frequency pulse signal generated by the clock source is always the same as the latched low-frequency pulse signal within the timing period. the

Wherein, the first indication signal is used to indicate that the low-frequency pulse signal is lost, and the second indication signal is used to indicate that the low-frequency pulse signal is not lost. the

In the embodiment of the present invention, the circuit for detecting the failure of the clock source may include a processor, the input end of the processor is used to connect with the clock source, and the output end is used to output an indication signal, and the timing point is started by latching each timing cycle The low-frequency pulse signal generated by the clock source; and within the timing period, detect whether the current low-frequency pulse signal generated by the clock source is always the same as the latched low-frequency pulse signal; if so, output the first indication signal, the The first indication signal is used to indicate that the low-frequency pulse signal is lost, and when the low-frequency pulse signal is lost, it can be confirmed that the clock source has failed; if not, a second indication signal is output, and the second indication signal is used to indicate the The low-frequency pulse signal is not lost. When the low-frequency pulse signal is not lost, it can be confirmed that the clock source has not failed. It can be seen that the utility model realizes whether the clock source fails by determining whether the low-frequency pulse signal is lost. detection. the

In the utility model, the processor is used to detect whether the current low-frequency pulse signal generated by the clock source is always the same as the latched low-frequency pulse signal within the timing cycle.

As a way of implementing:

The processor can be used to compare whether the current low-frequency pulse signal generated by the clock source is the same as the latched low-frequency pulse signal, and generate the first signal according to the comparison result;

Wherein, the first signal is a signal used to indicate whether the current low-frequency pulse signal generated by the clock source is the same as the latched low-frequency pulse signal, and the specific implementation method is not limited;

For example, when the first signal is a low-level signal, it is used to indicate that the current low-frequency pulse signal generated by the clock source is the same as the latched low-frequency pulse signal; when the first signal is a high-level signal, it is used to indicate the current low-frequency pulse signal generated by the clock source. The current low-frequency pulse signal is different from the latched low-frequency pulse signal;

Or, when the first signal is a high-level signal, it is used to indicate that the current low-frequency pulse signal generated by the clock source is the same as the latched low-frequency pulse signal; when the first signal is a low-level signal, it is used to indicate the current low-frequency pulse signal generated by the clock source. The current low-frequency pulse signal is different from the latched low-frequency pulse signal. the

When the processor determines that the first signal is used to represent that the current low-frequency pulse signal is different from the latched low-frequency pulse signal, a third signal is generated, and a second indication signal can be output according to the third signal;

It should be noted that, when the clock source is in a normal working state, that is, when no fault occurs, the clock source will generate a high-level pulse signal and a low-level pulse signal in each clock cycle. That is to say, if the clock source does not lose the low-frequency pulse signal, it can be determined that the first signal changes within the timing period, that is, the first signal not only represents that the current low-frequency pulse signal is the same as the latched low-frequency pulse signal, It is also characterized that the current low-frequency pulse signal is different from the latched low-frequency pulse signal. Therefore, as long as the processor determines that the first signal is used to indicate that the current low-frequency pulse signal is different from the latched low-frequency pulse signal, a third signal is generated; and a second indication signal is output according to the third signal to indicate the low-frequency The pulse signal is not lost. the

When the processor determines that the first signal is used to always represent the current low-frequency pulse signal and the latched low-frequency pulse signal, a second signal is generated, and the first indication signal can be output according to the second signal;

It should be noted that, when the clock source is in an abnormal working state, that is, when a fault occurs, the clock source will only generate a high-level pulse signal or a low-level pulse signal in certain clock cycles. That is to say, if the low-frequency pulse signal generated by the clock source is lost, it can be determined that the first signal has not changed during the timing period, that is, the first signal is used to always represent the current low-frequency pulse signal and the latched low-frequency The pulse signal is the same. Therefore, when the processor determines that the first signal is used to always indicate that the current low-frequency pulse signal is the same as the latched low-frequency pulse signal, it generates a second signal; and outputs the first indication signal according to the second signal to indicate the low-frequency The pulse signal is lost. the

As another implementation:

The processor can be used to compare whether the current low-frequency pulse signal generated by the clock source is the same as the latched low-frequency pulse signal, and generate the first signal according to the comparison result; and detect whether the first signal is consistent with the preset The standard signal is the same;

Wherein, the processor is preset with a standard signal, which is a signal representing that the current low-frequency pulse signal generated by the clock source is the same as the latched low-frequency pulse signal, and the specific implementation method is not limited;

For example, when the first signal is a low-level signal, it is used to indicate that the current low-frequency pulse signal generated by the clock source is the same as the latched low-frequency pulse signal; when the first signal is a high-level signal, it is used to indicate the current low-frequency pulse signal generated by the clock source. The current low-frequency pulse signal is different from the latched low-frequency pulse signal; correspondingly, the preset standard signal is a low-level signal;

Or, when the first signal is a high-level signal, it is used to indicate that the current low-frequency pulse signal generated by the clock source is the same as the latched low-frequency pulse signal; when the first signal is a low-level signal, it is used to indicate the current low-frequency pulse signal generated by the clock source. The current low-frequency pulse signal is different from the latched low-frequency pulse signal; correspondingly, the preset standard signal is a high-level signal. the

When the processor detects that the first signal is always the same as the preset standard signal within the time period, it outputs the first indication signal to indicate that the low-frequency pulse signal is lost; when it detects that the first signal is not always the same as the preset When the standard signals are the same, for example, the first signal and the preset standard signal may first be the same and then different, then output a second indication signal to indicate that the low-frequency pulse signal is not lost. the

In practical applications, the circuit for detecting clock source failure may have different sensitivities to different low-frequency pulse signals. Therefore, in the utility model, the standard for the processor to determine whether the low-frequency pulse signal is lost is also different;

When the circuit for detecting clock source failure is highly sensitive to low-frequency pulse signals, the processor can detect whether the current low-frequency pulse signal generated by the clock source is always the same as the latched low-frequency pulse signal in each timing cycle, and if so, then Output the first indication signal; if not, output the second indication signal;

In the above method, as long as the processor determines that the low-frequency pulse signal is always the same as the latched low-frequency pulse signal within a certain timing period, then it is determined that the low-frequency pulse signal is lost, and at this time, the first indication signal is output;

In order to facilitate understanding, an example is used to illustrate, assuming that the processor latches the low-level pulse signal at the beginning of a certain timing period; and within the timing period, the current low-frequency pulse signal generated by the clock source is always low pulse signal, then it can be determined that the low-frequency pulse signal is lost, and the first indication signal is output at this time; and if within the timing period, the current low-frequency pulse signal generated by the clock source is first a low-level pulse signal and then a high-level pulse signal, then it can be determined that the low-frequency pulse signal is not lost within the timing period, and at this time, a second indication signal is output. the

When the circuit for detecting the failure of the clock source is less sensitive to the low-frequency pulse signal, the processor can output the first indication when the current low-frequency pulse signal generated by the clock source and the latched low-frequency pulse signal last for the same time and reach a preset time signal; otherwise, output a second indication signal. the

Specifically, the processor checks whether the current low-frequency pulse signal generated by the clock source is always the same as the latched low-frequency pulse signal within the timing period; if so, it starts timing, and when the timing reaches the preset time, it outputs the first an indication signal; if not, the counting time is cleared, and a second indication signal is output. the

Wherein, the preset time can be set according to the actual situation, which is not specifically limited in the present invention. For example, when the timing period is 1.1 seconds, the preset time can be 10 seconds. the

For example, in a certain timing period, when the processor detects that the current low-frequency pulse signal generated by the clock source is always the same as the low-frequency pulse signal latched at the start timing point of the timing period, it starts timing; In the timing period, it is detected that the current low-frequency pulse signal generated by the clock source is always the same as the low-frequency pulse signal latched at the start timing point of the corresponding timing period, then continue timing, and when it is determined that the timing time reaches the preset time, output the first Indication signal; before the timing time reaches the preset time, if within a certain timing period, it is detected that the current low-frequency pulse signal generated by the clock source is not always consistent with the low-frequency pulse signal latched at the start timing point in the corresponding timing period At the same time, then, the timing time is cleared, and the second indication signal is output

Each embodiment in this specification is described in a progressive manner, each embodiment focuses on the difference from other embodiments, and the same and similar parts of each embodiment can be referred to each other. As for the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and for the related information, please refer to the description of the method part. the

The above description of the disclosed embodiments enables those skilled in the art to realize or use the utility model. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention will not be limited to these embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein. the

Claims (6)

1. A circuit for detecting a clock source failure, characterized in that the clock source is used to generate low-frequency pulse signals, and the circuit comprises: A first timer for cycle timing, the timing period of the first timer is greater than or equal to the clock period of the low-frequency pulse signal; A first register connected to the clock source and the first timer respectively, the first register is used to latch the low-frequency pulse signal generated by the clock source at the start timing point of each timing cycle; A detection unit connected to the clock source, the first timer and the first register respectively; Wherein, the detection unit is used to detect whether the current low-frequency pulse signal generated by the clock source is always the same as the latched low-frequency pulse signal within the timing period; if so, output a first indication signal, and the first indication signal It is used to indicate that the low-frequency pulse signal is lost; if not, a second indication signal is output, and the second indication signal is used to indicate that the low-frequency pulse signal is not lost. the 2. The circuit according to claim 1, wherein the detection unit comprises: A logic circuit in which the first input end is connected to the clock source and the second input end is connected to the first register, and the logic circuit is used to compare the current low-frequency pulse signal generated by the clock source with the latched low-frequency pulse Whether the signals are the same, and output the first signal according to the comparison result; The second register connected to the output terminal of the logic circuit and the first timer respectively, the output signal of the second register is set as the second signal when the timing point of each timing cycle is started; The second register is used to output a third signal when it is recorded that the first signal output by the logic circuit is different from the latched low-frequency pulse signal during the timing period; It is recorded that the first signal output by the logic circuit is used to always indicate that the current low-frequency pulse signal is the same as the latched low-frequency pulse signal, and keep outputting the second signal; The third register connected to the first timer and the second register is used to latch the signal output by the second register at the start timing point of each timing cycle, and when the latched signal is When the signal is the second signal, the first indication signal is output, and when the latched signal is the third signal, the second indication signal is output. the 3. The circuit according to claim 1, further comprising a second timer connected to the detection unit; The second timer is used to start timing when the detection unit outputs the first indication signal; When the detection unit outputs the second indication signal, it is cleared. the 4. The circuit according to claim 2, wherein the logic circuit is an XOR gate logic circuit; When the current low-frequency pulse signal is the same as the latched low-frequency pulse signal, the first signal is a low-level signal; When the current low-frequency pulse signal is different from the latched low-frequency pulse signal, the first signal is a high-level signal; The second signal is a high level signal; the third signal is a low level signal; Or, the logic circuit is an NOR gate logic circuit; When the current low-frequency pulse signal is the same as the latched low-frequency pulse signal, the first signal is a high-level signal; When the current low-frequency pulse signal is different from the latched low-frequency pulse signal, the first signal is a low-level signal; The second signal is a low level signal; the third signal is a high level signal. the 5. A circuit for detecting a clock source failure, characterized in that it includes a processor, the processor has an input end and an output end, the input end is used to be connected to the clock source, and the clock source is used to generate Low-frequency pulse signal; the output terminal is used to output an indication signal; The processor is used to latch the low-frequency pulse signal generated by the clock source at the start timing point of each timing cycle; and detect whether the current low-frequency pulse signal generated by the clock source is consistent with the latched low-frequency pulse signal within the timing cycle. The pulse signals are the same; if so, output a first indication signal, and the first indication signal is used to indicate that the low-frequency pulse signal is lost; if not, output a second indication signal, and the second indication signal is used to indicate that the low-frequency pulse signal is lost. The pulse signal is not lost; Wherein, the timing period is greater than or equal to the clock period of the low-frequency pulse signal. the 6. The circuit according to claim 5, wherein the processor outputs the first indication signal specifically as follows: The processor outputs a first indication signal when the current low-frequency pulse signal generated by the clock source lasts for the same time as the latched low-frequency pulse signal for a preset time. the