CN203950176U - Wireless sensor network node hardware platform capable of being reconfigured online - Google Patents

Abstract

The utility model relates to a wireless sensor network node hardware platform that can reconfigure online, which enables the upper Internet of things application system integrated integration platform to shield the development of hardware, when using the platform, a user can configure appropriate sensor nodes online only by setting system parameters according to the functional requirements of projects, and assemble the Internet of things application system that meets the requirements; the portability is good, and smooth upgrading can be realized; when new functions are required to be added or different types of sensors are adopted, external hardware circuits do not need to be modified, and by utilizing the characteristics of the online reconfigurable system, the new functions can be conveniently transplanted to the system, more complex processing is realized, and smooth upgrading is realized.

Description

A wireless sensor network node hardware platform that can be reconfigured online

technical field

The utility model relates to the field of wireless sensor networks, in particular to an online reconfigurable wireless sensor network node hardware platform. the

Background technique

At present, the IoT application system training platform can mainly complete the verification of some basic experiments, such as marquee, serial communication, temperature and humidity sensor experiments, etc. This kind of training platform is biased towards the training of the underlying development, requiring students to have a certain degree of hardware development. Basic, with a certain embedded development ability, it is difficult for vocational students to reach this level. the

Higher vocational Internet of Things training teaching requirements can provide an incubation platform for students to understand and develop Internet of Things application systems. After students learn advanced languages and master the necessary hardware knowledge, they do not need to have a deep understanding of hardware. The high-level language is used to realize the communication between sensor nodes, and through encapsulation, the control function of the execution structure is completed, and the intelligent application system of the Internet of Things can be developed, which has positive significance for the teaching and promotion of the application system of the Internet of Things. the

Utility model content

The technical problem to be solved by the utility model is to provide an online reconfigurable wireless sensor network node hardware platform, which can develop a secondary development platform with strong versatility and based on real projects. In the teaching process, based on the secondary development platform, different IoT application systems can be designed to organize teaching. Students only need to design the system logic, select the appropriate node module, and complete a real Application system development. the

The technical scheme adopted by the utility model to solve the technical problem is: a wireless sensor network node hardware platform that can be reconfigured online, consisting of a processing unit, a sensor analog input processing unit, a sensor digital input unit, and an analog output control unit , a digital output control unit, a wireless transceiver unit, and a power supply unit; the sensor analog input processing unit, the sensor digital input unit, the analog output control unit, and the digital output control unit are connected to the processing unit through a slot;

Described processing unit is completed by FPGA chip, comprises microprocessor IP core; Described sensor analog quantity input processing unit comprises sensor, conditioning circuit, A/D conversion circuit; Described A/D conversion circuit passes A/D The timing control circuit is connected with the microprocessor IP core;

The analog output control unit includes a mechanism function control circuit and a D/A conversion circuit; the D/A conversion circuit is connected with the microprocessor IP core through the D/A timing control circuit; the microprocessor IP The core is connected with a wireless transceiver unit.

The wireless transceiver unit described in the utility model is composed of a wireless radio frequency circuit and an antenna; the processing unit controls and coordinates the entire sensor to make the acquisition node work; the sensor analog input processing unit collects corresponding information; and according to the required Depending on the collected information, it can be flexibly configured as a temperature and humidity sensor, a gas sensor, a light intensity sensor and/or a smoke sensor; the sensor digital input unit collects corresponding digital input signals. the

The processing unit described in the utility model can complete the function of the node hardware platform processing unit of an intelligent application system in a specific field by reconfiguring the corresponding configuration file online. Since different types of applications require different types of sensors, conditioning circuits, A/D conversion circuits, and D/A conversion circuits, different A/D timing control and D/A conversion circuits need to be configured each time the processing unit is reconfigured. Timing control functional unit. The data collected by the sensor analog input processing unit and the sensor digital input unit are sent to the microprocessor IP core for processing. For different applications, the microprocessor IP core needs to be configured to run different programs. The threshold comparison function is set in the program as Different parameters, to complete the warning trigger action and data display mode required by the corresponding application. the

The beneficial effect of the utility model is that it solves the defects existing in the background technology, 1. The upper-level Internet of Things application system integrated platform shields the development of the hardware, and the user only needs to follow the project function requirements when using the platform. Through the setting of system parameters, suitable sensor nodes can be prepared online, and an IoT application system that meets the needs can be assembled; 2. Good portability and smooth upgrade. When it is necessary to add new functions or adopt different types of sensors, it is not necessary to modify the external hardware circuit. Using the characteristics of the online reconfigurable system, it is convenient to transplant new functions for the system, realize more complex processing, and realize smooth upgrades. the

Description of drawings

Below in conjunction with accompanying drawing and embodiment the utility model is further described. the

Fig. 1 is a block diagram of the wireless sensor network node hardware platform system of the present invention. the

Detailed ways

Now in conjunction with accompanying drawing and preferred embodiment the utility model is described in further detail. These drawings are all simplified schematic diagrams, and only schematically illustrate the basic structure of the utility model, so they only show the configurations related to the utility model. the

As shown in Figure 1, the wireless sensor network node hardware platform consists of a processing unit, a sensor analog input processing unit, a sensor digital input unit, an analog output control unit, a digital output control unit, a wireless transceiver unit, and a power supply unit. the

The processing unit is responsible for controlling and coordinating the work of the entire sensor acquisition node; the sensor analog input processing unit is used to collect corresponding information. According to the different information to be collected, it can be flexibly configured as temperature and humidity sensors, gas sensors, light intensity sensors, smoke sensors and other types; the sensor digital input unit is used to collect corresponding digital input signals. The analog quantity output control unit and the digital quantity output control unit complete the intelligent control of the external related operating equipment. The wireless transceiver unit consists of a radio frequency circuit and an antenna, and is mainly responsible for sending and receiving data and exchanging control information; the power supply unit is used to provide power for the entire node, and monitor the battery voltage of the node to determine whether maintenance is required. the

The sensor analog input processing unit, the sensor digital input unit, the analog output control unit, and the digital output control unit are connected to the processing unit through slots. When it is necessary to construct a new Internet of Things application system, the corresponding input and output processing unit type can be replaced with the required type. The processing unit is completed by FPGA, and the corresponding configuration file can be reconfigured online to complete the node hardware platform processing unit function of an intelligent application system in a specific field. Since different types of applications require different types of sensors, conditioning circuits, A/D conversion circuits, and D/A conversion circuits, different A/D timing control and D/A conversion circuits need to be configured each time the processing unit is reconfigured. Timing control functional unit. The data collected by the sensor analog input processing unit and the sensor digital input unit are sent to the microprocessor IP core for processing. For different applications, the microprocessor IP core needs to be configured to run different programs. The threshold comparison function is set in the program as Different parameters, to complete the warning trigger action and data display mode required by the corresponding application. the

The IP core used by the processing unit is written using the hardware description language VHDL using a top-down design method. The IP core mainly includes several important modules: CPU, timer, interrupt controller, serial port controller, 8KB ROM, 256B internal RAM memory, and SPI interface. The CPU is the core component of the entire microcontroller and controls the rest of the modules. The CPU consists of an arithmetic logic operation unit (ALU), a register file, a multiplication and division unit, and a decoder. The address line, control line and data line are drawn from the CPU module, and the CPU realizes the connection with other modules through these three sets of lines. The internal RAM memory is used to store data, which consists of four parts: working register, bit addressing area, buffer and special function register. ROM memory is used to store programs. Interrupts are an essential part of microcontrollers, and interrupts allow the system to deal with emergencies in real time. An interrupt interface with two levels of priority and 12 interrupt sources is designed here. Timers are also called counters, and their functions in microcontrollers include the following functions: provide periodic interrupts for microcontrollers, and perform task scheduling; provide timing for applications that require timing. Three timers are designed in this microcontroller, among which timer 0 and timer 1 have four working modes, and timer 2 has three working modes. The SPI interface is used to connect the wireless transceiver unit. The SPI interface consists of a clock divider, clock control logic, special function registers and a control unit. the

The main device selected by the wireless transceiver unit is CC2530. CC2530 is a true system-on-chip (SoC) solution for IEEE802.15.4, ZigBee and RF4CE applications, which combines the excellent performance of leading RF transceivers to ensure the effectiveness and reliability of short-range communication. CC2530 only needs very few peripheral components, and the peripheral circuit includes three parts: crystal oscillator clock circuit, RF input/output matching circuit and microcontroller interface circuit. The local oscillator signal of the chip can be provided by an external active crystal or by an internal circuit. When provided by an internal circuit, an external crystal oscillator and two load capacitors are required. The size of the capacitor depends on parameters such as crystal frequency and input capacitance. The RF I/O matching circuit is mainly used to match the input and output impedance of the chip so that the input and output impedance is 50Ω, and at the same time provide DC bias for the PA and LNA inside the chip. The microprocessor IP core is connected with CC2530 through SPI interface. Here, the microprocessor IP core is the main controller, and the SPI of the microprocessor IP core works in the host mode, which is the controller of the SPI data transmission. CC2530 is controlled, and its SPI works in slave mode. the

The system software program includes CC2530 initialization, microprocessor control CC2530 to send and receive data, node data collection and summary, external device control, personalized intelligent application and other program sub-modules. Among them, node data collection and summary, external device control, and personalized intelligent application sub-module programs are configured online according to different project application requirements to generate an operating platform for an intelligent application system in a specific field. The software program of this design is written in C language in Nios II IDE, and all the designs are completed in the project manager provided by Nios II IDE. The program structure includes the bottom driver and the upper application program design. The bottom program includes hardware drivers and basic input and output functions, which are used for the call of the upper program. the

In this embodiment, the online configuration module adopts the method of using the Jam Player and the Jam configuration file in the ARM-based embedded Linux system, and utilizing the JTAG interface of the FPGA to configure it online. The configuration file is generated by the training equipment manufacturer when designing the intelligent application, and is transmitted to the ARM of the online configuration module by the user through the system man-machine interface via Ethernet for online configuration. The ARM model used in the utility model is S3C2410. The general-purpose pins GPB7, GPB8, GPB9, and GPB10 of the S3C2410 are connected to the JTAG interfaces TMS, TDI, TCK, and TDO of the FPGA respectively. the

In the embedded Linux environment, use the JTAG interface to configure the FPGA, and use the standard test and programming language STAPL. Jam STAPL is a suite provided by Altera that supports STAPL. Configuration with Jam STAPL consists of two parts, Jam Player and Jam configuration files. Jam Player reads the Jam file and parses the content expressed by the Jam file, generates a binary data stream for configuration on the JTAG interface and reads the feedback data. The Jam configuration file can be generated by Quartus II software or by a file format conversion tool. the

Porting Jam Player to embedded Linux requires the following customizations:

1. Change the platform's predefined environment, add prepared statements, and remove unnecessary source code;

2. Map JTAG signals to specific hardware pins;

3. Customize the error message output method;

4. Customize the delay function according to the processing capability of the specific microprocessor.

Because Jam Player runs in the embedded Linux environment, it cannot directly access the pin registers of the ARM chip, and thus cannot directly operate the input and output of the pins. So it is also necessary to write drivers for the pins used for the JTAG interface, and package them into character files that Jam Player can read and write. the

After Jam Player and the corresponding driver are successfully transplanted, the FPGA is configured online through ARM; the system can dynamically update the application without restarting. The user transmits the configuration file to the online configuration module on the system machine through Ethernet, and can set the A/D sequence control and D/A sequence control function units online according to the business rules and configuration parameters, and configure the microprocessor IP for different applications. The core runs different programs, completes the required warning trigger actions and data display methods, etc., to generate a node hardware platform for an intelligent application system in a specific field. the

What is described in the above specification is only the specific implementation of the present utility model, and various illustrations do not limit the essential content of the present utility model. Those of ordinary skill in the art can make specific implementations described before after reading the specification. modification or deformation without departing from the essence and scope of the utility model. the

Claims (1)

1. a wireless sensor network node hardware platform that can online reconfiguration, is made up of processing unit, Sensor Analog Relay System amount input processing unit, sensor digital quantity input block, analog output control module, digital output control module, wireless transmit/receive units, power supply unit; It is characterized in that: described Sensor Analog Relay System amount input processing unit, sensor digital quantity input block, analog output control module, digital output control module are connected with processing unit by slot;

Described processing unit is completed by fpga chip, comprises microprocessor IP kernel; Described Sensor Analog Relay System amount input processing unit comprises sensor, modulate circuit, A/D change-over circuit; Described A/D change-over circuit is connected with microprocessor IP kernel by A/D sequential control circuit;

Described analog output control module comprises mechanism's functional control circuit and D/A change-over circuit; Described D/A change-over circuit is connected with microprocessor IP kernel by D/A sequential control circuit; Described microprocessor IP kernel is connected with wireless transmit/receive units.