CN203851019U - Power Factor Correction Circuit and TV - Google Patents

Abstract

The utility model discloses a power factor correction circuit and a television set. The power factor correction circuit comprises an alternating current power input end, a rectification circuit, an active PFC (Power Factor Correction) circuit, a buffer circuit used for reducing switching loss and electromagnetic interference of the PFC circuit, a direct current power output end, a reactive circuit and a PWM (Pulse Width Modulation) control circuit. The rectification circuit is connected between the alternating current power input end and an input end of the PFC circuit. The buffer circuit is connected with the PFC circuit. The direct current power output end is connected with an output end of the PFC circuit. An input end of the reactive circuit is connected with the direct current power output end, and an output end of the reactive circuit is connected with an input end of the PWM control circuit. An output end of the PWM control circuit is connected with a control end of the PFC circuit. The power factor correction circuit reduces switching loss and improves circuit output power. In addition, electromagnetic interference of the PFC circuit is greatly reduced, and the safety performance of the PFC circuit is improved.

Description

Power Factor Correction Circuit and TV

technical field

The utility model relates to the technical field of power supplies, in particular to a power factor correction circuit and a television set.

Background technique

With the continuous development of power supply technology, power factor correction circuits have been more and more widely used. At present, there are many forms of circuits that can realize power factor correction, and because the boost type power factor correction circuit has the advantages of continuous input current, small current waveform distortion and simple driving circuit, etc., the boost type power factor correction circuit has been obtained. Wider range of applications.

However, in the traditional step-up power factor correction circuit, when the MOS switch is turned on, the inductor stores energy. When the MOS switch is turned off, the diode is turned on, and the energy stored in the inductor is released to the load. The turn-on and turn-off of the switch tube is controlled by the PWM signal. Therefore, when the switching frequency of the MOS switch tube increases, it will inevitably lead to an increase in switching loss and an increase in EMI (ElectroMagnetic Interference, electromagnetic interference). , and the increase of switching loss will not only reduce the output power of the circuit, but also cause the temperature of the circuit to rise, thereby reducing the reliability of the circuit. At the same time, the increase of electromagnetic interference will reduce the safety performance of the circuit.

Utility model content

The main purpose of the utility model is to provide a power factor correction circuit, aiming at reducing switching loss and reducing electromagnetic interference.

In order to achieve the above object, the utility model proposes a power factor correction circuit, the power factor correction circuit includes an AC power input terminal for inputting an AC power supply, a rectification circuit for rectifying the AC power supply, and a rectification circuit for An active PFC circuit for correcting the power factor of the DC power outputted by the rectifier circuit, a buffer circuit for reducing switching loss and electromagnetic interference of the active PFC circuit, and a DC power supply for outputting a preset DC voltage an output terminal, a feedback circuit for collecting the voltage at the output terminal of the DC power supply, and a PWM control circuit for outputting a corresponding PWM control signal to the active PFC circuit according to the voltage collected by the feedback circuit; wherein ,

The rectifier circuit is connected between the input end of the AC power supply and the input end of the active PFC circuit; the buffer circuit is connected to the active PFC circuit; the output end of the DC power supply is connected to the active PFC circuit The output end of the circuit is connected; the input end of the feedback circuit is connected to the output end of the DC power supply, the output end of the feedback circuit is connected to the input end of the PWM control circuit; the output end of the PWM control circuit is connected to the The control terminal connection of the above-mentioned active PFC circuit.

Preferably, the rectifier circuit is a rectifier bridge stack, and the rectifier bridge stack includes a first pin, a second pin, a third pin, and a fourth pin; the AC power input end includes a first AC input end and a second AC input end. Input end; the second pin of the rectifier bridge stack is connected to the first AC input end, the fourth pin of the rectifier bridge stack is connected to the second AC input end, and the first pin of the rectifier bridge stack is connected to the first AC input end. The positive pole of the input terminal of the active PFC circuit is connected, and the third pin of the rectifier bridge stack is connected with the negative pole of the input terminal of the active PFC circuit.

Preferably, the active PFC circuit includes a first inductor, a MOS switch, a first diode and a first capacitor; wherein,

The first end of the first inductance is the anode of the input end of the active PFC circuit, the anode is connected to the first pin of the rectifier bridge stack, and the second end of the first inductance is connected to the snubber circuit connected; the drain of the MOS switch tube is connected to the second end of the first inductor, the drain of the MOS switch tube is also connected to the buffer circuit, and the gate of the MOS switch tube is connected to the PWM The output terminal of the control circuit is connected, the source of the MOS switch tube is the negative pole of the input terminal of the active PFC circuit, and the negative pole is connected to the third pin of the rectifier bridge stack; the anode of the first diode connected to the buffer circuit, the cathode of the first diode is connected to the output terminal of the DC power supply; the first terminal of the first capacitor is connected to the output terminal of the DC voltage, and the first terminal of the first capacitor is connected to the output terminal of the DC power supply. The two terminals are connected with the source of the MOS switch tube.

Preferably, the snubber circuit includes a second inductor, a second diode, a third diode, a fourth diode, a second capacitor and a third capacitor; wherein,

The first end of the second inductance is connected to the second end of the first inductance in the active PFC circuit, and the second end of the second inductance is connected to the anode of the first diode in the active PFC circuit; the second The anode of the diode is connected to the drain of the MOS switching tube in the active PFC circuit, the cathode of the second diode is connected to the anode of the third diode; the cathode of the third diode is connected to the fourth diode The anode of the tube is connected; the cathode of the fourth diode is connected to the cathode of the first diode in the active PFC circuit; the first end of the second capacitor is connected to the second inductor and the first end of the active PFC circuit Between the anodes of a diode, the second end of the second capacitor is connected between the cathode of the third diode and the anode of the fourth diode; the first end of the third capacitor is connected to the second diode Between the cathode of the third capacitor and the anode of the third diode, the second end of the third capacitor is connected to the source of the MOS switch in the active PFC circuit.

Preferably, the feedback circuit includes a first resistor and a second resistor; wherein,

The first end of the first resistor is connected to the output terminal of the DC power supply, the second end of the first resistor is connected to the first end of the second resistor; the second end of the second resistor is connected to the MOS switch in the active PFC circuit The source connection of the tube.

Preferably, the input end of the PWM control circuit is connected between the first resistor and the second resistor in the feedback circuit, and the MOS switch tube in the active PFC circuit is the control end of the active PFC circuit, so The control terminal is connected with the output terminal of the PWM control circuit.

The utility model also proposes a TV set, which includes a power factor correction circuit, and the power factor correction circuit includes an AC power input terminal for inputting an AC power supply, a rectifying circuit for rectifying the AC power supply, An active PFC circuit for correcting the power factor of the DC power outputted by the rectifier circuit, a buffer circuit for reducing switching loss and electromagnetic interference of the active PFC circuit, and a preset DC voltage for outputting The output end of the DC power supply, the feedback circuit for collecting the voltage of the output end of the DC power supply, and the PWM control for outputting a corresponding PWM control signal to the active PFC circuit according to the voltage collected by the feedback circuit circuit; where,

The rectifier circuit is connected between the input end of the AC power supply and the input end of the active PFC circuit; the buffer circuit is connected to the active PFC circuit; the output end of the DC power supply is connected to the active PFC circuit The output end of the circuit is connected; the input end of the feedback circuit is connected to the output end of the DC power supply, the output end of the feedback circuit is connected to the input end of the PWM control circuit; the output end of the PWM control circuit is connected to the The control terminal connection of the above-mentioned active PFC circuit.

The power factor correction circuit proposed by the utility model includes an AC power input terminal for inputting an AC power supply, a rectification circuit for rectifying the AC power supply, and an active circuit for correcting the power factor of the DC power supply output by the rectification circuit. A source PFC circuit, a buffer circuit for reducing switching loss and electromagnetic interference of the active PFC circuit, a DC power output terminal for outputting a preset DC voltage, a feedback circuit for collecting the voltage of the DC power output terminal, and It is used to output the corresponding PWM control signal to the PWM control circuit of the active PFC circuit according to the voltage collected by the feedback circuit; the rectifier circuit is connected between the input end of the AC power supply and the input end of the active PFC circuit; the buffer circuit and the active PFC circuit The circuit is connected; the output end of the DC power supply is connected with the output end of the active PFC circuit; the input end of the feedback circuit is connected with the output end of the DC power supply, and the output end of the feedback circuit is connected with the input end of the PWM control circuit; the output end of the PWM control circuit is connected with the Control terminal connection for active PFC circuit. The power factor correction circuit of the utility model reduces the switching loss, improves the output power of the circuit, and the utility model greatly reduces the electromagnetic interference in the circuit, thereby improving the safety performance of the circuit; at the same time, the utility model also has The advantages of simple circuit structure and easy realization.

Description of drawings

Fig. 1 is the circuit structural block diagram of the utility model power factor correction circuit;

Fig. 2 is the circuit structural diagram of the utility model power factor correction circuit;

Fig. 3 is a waveform diagram of the working principle of the power factor correction circuit of the present invention.

The realization of the purpose of the utility model, functional characteristics and advantages will be further described in conjunction with the embodiments and with reference to the accompanying drawings.

Detailed ways

It should be understood that the specific embodiments described here are only used to explain the utility model, and are not intended to limit the utility model.

The utility model provides a power factor correction circuit. Fig. 1 is a block diagram of the circuit structure of the power factor correction circuit of the present invention.

Referring to Fig. 1, the utility model power factor correction circuit comprises AC power input terminal 101, rectifier circuit 102, active PFC circuit 103, buffer circuit 104, DC power output terminal 105, feedback circuit 106 and PWM control circuit 107.

Among them, the AC power input terminal 101 is used to input the AC power; the rectifier circuit 102 is used to rectify the AC power input by the AC power input terminal 101; The power factor of the power supply is corrected; the buffer circuit 104 is used to reduce the switching loss and electromagnetic interference of the active PFC circuit 103; the DC power supply output terminal 105 is used to output the preset DC voltage Vout; the feedback circuit 106 is used for the DC The preset DC voltage Vout output by the power supply output terminal 105 is collected; the PWM control circuit 107 is used to output a corresponding PWM control signal to the active PFC circuit 103 according to the voltage collected by the feedback circuit 106, so as to control the active PFC circuit 103 work.

Specifically, the rectifier circuit 102 is connected between the AC power input terminal 101 and the input terminal of the active PFC circuit 103; the buffer circuit 104 is connected to the active PFC circuit 103; the DC power output terminal 105 is connected to the output terminal of the active PFC circuit 103 Connect; the input end of the feedback circuit 106 is connected with the DC power supply output end 105, the output end of the feedback circuit 106 is connected with the input end of the PWM control circuit 107; the output end of the PWM control circuit 107 is connected with the control end of the active PFC circuit 103.

Fig. 2 is a circuit structure diagram of the power factor correction circuit of the present invention.

Referring to Fig. 2, the rectifier circuit 102 in the present embodiment is a rectifier bridge stack, and the rectifier bridge stack includes the first pin, the second pin, the third pin and the fourth pin; the AC power input in the power factor correction circuit of the utility model The terminal 101 includes a first AC input terminal a and a second AC input terminal b. Wherein the 2nd pin of the rectifier bridge stack 102 is connected with the first AC input end a of the AC power supply input end 101, the 4th pin of the rectification bridge stack 102 is connected with the second AC input end b of the AC power supply input end 101, and the rectification bridge stack The first pin of 102 is connected to the positive pole of the input end of the active PFC circuit 103, and the third pin of the rectifier bridge stack 102 is connected to the negative pole of the input end of the active PFC circuit 103;

The active PFC circuit 103 in this embodiment includes a first inductor L, a MOS switch VS, a first diode D and a first capacitor CB. Specifically, the first end of the first inductor L is the positive pole of the input end of the active PFC circuit 103, the positive pole of the input end of the active PFC circuit 103 is connected to the first pin of the rectifier bridge stack 102, and the second end of the first inductor L terminal is connected to the buffer circuit 104; the drain of the MOS switch tube VS is connected to the second end of the first inductor L, the drain of the MOS switch tube VS is also connected to the buffer circuit 104, and the gate of the MOS switch tube VS is connected to the PWM control circuit The output terminal of 107 is connected, the source of the MOS switching tube VS is the negative pole of the input terminal of the PFC circuit, and the negative pole of the input terminal of the PFC circuit is connected to the third pin of the rectifier bridge stack 102; the anode of the first diode D is connected to the buffer circuit 104 connected, the cathode of the first diode D is connected to the DC power supply output terminal 105; the first terminal of the first capacitor CB is connected to the DC voltage output terminal 105, and the second terminal of the first capacitor CB is connected to the source of the MOS switch tube VS connect;

The snubber circuit 104 in this embodiment includes a second inductor L1, a second diode D1, a third diode D2, a fourth diode D3, a second capacitor C1 and a third capacitor C2. Specifically, the first end of the second inductor L1 is connected to the second end of the first inductor L in the active PFC circuit 103, and the second end of the second inductor L1 is connected to the first diode D in the active PFC circuit 103. Anode connection; the anode of the second diode D1 is connected to the drain of the MOS switch VS in the active PFC circuit 103, and the cathode of the second diode D1 is connected to the anode of the third diode D2; the third diode The cathode of the tube D2 is connected to the anode of the fourth diode D3; the cathode of the fourth diode D3 is connected to the cathode of the first diode D in the active PFC circuit 103; the first end of the second capacitor C1 is connected to Between the second inductor L1 and the anode of the first diode D in the active PFC circuit 103, the second terminal of the second capacitor C1 is connected between the cathode of the third diode D2 and the anode of the fourth diode D3 Between; the first end of the third capacitor C2 is connected between the cathode of the second diode D1 and the anode of the third diode D2, and the second end of the third capacitor C2 is connected to the MOS switch tube in the active PFC circuit 103 Source connection of VS;

The feedback circuit 106 in this embodiment includes a first resistor R1 and a second resistor R2. Specifically, the first end of the first resistor R1 is connected to the output terminal 105 of the DC power supply, the second end of the first resistor R1 is connected to the first end of the second resistor R2; the second end of the second resistor R2 is connected to the active PFC The source connection of the MOS switch tube VS in the circuit 103;

The input terminal of the PWM control circuit 107 in this embodiment is connected between the first resistor R1 and the second resistor R2 in the feedback circuit 106, and the MOS switch tube VS in the active PFC circuit 103 is the control terminal of the active PFC circuit 103, The control terminal of the active PFC circuit 103 is connected to the output terminal of the PWM control circuit 107 .

Fig. 3 is a waveform diagram of the working principle of the power factor correction circuit of the present invention.

Referring to Fig. 2 and Fig. 3 together, the operating principle of the power factor correction circuit of the present invention is specifically described as follows: (1) During T0-T1, when the MOS switching tube VS in the active PFC circuit 103 is turned off, the first two The pole diode D is turned on, and the current ID on the first inductor L flows into the DC power output terminal 105 through the second inductor L1 in the buffer circuit 104 and the first diode D in the active PFC circuit 103, and then from the DC The output terminal 105 of the power supply flows to the load (not shown in the figure), at this time, the current flowing through the second diode D1, the third diode D2, the fourth diode D3 and the MOS switch VS is 0, and the second The voltage VC1 on the capacitor C1 is 0, and the voltage VC2 on the third capacitor C2 is equal to the voltage VL of the output terminal 105 of the DC power supply; (2) During T1-T2, the MOS switch VS in the active PFC circuit 103 is turned on at T1 , the voltage VVS between the drain and source of the MOS switch VS drops rapidly to 0, while the current flowing through the MOS switch VS increases linearly and slowly, thus realizing the ZCS conduction of the MOS switch VS (ZCS, ZeroCurrentSwitch, zero current switch), at this time, the first diode D has not yet been turned off, the current ID on the first inductor L and the current IL1 on the second inductor L1 decrease linearly; (3) During T2-T3, at T2 time, the first When the current ID on the inductor L decreases to 0 and reversely increases to the reverse recovery current peak value IRR, then the reverse current rapidly decreases to 0, the reverse recovery period of the first diode D ends, and the second A diode D is turned off, and then the third diode D2 is turned on; (4) During T3-T4, at T3 time, the third diode D2 is turned on, the second capacitor C1, the third capacitor C2 and the second capacitor C2 The second inductor L1 forms a resonant loop through the MOS switch VS and the third diode D2, the third capacitor C2 is discharged, the second capacitor C1 is charged, and the current in the second inductor L1 continues to decrease. When the voltage VC1 across the second capacitor C1 is equal to the voltage VC2 across the third capacitor C2 (that is, when VC1=VC2), the current IL1 of the second inductor L1 reaches a negative maximum value, and the current IVS of the MOS switch VS reaches a positive value. Maximum value; (5) During T4-T5, at time T4, the third capacitor C2 is completely discharged, the voltage VC2 across the third capacitor C2 is 0, the second diode D1 is turned on, the second inductor L1, the second capacitor C1 Through the second diode D1 and the third diode D2 to form a resonant circuit, the energy on the second inductor L1 is transferred to the second capacitor C1, the current IL1 of the second inductor L1 starts to rise, and the second capacitor C1 continues to charge, The voltage VC1 across the second capacitor C1 continues to increase, and the current IVS of the MOS switch VS decreases; (6) During T5-T6, at T5, the current IL1 on the second inductor L1 is equal to 0, and the second capacitor C1 stops charging , the second diode D1 and the third diode D2 are turned off. At this time, the current IVS of the MOS switch tube VS is equal to the current ID on the first inductor L (i.e. IVS=ID); (7) During T6-T7, at T6 time, the MOS switch tube VS is turned off, and the current flowing through the MOS switch tube VS The current IVS rapidly decreases to 0, the first inductor L charges the third capacitor C2 with a constant current through the second diode D1, the voltage VC2 on the third capacitor C2 increases linearly, and the increase rate dv/dt of VC2 is: dv/ dt=ID/C2, so that the voltage VVS between the drain and source of the MOS switch VS rises linearly and slowly, thereby realizing the ZVS (Zero Voltage Switch, zero voltage switch) shutdown of the MOS switch VS; (8) T7 During -T8, at time T7, when the MOS switch VS realizes ZVS turn-off, the voltage VC2 across the third capacitor C2 is equal to the voltage VL across the first inductor L (that is, VC2=VL), and the third diode D2, the fourth The diode D3 is turned on, the second inductor L1 and the second capacitor C1 form a parallel resonant circuit through the second diode D1 and the third diode D2, the current ID of the first inductor L increases, and the current ID of the second capacitor C1 The voltage VC1 decreases, and after a quarter cycle of resonance, the current on the second inductor L1 drops to 0, and the second diode D1 and the third diode D2 are turned off; (9) During T8-T9, At time T8, when the second diode D1 and the third diode D2 are turned off, the voltage VC1 across the second capacitor C1 has not been discharged to 0, and the current ID on the first inductor L flows through the second inductor L1, the second inductor L The second capacitor C1 and the fourth diode D3 connect to the first capacitor CB to discharge the second capacitor C1. At time T9, when the second capacitor C1 is fully discharged, the voltage VC1 across the second capacitor C1 is 0, and the energy stored in the second capacitor C1 is released to the load through the DC power output terminal 105 . At this point, one working cycle ends, and then enters the next working cycle. The working principles of all subsequent working cycles in this embodiment are the same as those described above, and will not be repeated here.

The power factor correction circuit of the utility model suppresses the active PFC during the reverse recovery period of the first diode D of the active PFC circuit 103 by connecting the second inductance L1 in series with the first diode D of the active PFC circuit 103. The instantaneous surge current on the MOS switch tube VS in the circuit 103; and, by connecting the third capacitor C2 in parallel on the MOS switch tube VS to suppress the voltage VVS between the drain and the source when the MOS switch tube VS is turned off rate of ascent. When the power factor correction circuit of the utility model is turned on, the voltage VVS between the drain and the source of the MOS switch VS drops rapidly to 0, and the current flowing through the MOS switch VS rises linearly and slowly; When the MOS switch VS is turned off, the current flowing through the MOS switch VS drops rapidly to 0, and the voltage VVS between the drain and the source of the MOS switch VS rises linearly and slowly. The power factor correction circuit of the utility model reduces the switching loss and improves the output power of the circuit. At the same time, the utility model greatly reduces the electromagnetic interference of the circuit, thereby enhancing the safety performance of the circuit.

The power factor correction circuit proposed by the utility model includes an AC power input terminal for inputting AC power, a rectifying circuit for rectifying the AC power, and a PFC for correcting the power factor of the DC power output from the rectifying circuit circuit, a buffer circuit for reducing switching loss and electromagnetic interference of a PFC circuit, a DC power output terminal for outputting a preset DC voltage, a feedback circuit for collecting the voltage of the DC power output terminal, and a feedback circuit for The voltage collected by the circuit outputs the corresponding PWM control signal to the PWM control circuit of the PFC circuit; the rectifier circuit is connected between the input terminal of the AC power supply and the input terminal of the PFC circuit; the buffer circuit is connected to the PFC circuit; the output terminal of the DC power supply is connected to the PFC circuit The output terminal of the feedback circuit is connected to the output terminal of the DC power supply, and the output terminal of the feedback circuit is connected to the input terminal of the PWM control circuit; the output terminal of the PWM control circuit is connected to the control terminal of the PFC circuit. The power factor correction circuit of the utility model reduces the switching loss, improves the output power of the circuit, and the utility model greatly reduces the electromagnetic interference in the circuit, thereby improving the safety performance of the circuit; at the same time, the utility model also has The advantages of simple circuit structure and easy realization.

The utility model also proposes a TV set, which includes a power factor correction circuit, the circuit structure and circuit operation principle of the power factor correction circuit are the same as the circuit structure and circuit operation of the power factor correction circuit described in the above embodiment The principle is the same and will not be repeated here.

The above descriptions are only preferred embodiments of the present utility model, and are not therefore limiting the patent scope of the present utility model. Any equivalent structure or equivalent process transformation made by using the specification of the utility model and the contents of the accompanying drawings may be directly or indirectly used in Other relevant technical fields are all included in the patent protection scope of the present utility model in the same way.

Claims (7)

1. A power factor correction circuit comprises an alternating current power supply input end, a rectification circuit, an active PFC circuit, a direct current power supply output end, a feedback circuit and a PWM control circuit, and is characterized by further comprising a buffer circuit used for reducing the switching loss and the electromagnetic interference of the active PFC circuit; wherein,

the rectification circuit is connected between the input end of the alternating current power supply and the input end of the active PFC circuit; the buffer circuit is connected with the active PFC circuit; the output end of the direct current power supply is connected with the output end of the active PFC circuit; the input end of the feedback circuit is connected with the output end of the direct current power supply, and the output end of the feedback circuit is connected with the input end of the PWM control circuit; and the output end of the PWM control circuit is connected with the control end of the active PFC circuit.

2. The pfc circuit of claim 1 wherein the rectifier circuit is a bridge stack comprising a 1 st pin, a 2 nd pin, a 3 rd pin, and a 4 th pin; the alternating current power supply input end comprises a first alternating current input end and a second alternating current input end; the No. 2 pin of the rectifier bridge stack is connected with the first alternating current input end, the No. 4 pin of the rectifier bridge stack is connected with the second alternating current input end, the No. 1 pin of the rectifier bridge stack is connected with the positive pole of the input end of the active PFC circuit, and the No. 3 pin of the rectifier bridge stack is connected with the negative pole of the input end of the active PFC circuit.

3. The PFC circuit of claim 2, wherein the active PFC circuit comprises a first inductor, a MOS switch, a first diode, and a first capacitor; wherein,

the first end of the first inductor is the positive electrode of the input end of the active PFC circuit, the positive electrode is connected with the 1 st pin of the rectifier bridge stack, and the second end of the first inductor is connected with the buffer circuit; the drain electrode of the MOS switch tube is connected with the second end of the first inductor, the drain electrode of the MOS switch tube is also connected with the buffer circuit, the grid electrode of the MOS switch tube is connected with the output end of the PWM control circuit, the source electrode of the MOS switch tube is the negative electrode of the input end of the active PFC circuit, and the negative electrode is connected with the 3 rd pin of the rectifier bridge stack; the anode of the first diode is connected with the buffer circuit, and the cathode of the first diode is connected with the output end of the direct-current power supply; the first end of the first capacitor is connected with the direct-current voltage output end, and the second end of the first capacitor is connected with the source electrode of the MOS switch tube.

4. The PFC circuit of claim 3, wherein the snubber circuit comprises a second inductor, a second diode, a third diode, a fourth diode, a second capacitor, and a third capacitor; wherein,

the first end of the second inductor is connected with the second end of the first inductor in the active PFC circuit, and the second end of the second inductor is connected with the anode of the first diode in the active PFC circuit; the anode of the second diode is connected with the drain electrode of the MOS switch tube in the active PFC circuit, and the cathode of the second diode is connected with the anode of the third diode; the cathode of the third diode is connected with the anode of the fourth diode; the cathode of the fourth diode is connected with the cathode of the first diode in the active PFC circuit; the first end of the second capacitor is connected between the second inductor and the anode of the first diode in the active PFC circuit, and the second end of the second capacitor is connected between the cathode of the third diode and the anode of the fourth diode; the first end of the third capacitor is connected between the cathode of the second diode and the anode of the third diode, and the second end of the third capacitor is connected with the source electrode of the MOS switch tube in the active PFC circuit.

5. The PFC circuit of claim 4, wherein the feedback circuit comprises a first resistor and a second resistor; wherein,

the first end of the first resistor is connected with the output end of the direct-current power supply, and the second end of the first resistor is connected with the first end of the second resistor; and the second end of the second resistor is connected with the source electrode of the MOS switch tube in the active PFC circuit.

6. The power factor correction circuit of claim 5, wherein the input terminal of the PWM control circuit is connected between a first resistor and a second resistor in the feedback circuit, the MOS switch tube in the active PFC circuit is the control terminal of the active PFC circuit, and the control terminal is connected with the output terminal of the PWM control circuit.

7. A television set comprising the power factor correction circuit of any one of claims 1 to 6.