CN203813767U - Circuit for eliminating harmonic distortion in sampling and holding circuit - Google Patents
Circuit for eliminating harmonic distortion in sampling and holding circuit Download PDFInfo
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Abstract
The utility model discloses a circuit for eliminating the harmonic distortion in a sampling and holding circuit. An auxiliary sampling part of the circuit eliminates the distortion generated by a main sampling part of the sampling and holding circuit. The offset distortion of the auxiliary sampling part of the circuit is properly greater than the distortion generated by the main sampling part, and the distortion of the auxiliary sampling part is reduced till the offset distortion is properly equal to the distortion of the main sampling part. Finally, the offset distortion of the auxiliary sampling part is subtracted from the distortion of the main sampling part, so as to offset all the distortion basically, and keep the real part of an input signal.
Description
Technical field:
The present invention relates to sampling and holding circuit.More particularly, the circuit the present invention relates to and method are to eliminate the harmonic distortion of sampling and holding circuit generation.
Background technology:
Sampling and holding circuit are widely used in sampled voltage and remain on a constant level, to such an extent as to another circuit is sampled as being connected to and the analog to digital converter of holding circuit, can measure this voltage.In many samplings and holding circuit, but, the harmonic distortion that circuit element produces has limited the useful voltage scope of input signal, limit the useful frequency range of input signal, and need a circuit designers in circuit, to use more expensive device, eliminate distortion, otherwise can produce distortion by inferior element.The threshold value of metal-oxide-semiconductor field effect transistor, bulk effect, the variation of on-off ratio and process, causes the nonlinear resistance property in sampling and holding circuit switch, thus the distortion producing.This distortion by sample and holding circuit switch in parasitic capacitance produce, electric charge is injected in the switch of some modulation by the switch of other samplings and holding circuit, and the nonlinear load electric current in input power load is to be caused by semiconductor junction switch in sampling and holding circuit and end resistance.
Summary of the invention:
In sum, the object of circuit provided by the invention and method is the harmonic distortion producing in order to eliminate sampling and holding circuit.
Another object of circuit provided by the invention and method is the harmonic distortion producing in order to eliminate sampling and holding circuit, and this harmonic distortion is to be caused by the nonlinear resistance property in sampling and holding circuit switch.
Another object of circuit provided by the invention and method is the harmonic distortion producing in order to eliminate sampling and holding circuit, and this harmonic distortion is to be caused by the parasitic capacitance in sampling and holding circuit switch.
Another object of circuit provided by the invention and method is the harmonic distortion producing in order to eliminate sampling and holding circuit, and this harmonic distortion is to be caused by the electric charge being injected in sampling and holding circuit modulation switch.
The further object of circuit provided by the invention and method is the harmonic distortion producing in order to eliminate sampling and holding circuit, this harmonic distortion is to be caused by nonlinear load electric current, and the nonlinear load electric current in input power load is to be caused by semiconductor junction switch in sampling and holding circuit and end resistance.
Another further object of circuit provided by the invention and method is the harmonic distortion producing in order to eliminate sampling and holding circuit, and this harmonic distortion is that the end resistance in sampling and holding circuit switch causes.
Technical solution of the present invention:
According to the present invention, above-mentioned purpose of the present invention is to realize by the harmonic distortion that elimination is sampled and holding circuit produces.More particularly, in circuit of the present invention and method, sampling and holding circuit comprise an auxiliary sampling part, produce distortion and offset the distortion that main sampling section produces.
The distortion producing in order to eliminate main sampling section, first, the auxiliary sampling part of circuit produces offsets distortion, and the distortion producing than main sampling section is large.In the time that auxiliary sampling part produces larger distortion, the signal of auxiliary sampling part sampling equals being retained of main sampling section with a dimension scale.The size of auxiliary sampling partial distortion and sampled signal is reduced, to such an extent as to counteracting distortion equals the distortion of main sampling section in size, and therefore, the signal of auxiliary sampling part sampling is less than the signal of main sampling section sampling.
Finally, the sampled signal of auxiliary sampling part and elimination distortion are removed by sampled signal and the elimination distortion of main sampling section, and therefore, all distortions and a part of sampled signal have been eliminated substantially.In this mode, harmonic distortion is by the distortion cancellation of auxiliary sampling part.
The present invention goes out a kind of circuit of eliminating harmonic distortion in sampling and holding circuit, this circuit comprises an auxiliary sampling part, harmonic carcellation distortion, a part for the sampling harmonic distortion producing corresponding to above-mentioned main sampling section, wherein, above-mentioned auxiliary sampling part comprises at least one input switch device, in the time that input signal is used for the output of at least one input switch device, produce a part of harmonic carcellation distortion, to receive the input signal of input; A kind of combinational circuit, combines the harmonic distortion of sampling distortion and counteracting, to such an extent as to the sampling harmonic distortion of at least a portion is offset in the harmonic distortion of above-mentioned counteracting, and only eliminates the output signal of an above-mentioned part.
Further, auxiliary sampling part produces the harmonic distortion of above-mentioned counteracting, to such an extent as to the harmonic distortion of offsetting is larger than the sampling harmonic distortion of above-mentioned at least a portion, then, reduce the harmonic distortion of offsetting, to such an extent as to the harmonic distortion of offsetting is substantially equal to the sampling harmonic distortion of at least a portion; Auxiliary sampling part further comprises a sampling capacitance circuit, the input signal that the output of above-mentioned at least one the input switch device of sampling provides; At least one above-mentioned input switch device comprises an input redirect switch, transistor bridge, a diode bridge that diode connects; The electric bridge of at least one above-mentioned input switch device comprises a transistor and a resistance; Above-mentioned sampling capacitance circuit comprises a Single Capacitance device; Above-mentioned sampling capacitance circuit comprises a capacitor network.
Further, at least one above-mentioned input switch device produces harmonic carcellation distortion, to such an extent as to by the reduced size of at least one the input switch device in corresponding main sampling section, make the harmonic distortion of counteracting larger than the sampling harmonic distortion of above-mentioned at least a portion; Above-mentioned sampling capacitance circuit reduces the harmonic distortion of offsetting, and by the also little electric capacity of sampling capacitance circuit than in corresponding main sampling section, makes the harmonic distortion of offsetting be substantially equal to the sampling harmonic distortion of at least a portion.
Further, auxiliary sampling part, by total capacitance larger in main sampling section, produces the harmonic distortion of offsetting; Auxiliary sampling part further comprises a base resistance, and the output that is used for connecting at least one input switch device is to sampling capacitance circuit, and wherein the size of this base resistance has roughly the same size with the base resistance in corresponding main sampling section; Auxiliary sampling part also comprises a capacity load, is connected to the output of at least one input switch device, and wherein due to the parasitic capacitance in auxiliary sampling part, this capacitive load causes distortion; Due to the parasitic capacitance in main sampling section, auxiliary sampling part has been eliminated a part of distortion substantially; Auxiliary sampling part also comprises multiple cascade sampled points, and an extra switching device is connected to the output of above-mentioned at least one input switch device, produces distortion; Due to input power resistance, substantially eliminate the distortion of at least a portion; Due to the end resistance of at least one input switch device in above-mentioned main sampling section, the end resistance of above-mentioned at least one input switch device produces distortion, the distortion of having offset at least a portion.
Further, said method comprises the signal that receives at least one input switch device input; On at least one input switch device of auxiliary sampling part, produce and offset distortion, a part of sampling distortion producing corresponding to main sampling section; Control inputs signal application is in the output of at least one input switch device; The harmonic distortion of sampling distortion and counteracting is combined, to such an extent as to the sampling harmonic distortion of at least a portion is offset in the harmonic distortion of above-mentioned counteracting, and only eliminate the output signal of an above-mentioned part.
Further, because auxiliary sampling part has larger total capacitance than main sampling section, the harmonic distortion of counteracting is larger than the sampling harmonic distortion of above-mentioned at least a portion; Because sampling capacitance circuit has than the less electric capacity of corresponding main sampling section up-sampling electric capacity, reduce the harmonic distortion of offsetting, to such an extent as to the harmonic distortion of offsetting is substantially equal to the sampling harmonic distortion of at least a portion.
Further, the method connects the output of capacity load at least one input switch device, and wherein, due to the parasitic capacitance in auxiliary sampling part, capacity load produces distortion; Due to the parasitic capacitance in main sampling section, auxiliary sampling part has been eliminated the distortion of at least a portion substantially.
Contrast patent documentation: CN2101345U passive suppressor for source current harmonic distortion 91215965.0
Brief description of the drawings:
Object of the present invention will describe in detail below, and accompanying drawing will be further described advantage of the present invention.The reference character of part of devices is indicated in the drawings.
Fig. 1 is the schematic diagram of a known sampling and holding circuit;
Fig. 2 is a sampling and holding circuit schematic diagram, and it comprises an auxiliary sampling part, produces and offsets distortion;
Fig. 3 is a known difference sampling and the schematic diagram of holding circuit;
Fig. 4 is the schematic diagram of a difference sampling and holding circuit, and it comprises two auxiliary sampling parts, and distortion is offset in each generation;
Fig. 5 is that sampling and holding circuit schematic diagram are eliminated in a distortion, wherein, and single input redirect switch instead of the input redirect switch of its each main sampling section of use and auxiliary sampling part;
Fig. 6 is a sampling and holding circuit schematic diagram, and in single input redirect switch gate of each main sampling section and auxiliary sampling part, the elimination of distortion is based on bootstrap capacitor;
Fig. 7 is a sampling and holding circuit schematic diagram, and it comprises an auxiliary sampling part, and wherein capacitive load eliminates by the right parasitic capacitance of input redirect switch the distortion that main sampling section produces;
Fig. 8 is a sampling and holding circuit schematic diagram, and wherein, the sampling time of auxiliary sampling part improves by the use of cascade sampling point;
Fig. 9 is a sampling and holding circuit schematic diagram, and wherein, the sampling time of auxiliary sampling part is further by keeping the input redirect switch connection on the first cascade sampling point to improve;
Figure 10 is a sampling and holding circuit schematic diagram, and wherein, the base resistance of main sampling section replaces with pole changer resistance, thereby mates better the sampling time of auxiliary sampling part;
Figure 11 is a sampling and holding circuit schematic diagram, and wherein, another pole changer, to being included into auxiliary sampling part with resistance, produces and offsets distortion, corresponding with the distortion that input power resistance produces;
Figure 12 is the schematic diagram of a difference sampling and holding circuit, and the distortion of injecting switch-charge is caused by the modulation of the sampling switch of main sampling section, and offsets distortion by the sampling switch by corresponding auxiliary sampling section;
Figure 13 is sampling and the holding circuit schematic diagram of a distortion cancellation, and it uses bipolar transistor;
Figure 14 is sampling and the holding circuit schematic diagram of a distortion cancellation, and it uses diode bridge;
Figure 15 is sampling and the holding circuit schematic diagram of a distortion cancellation, the combination of bipolar transistor of its use and diode bridge;
Figure 16 is a sampling and holding circuit schematic diagram, in main sampling section, due to the right switch resistance drain-source utmost point of input redirect switch, has eliminated distortion.
Embodiment:
Circuit of the present invention and method are to eliminate the harmonic distortion of sampling and holding circuit generation.
As shown in Figure 1, known sampling and holding circuit 100.Circuit 100 comprises inverter group 102, and the time of control circuit 100, to respond the inhibit signal that keeps input 134; The voltage of main sampling section 104 tracking and inhibit signal input 136, to such an extent as to this voltage can be measured at signal output part 138 places.Inverter group 102 is made up of six inverters 106,108,110,112,114 and 116.Main sampling section 104 is made up of 118 (forming by input change over switch 120 and 122), base resistance 124, base electric capacity 126, ground connection pole changer 128, sampling capacitance 130 and sampling switch 132 input redirect switch.As shown in the figure, switch 120,122,128 and 132 is metal-oxide-semiconductor field effect transistors, but J type field effect transistor, bipolar transistor and other applicable switching devices can be for realizing circuit 100.Although be not presented in Fig. 1, the substrate of all N-channel MOS field effect transistor of switch 122,128 and 132 is all connected to earth terminal 140.
As shown in the figure, inverter 106,108,110,112,114 and 116 is connected in series with each inverter output respectively, to drive the input of next inverter.The input of the first inverter 106 is by keeping input 134 to drive.Keeping input 134 is high level inputs, when being transitioned into high level from low level and maintaining, cause that circuit 100 gathers and the voltage at inhibit signal input 136 places, to such an extent as to signal input part can be measured at signal output part 138 places.The output of inverter 106,112,114 and 116 is used for switching on and off sampling switch 132, input redirect switch 120,122 and ground connection pole changer 128.
As mentioned above, the input signal of main sampling section sampling is to receive by signal input part 136.Signal input part 136 is connected to the drain electrode of source electrode and the switch 122 of switch 120.The grid of switch 120 and 122 is connected respectively to the output of inverter 112 and 114.Switch 120 is connected to positive voltage source 142 places, prevents the drain electrode of switch or the conduction of source electrode.Together with the source electrode of the drain electrode of switch 120 and switch 122, be connected to one end of base resistance 124.The other end of base resistance 124 is connected to one end of base electric capacity 126, drain electrode and the sampling capacitance 130 of ground connection pole changer 128.The source electrode of the other end of base electric capacity 126 and switch 128 is connected to earth terminal 140.The grid of switch 128 is connected to the output of inverter 116.The other end of sampling capacitance 130 is connected to drain electrode and the signal output part 138 of sampling switch 132.Finally, the grid of sampling switch 132 is connected to the output of inverter 106.
In operation, the behavior of sampling and holding circuit 100 is as follows.In the time keeping input 134 to be low level, the grid of switch 120 and 122 is driven by low level and high level by inverter 112 and 114 respectively.This causes switch 120 and 122 to be connected.Meanwhile, keeping input 134 is low levels, and the grid of switch 128 and 132 is driven by low level and high level respectively, causes respectively switch 128 and 132 disconnect and connect.Due to these states of switch 120,122,128 and 132, sampling capacitance 130 charging and dischargings, with the change in voltage of response signal input 136.
Keeping input 134 from low transition is high level, sampling switch 132 disconnects, and causes the electric charge on sampling capacitance 130 constant.In the time that switch 132 disconnects, base resistance 124 and base electric capacity 126 are coupled sampling capacitance 130 to input redirect switch 120,122 and signal input part 136.Inverter 108,110,112 and 114 causes transmission delay, and input redirect switch 120 and 122 is disconnected, and causes sampling capacitance 130 and signal input part 136 more isolated.Finally, ground connection pole changer 128 is connected, and provides ground connection reference voltage by the voltage on sampling capacitance 130, and it can be detected at signal output part 138 places.
As mentioned above, circuit of the present invention and method, the distortion of the one or more main sampling section generation that is used for eliminating sampling and holding circuit, as shown in Figure 1.Distortion sources in main sampling section 104 comprises that input redirect switch is to 118 nonlinear resistance property and parasitic capacitance, injection modulated charge on sampling switch 132, nonlinear load electric current,, cause by flowing through input power resistor current 118 semiconductor junction and earthing switch 128 by pole changer.
Fig. 2 has shown a sampling and holding circuit 200, according to principle of the present invention, this sampling and holding circuit 200 comprise auxiliary sampling part 204, are used for offsetting the harmonic distortion 118 nonlinear resistance property being caused by the input redirect switch of main sampling section 104.As shown in the figure, circuit 200 comprises inverter group 102, main sampling section 104 and the auxiliary sampling part 204 being driven by signal input part 136, differential amplifier 244 driving signal input 138 and differential amplifier 244 are driven by main sampling section 104 and auxiliary sampling part 204.It is identical that the element of inverter group 102 and main sampling section 104 are roughly described with Fig. 1 circuit 100.
The selection of the device of auxiliary sampling part 204 is corresponding to main sampling section 104, therefore, and the element similar (for example, the operation of sampling switch 232 is roughly identical with the sampling switch 132 of main sampling section 104) of basic and main sampling section 104.But the size of these elements is different from the element of main sampling section 104.Although circuit 200 use base resistance 124 and 224 and base electric capacity 126 and 226 shows, the present invention can use one or both of these types of devices.
Eliminate in order to make the auxiliary sampling part 204 of circuit 200 distortion that main sampling section 104 produces, auxiliary sampling part 204 elements are used for producing the distortion being in equal proportions with main sampling section 104, are less than and only produce an output signal ratio output signal that main sampling section 104 produces.In order to realize it, first by some factors, increase the distortion of auxiliary sampling part 204, and maintain the constant magnitude of output signal.After distortion increases, distortion and output signal all reduce by identical factor, come distortion that generation ratio is identical and less output signal.
This method can be by selecting the input redirect switch 220,222 of suitable auxiliary sampling part 204, and base electric capacity 226 and sampling capacitance 230, corresponding to the element in main sampling section 104.First, increase the distortion that auxiliary sampling part 204 produces, increase the size of output signal, input redirect switch 220 and 222 is less than the input redirect switch of main sampling section 104 120 and 122.In addition, the total capacitance of base electric capacity 226 and sampling capacitance 230 is greater than the total capacitance of base electric capacity 126 and the sampling capacitance 130 of main sampling section 104.Then, reduce distortion and the output signal of auxiliary sampling part 204, to such an extent as to the combination of this distortion and output signal and main sampling section 104, sampling capacitance 230 is less than the sampling capacitance 130 of main sampling section 104.In addition, the ratio of gains positive input terminal of differential amplifier 244 negative input ends little, thus reduce the distortion of auxiliary sampling part 204, match to such an extent as to eliminate distortion time in it and differential amplifier 244.
For example, the input redirect switch 220 and 222 of auxiliary sampling part 204 be main sampling section 104 input redirect switch 120 and 122 sizes 1/4.The total capacitance of base electric capacity 226 and sampling capacitance 230 is consistent with the total capacitance in main sampling section 104, and the distortion that main sampling section 104 produces is 4 times of auxiliary sampling part 204.The size of sampling capacitance 230 is 1/4 of sampling capacitances 130.The size of the output signal of sampling capacitance 230 is 1/4 of sampling capacitances 130.
Because the distortion that in auxiliary sampling part 204, input redirect switch 220 and 222 produces is four times that in main sampling section 104, input redirect switch 120 and 122 produces, the distortion of sampling capacitance 230 equals sampling capacitance 130, has therefore been eliminated.But the output signal of auxiliary sampling part 204 is 1/4 of main sampling section 104, to such an extent as to the output signal of main sampling section 104 can not be eliminated.Therefore, in the time that the distortion of output signal and sampling capacitance 130 and 230 is input to differential amplifier 244, all distortions of sampling capacitance 130 and 230 are eliminated, and only have 1/4 output signal to be eliminated.
In order to compensate the loss of output signal, select the element of auxiliary sampling part 204, it can increase by increasing the size of sampling capacitance 130 output signal of main sampling section 104.For example, increase the sampling capacitance 130 of 1/3 size in main sampling section 104, to cause in the time that 1/4 output signal loses, remaining output signal is the same large with signal corresponding in circuit.
For the sampling time of the main sampling section 104 of balance and auxiliary sampling part 204, select base resistance 124 and 224, RC time constant is matched.These time constants be approximately the resistance of input switch pole changer (in the time connecting) and base resistance 124 and 224 to 118 and 218 and be multiplied by base electric capacity 126 and 226 with the electric capacity of sampling capacitance 130 and 230 with.Therefore, in the above example, because the total capacitance of main and auxiliary sampling part equates, each base resistance 124 and 224 is selected, to such an extent as to input redirect switch to 118 and 218 with the resistance of base resistance 124 and 224 with equal corresponding mainly and the resistance of auxiliary sampling part.
Select base resistance 224, to such an extent as to any gain error in base resistance 124 is eliminated.The impact of base resistance 224 is greater than base resistance 124, and sampling capacitance 130 is greater than sampling capacitance 230.Like this, the counteracting distortion that base resistance 224 produces is greater than the distortion that base resistance 124 produces.In the time that the size of this distortion reduces by sampling capacitance 230 subsequently, the size of offsetting distortion is identical with the distortion that base resistance 124 produces.
Known difference sampling and a holding circuit 300, as shown in Figure 3.Circuit 300 comprises inverter group 102, the time of control circuit 300; The voltage of just main sampling section 104 and 354 tracking of negative main sampling section and inhibit signal positive input terminal 346 and negative input end 348, to such an extent as to this voltage can be measured at positive signal output 350 and negative signal output 352 places.Inverter group 102 is basic identical with the circuit described in Fig. 1 with just main sampling section 104, except the input and output design of main sampling section 104 becomes 346 and 350.Negative main sampling section 354 comprises input redirect switch to 368 (forming by input switch 370 and 372), base resistance 374, base electric capacity 376, ground connection pole changer 378, sampling capacitance 380 and sampling switch 382.
In operation, each just main sampling section 104 is basic identical with the main sampling section 104 of the circuit 100 in Fig. 1 with negative main sampling section 354.In circuit 300, the source electrode distortion of just main sampling section 104 and negative main sampling section 354 is identical with main sampling section 104 in circuit in Fig. 1 100.In order to compensate these source electrode distortions, auxiliary sampling part is added in circuit 300 in the mode same with circuit 200.
Fig. 4 represents difference sampling and holding circuit 400, comprises an auxiliary sampling part, is used for harmonic carcellation distortion.As shown in the figure, circuit 400 comprises inverter group 102, just main sampling section 104 and negative main sampling section 354, positive auxiliary sampling part 481 and negative auxiliary sampling part 483.Inverter group 102, the element of just main sampling section 104 and negative main sampling section 354 identical with described in Fig. 3 substantially.Positive auxiliary sampling part 481 is basic identical with the sampling section 204 in Fig. 2, except sampling switch 232 is removed.Same, negative auxiliary sampling part 483 comprises input redirect switch to 484 (being formed by input switch 486 and 488), base resistance 490, base electric capacity 192, ground connection pole changer 494 and sampling capacitance 496.
Positive auxiliary sampling part 481 receives the input signal of positive signal input 346.Positive signal input 346 is connected to the drain electrode of source electrode and the input redirect switch 222 of input redirect switch 220, and similarly, input 136 is connected to the drain electrode of source electrode and the input redirect switch 222 of input redirect switch 220 in Fig. 2 sampling section 204.The output of sampling capacitance 230 is connected to negative signal output 352 negative input end of amplifier 244 (instead of in Fig. 2).The element of negative auxiliary sampling part 483 is roughly the same with positive auxiliary sampling part 481, and except the input of negative auxiliary sampling part 483 receives negative signal input 348, sampling capacitance 496 is connected to positive signal output 350 instead of negative signal output 352.
In operation, circuit 400 is substantially identical with the circuit 200 in Fig. 2, except two main sampling section 104 and 354 and two auxiliary sampling parts 481 and 483 substituted mutually.Therefore, in the time keeping input 134 to be low level, sampling capacitance 130 and 230 is followed the trail of the input signal of positive signal input 346, and sampling capacitance 380 and 496 is followed the trail of the input signal of negative signal input 348.In the time that input 134 is converted to high level and keeps, the signal of sampling section 104 and 481 samplings and maintenance input 346, the signal of sampling section 483 and 354 samplings and maintenance input 348.Then the signal combination of sampling section 104 and 483 is got up, and the signal of sampling section 481 and 354 also combines, and then the signal of combination is exported by positive signal output 350 and negative signal output 352.
The circuit 200 of Fig. 2 as above, the element of each auxiliary sampling part 481 and 483 may produce harmonic distortion, eliminates the harmonic distortion of main sampling section 104 and 354, does not eliminate corresponding output signal completely.
Fig. 5 represents the circuit 500 that Fig. 2 circuit 200 changes.Circuit 500 uses the single input change over switch 122 of a main sampling section 502 and the single input change over switch 222 of an auxiliary sampling part 504, instead of input redirect switch is to 118 and 218.Except input change over switch 120 with 220 and Fig. 2 in their circuit 200 of being connected separately, the connected mode of circuit 500 elements is substantially identical with Fig. 2 circuit 200.Because switch 120 and 220 (in Fig. 2) is to remove from circuit 500, compared with 220, due to the nonlinear resistance of input change over switch 122 and 222, circuit 500 has more serious distortion with input change over switch 120.But by removing switch 120 and 220, parasitic capacitance has also been removed.Although switch 120 and 220 is removed from circuit 500, switch 122 and 222 is also removed from circuit 500.
Fig. 6 represents the circuit 600 that Fig. 5 circuit 500 changes, and is further the variation of Fig. 2 circuit 200.The grid of switch 122 and 222 is connected to the output of inverter 114 in Fig. 5, and these grids can be connected to electric capacity 606 by switch 602.Electric capacity 606 is charged by power supply 604, then disconnects with power supply 604, is connected to the grid of switch 122 and 222, and is connected to input 136 by switch 602, until electricity is full of.Except these differences, the element of circuit 600 is basic identical with circuit 500 in circuit in Fig. 2 200 and Fig. 5.By carry out the grid of driving switch 122 and 222 with an electric capacity, the voltage between grid and the raceway groove of switch is fixed, and causes the raising of each equipment conducting resistance linearity.
Fig. 7 represents the circuit 700 of Fig. 2 circuit 200 another variations, non-linear due to parasitic capacitance and resistance, the distortion of the input redirect switch that it has eliminated main sampling section 104 to 118 generations.As shown in the figure, circuit 700 comprises the capacitive load 704 of an auxiliary sampling part 702.Capacitive load 704 is formed by two switches 706 and 708, and the drain electrode of switch 706 is connected to the source electrode of switch 708; The drain electrode of the source electrode of switch 706 and switch 708 is connected to drain electrode, the source electrode of switch 222 and one end of base resistance 224 of switch 220; The grid of switch 706 is connected to negative voltage source 710; The grid of switch 706 and switch 708 is connected to positive voltage source 142.Except element and the connection of capacitive load 704, the circuit 200 described in element fundamental sum Fig. 2 of circuit 700 is identical.Switch 706 and 708 is preferred sizes, to such an extent as to the distortion producing in auxiliary sampling part 702 increases.Like this, differential amplifier 244 will combine from main sampling section 104 and 702 outputs of auxiliary switch part, because the distortion of nonlinear resistance and parasitic capacitance generation has been eliminated.
Fig. 8 represents the circuit 800 of Fig. 2 circuit 200 another variations, and its cascade sampled point, for auxiliary sampling part 802, reduces the sampling time of auxiliary sampling part 802.As shown in the figure, circuit 800 comprises inverter group 102, main sampling section 104, auxiliary sampling part 802 and differential amplifier 244.The element of the main sampling section 104 of inverter group 102 and differential amplifier 244 and above-mentioned basic identical.Auxiliary sampling part 802 comprises one-level circuit 803 and secondary circuit 811 and sampling switch 232.One-level circuit 803 comprises input redirect switch to 804 (being formed by input switch 806 and 808) and base electric capacity 810.Secondary circuit 811 is basic identical with the sampling section 481 in Fig. 4.
The input of auxiliary sampling part 802 is from signal input part 136.Signal input part 136 is connected to the drain electrode of source electrode and the input redirect switch 808 of input redirect switch 806.The grid of switch 804 and 808 is connected respectively to the output of inverter 112 and 114.The source electrode of the drain electrode of switch 804 and switch 808 is connected to one end of base electric capacity 810, the drain electrode of the source electrode of input redirect switch 220 and input redirect switch 222.The other end of base electric capacity 810 is connected to earth terminal 140.The grid of switch 220 and 222 is connected respectively to the output of inverter 112 and 114.The source electrode of the drain electrode of switch 220 and switch 222 is connected to one end of base electric capacity 226, one end of the drain electrode of ground connection pole changer 228 and sampling capacitance 230.The source electrode of the other end of electric capacity 226 and switch 228 is connected to earth terminal 140.The grid of switch 228 is connected to the output of inverter 116.The other end of sampling capacitance 230 is connected to the drain electrode of sampling switch 232 and the negative input end of differential amplifier 244.Finally, the grid of switch 232 is connected to the output of inverter 106, and the source electrode of switch 232 is connected to earth terminal 140.
In operation, the operation of auxiliary sampling circuit 802 and 800 is as follows.In the time keeping input 134 to be low level, the grid of inverter 112 driving switchs 806 and 220, the grid of inverter 114 driving switchs 808 and 222, causes switch 806,220,808 and 222 to be connected.In the time keeping input 134 to be low level, the grid of switch 228 and 232 is inverted device 116 and 106 and drives, and causes switch 228 and 232 disconnect respectively and connect equally.Due to the state of switch 220,222,228,232,806 and 808, base electric capacity 226 and 810 and the voltage of sampling capacitance 230 trace signals inputs 136.
In the time that input 134 is transferred to high level and kept by low level, switch 232 disconnects, the electric charge in fixed sample electric capacity 230.In the time that switch 232 disconnects, base electric capacity 226 and 810 coupling sampling capacitances 230 to input redirect switch to 218 and 804 and signal input on 136.Then switch 220,222,806 and 808 disconnects, and further sampling capacitance 230 and signal input 136 is kept apart.Finally, switch 228 is connected, and connects one end of sampling capacitance 230 to earth terminal 140, thereby the reference voltage of sampling capacitance 230 is provided, can be measured at the input of differential amplifier 244.
In order to eliminate input redirect switch, the nonlinear resistance on 118 is changed to the distortion producing, auxiliary sampling part 802 produces one and offsets distortion, is greater than the distortion that main sampling section 104 produces.Then, the distortion that a part for counteracting distortion produces from main sampling section 104, be subtracted, to such an extent as to all distortions that main sampling section 104 produces are removed.The distortion that auxiliary sampling part 802 produces is increased 804 size by reducing input redirect switch.For the size reducing, input redirect switch is increased 804 conducting resistance.The increase of conducting resistance causes the sampling time of auxiliary sampling part 802 to increase.
By use multi-cascade sampled point circuit 803 and 811 in auxiliary sampling part 802, the sampling time of auxiliary sampling part 802 is shorter than the sampling time of auxiliary sampling part 204 (in Fig. 2).For example, circuit in Fig. 2, input redirect switch is to select input redirect switch to 118 four times to 218 distortion, base resistance 124 and 224 resistance values are zero, the combination electric capacity of base electric capacity 226 and sampling capacitance 230 equals base electric capacity 126 and sampling capacitance 130, and the sampling time of auxiliary sampling part 204 is increased to four times of main sampling section 104.In other words,, if input redirect switch is R to 118 conducting resistance, input redirect switch is 4R to 218 conducting resistance.If the total capacitance of main sampling section 104 and auxiliary sampling part 204 is C, the sampling time of main sampling section 104 is constant R*C, and the sampling time of corresponding 0.01% sampling precision is ln (0.0001) * R*C=9.2RC, wherein the sampling time of auxiliary sampling part 204 is constant 4RC, and the sampling time of corresponding 0.01% sampling precision is ln (0.0001) * 4R*C=36.8RC.
In the circuit 800 of Fig. 8, select suitable input redirect switch to 218 and 804 and the value of electric capacity 226,230 and 810, make the sampling time of auxiliary sampling part 802 shorter than the sampling time of auxiliary sampling part 204 (in Fig. 2).Continue example above, suitable input redirect switch is input redirect switch to 812 twice to 218 and 804 distortion, causes that switch is to having separately the conducting resistance of 2R and 4R.The electric capacity of suitable electric capacity 226,230 and 810 is respectively 0.25C, 0.25C and 0.5C, and causing the total capacitance that auxiliary sampling part 802 has is C.But sampling time and the level circuit 811 due to level circuit 803 with RC have sampling time of 2RC, auxiliary sampling part 802 is twices of RC and 2RC, combines and produces the arbitrary accuracy setting-up time faster than auxiliary sampling part 204.
Although circuit 800 is to be represented by two level circuit 803 and 811, the sampling time that more level circuit can be used for improving auxiliary sampling part 802.
The sampling time of the auxiliary sampling part with cascade sampled point has further been shortened in a variation of circuit 800, as shown in the circuit 900 of Fig. 9.On the one-level circuit 906 of auxiliary sampling part 904, the grid of input redirect switch 806 and 808 is not connected to the output of inverter 112 and 114, the grid of input redirect switch 806 and 808 is connected to negative voltage power supply 710 and positive voltage source 142 places separately, to such an extent as to switch 806 and 808 is always connected.In this mode, the sampling time of auxiliary sampling part 904 has almost shortened to the sampling time of secondary circuit 811.
Another of circuit 800 changes, and the sampling time of the main sampling section of balance and auxiliary sampling part, as shown in the circuit 100 of Figure 10.In this variation, pole changer to resistance 1004 for main sampling section 1002 instead of base resistance 124.By using pole changer to resistance 1004, the balance in sampling time is not manufactured the impact of change in process, temperature and other second-order effects.
Sampling pole changer is formed by switch 1006 and 1008 resistance 1004, the connection of the positive input of the drain electrode of replacement from sampling capacitance 130 to sampling switch 132 and differential amplifier.These switches make the drain electrode of switch 1006 and the source electrode of switch 1008 be connected to the output of sampling capacitance 130.The grid of switch 1006 and switch 1008 are connected in positive voltage source 142, and the grid of switch 1008 is connected on negative voltage power supply 710.The drain electrode of the source electrode of switch 1006 and switch 1008 is connected to the drain electrode of sampling switch 132 and the positive input terminal of differential amplifier 244.Sampling pole changer is best selections to resistance 1004, to such an extent as to the sampling time of main sampling section 1002 equals the sampling time of auxiliary sampling part 802.
Another variation of Fig. 2 circuit 200 is on the input power resistance of sample circuit, eliminates the distortion that nonlinear load electric current produces, as shown in figure 11.In the sampling and holding circuit of a Fig. 2, nonlinear load electric current can be produced by the semiconductor junction of input redirect switch, as switch 120,122,220 and 222.These nonlinear load electric currents may cause the non-linear of correspondence, voltage drop, and in the time that signal passes through the input power resistance of signal source circuit, sampled signal distortion.This distortion appears at main sampling section 104 and the auxiliary sampling part 204 of Fig. 2 equally.Therefore, this distortion can not be removed by the use of auxiliary sampling part 204, because the sampling capacitance of smaller szie 230 causes the distortion of relative size at the negative input end of differential amplifier 244, this distortion is less than the positive input terminal of differential amplifier 244.
In order to eliminate the distortion of this input power resistance, the distortion in auxiliary sampling part 204 must increase before receiving sampling capacitance 230, and then the distortion of sampling capacitance 230 reduces.As shown in the circuit 1100 of Figure 11, auxiliary sampling part 1104 comprises that a pole changer realizes this goal to 1106.Pole changer can be used on base resistance 224, produce similar nonlinear load electric current to 1106, thereby in auxiliary sampling part 1104, produces auxiliary input power resistance distortion.Switch is formed by pole changer 1108 and 1110 1106.Source electrode and the drain electrode of the source electrode of switch 1108 and drain electrode and switch 1110 link together, and are connected to one end of base resistance 224 and one end of electric capacity 226.The grid of pole changer 1108 and 1110 is connected in earth terminal 140 and positive voltage source 142 separately.Switch 1108 is connected in positive voltage source 142.
As shown in the figure, circuit 1110 comprises inverter group 102, input power resistance 1102, main sampling section 104 and differential amplifier 244.Input power resistance 1102 is caused by an outer samples circuit.Except pole changer is to 1106 element and connection, inverter group 102, main sampling section 104, the element of auxiliary sampling part 1104 and differential amplifier 244 is substantially same as described above.
Select suitably big or small base resistance 224 and pole changer to 1106, to produce suitable amount distortion in auxiliary sampling part 1104.In circuit 1100, base resistance 224 is used for producing distortion, sampling capacitance 230 is coupled to input redirect switch on 218 simultaneously.Base resistance 224 in circuit 1100 and pole changer are determined by lower relation of plane 1106 size:
Auxiliary parasitic factor=(C130/C230) * main parasitic factor, wherein C130 and C230 are the capacitances of sampling capacitance 130 and 230, main parasitic factor and auxiliary parasitic factor are defined as: main parasitic factor=R1102* (CS120+CD122+CD120+CS122+CD128)+RON118* (CD120+CS122+CD128)+R124*CD128+R1102* (CS220+CD222+CD220+CS222+CS1108+CD1110+CD1108+CS1110+CD22 8), auxiliary parasitic factor=R1102* (CS220+CD222+CD220+CS222+CS1108+CD1110+CD1108+CS1110+CD22 8)+R1102* (CS120+CD122+CD120+CS122+CD128)+RON218* (CD220+CS222+CS1108+CD1110+CD1108+CS1110+CD228)+R224* (CS1108+CD1110+CD1108+CS1110+CD228), wherein R1102, RON118, RON218, with R224 be respectively the resistance of input power resistance 1102, the conducting resistance of switch 118 and 218, the resistance of base resistance 224, CD120, CS120, CD122, CS122, CD128, CD220, CS220, CD222, CS222, CD228, CD1108, CS1108, CD1110, CS1110 is respectively the electric capacity of switch 120 source electrodes and drain electrode, the electric capacity of switch 122 source electrodes and drain electrode, the electric capacity that switch 128 drains, the electric capacity of switch 220 source electrodes and drain electrode, the electric capacity of switch 222 source electrodes and drain electrode, the electric capacity that switch 228 drains, the source electrode of switch 1108 and the electric capacity of drain electrode and the source electrode of switch 1110 and the electric capacity of drain electrode.
The variation of Fig. 4 circuit 400, eliminate the distortion on sampling capacitance 130 and 380, as shown in the figure, be not the single sampling switch 132,382 only using respectively in main sampling section 104,354 and auxiliary sampling part 481,483, in Figure 12, each sampling section 104,1202,1204 and 354 comprises sampling switch 132,1206,1208 and 382 separately.Like this, the distortion on sampling capacitance 130 and 380 is eliminated.The same with sampling switch 132 and 382, the grid of sampling switch 1206 and 1208 is connected to the output of inverter 106, and the drain electrode of switch 1206 and 1208 is connected to one end of sampling capacitance 230 and 496, and the source electrode of switch 1206 and 1208 is connected to earth terminal 140.
By the output signal of sampling capacitance 130 and 380 and distortion respectively with the combining of sampling capacitance 496 and 230, the switch in circuit 1,200 1212 and 1210 is combined.The drain electrode of switch 1212 is connected to the drain electrode of sampling switch 1208 and one end of sampling capacitance 496, the source electrode of sampling switch 1212 is connected to the drain electrode of sampling switch 132, and the grid of one end, signal output part 350 and the switch 1212 of sampling capacitance 130 is connected to the output of inverter 116.The drain electrode of switch 1210 is connected to the drain electrode of sampling switch 1206 and one end of sampling capacitance 230, the source electrode of sampling switch 1210 is connected to the drain electrode of sampling switch 382, and the grid of one end, signal output part 352 and the switch 1210 of sampling capacitance 380 is connected to the output of inverter 116.Like this, at one time, ground connection pole changer 128,228,494 and 378 gives respectively sampling capacitance 130,230,496 and 380 by a reference, unit switch 1212 and 1210, by combining of the signal on sampling capacitance 130 and distortion and sampling capacitance 196, equally, combining the signal on sampling capacitance 380 and distortion and sampling capacitance 230.
Figure 13 represents the variation of a BJT of sampling and holding circuit 1300, comprises the characteristic that distortion of the present invention is eliminated.As shown in the figure, circuit 1300 comprises main sampling section 1301, auxiliary sampling part 1303 and summing amplifier 1305.Main sampling section 1301 and auxiliary sampling part 1303 receive the input signal from signal input part 1307, and sampling and inhibit signal are with responsive current source 1321,1323,1355 and 1357, and sampled signal outputs to summing amplifier 1305.The sampled signal of main sampling section 1301 and auxiliary sampling part 1303 is being done after addition, and summing amplifier 1305 drives signal output part 1309.
Main sampling section 1301 comprises electric bridge 1311, current source 1321,1323 and sampling capacitance 1325.The BJT1313,1315,1317 and 1319 that electric bridge 1311 is connected by four diodes forms.Therefore, main sampling section 1301 can be realized by diode or other equipment.BJT1313 and 1315 collector electrode are connected to current source 1321.BJT1313 emitter is connected on signal input part 1307 and the collector electrode of BJT1317.The emitter of BJT1315 is connected to collector electrode, one end of sampling capacitance 1325 and the positive input terminal of summing amplifier 1305 of BJT1319.BJT1317 and 1319 emitter are connected to the input of current source 1323.One end of sampling capacitance 1325 is connected to earth terminal 140.
Auxiliary sampling part 1303 comprises electric bridge 1329, current source 1355,1357 and sampling capacitance network 1347.The BJT1331,1333,1335,1337,1339,1341,1343 and 1345 that electric bridge 1329 is connected by eight diodes forms.BJT1331 and 1333 collector electrode are connected to the output of current source 1355.BJT1335 and 1337 collector electrode are connected to the emitter of BJT1331 and 1333.The emitter of BJT1335 is connected to the collector electrode of signal input part 1307 and BJT1339, and the emitter of BJT1337 is connected to the collector electrode of BJT1341 and the input of sampling capacitance network 1347.BJT1339 and 1341 emitter are connected to the collector electrode of BJT1343 and 1345, and BJT1343 and 1345 emitter are connected to the input of current source 1357.
Sampling capacitance network 1347 comprises three electric capacity 1349,1351 and 1353.One end of electric capacity 1349 is connected to the emitter of BJT1337, one end of the collector electrode of BJT1341 and electric capacity 1351.The other end of electric capacity 1349 is connected to one end and the earth terminal 140 of electric capacity 1353.The other end of electric capacity 1351 and 1353 is connected to the negative input end of summing amplifier 1305.
Each BJT1313,1315,1317,1319,1331,1333,1335,1337,1339,1341,1343 and 1345 is identical type and size, to guarantee identical conducting resistance and the ghost effect of electric capacity.Although electric bridge 1311 and 1329 comprises respectively four and eight BJT, the BJT of other numbers also can be implemented.Although current source 1321 and 1323 is different from current source 1355 and 1357, the electric current that current source 1321,1323,1355 and 1357 provides is identical.
In operation, the performance of circuit 1300 is as follows.Input signal is provided by signal input part 1307.Current source 1321,1323,1355 and 1357 is connected, and makes the voltage of electric capacity 1325 and capacitance network 1347 trace signals inputs 1307 simultaneously.In the time that current source 1321,1323,1355 and 1357 disconnects, reverse bias voltage place of current source 1321,1323,1355 and 1357, the voltage of electric capacity 1325 and capacitance network 1347 immobilizes.Because the BJT of electric bridge 1329 is twices of electric bridge 1311, electric bridge 1329 produces the distortion of twice, and the signal magnitude of passing through from signal input part 1307 is constant.Although the distortion that electric bridge 1329 produces is the twice of electric bridge 1311, only have the distortion of half and sampled signal to export by capacitance network 1347.Then these voltages are combined and are exported by signal output part 1309, and summing amplifier 1305 produces an output signal.
Figure 14 has shown the variation of the diode bridge of a sampling and holding circuit 1400, comprises the characteristic that distortion of the present invention is eliminated.As shown in the figure, circuit 1400 comprises main sampling section 1401 and auxiliary sampling part 1419, and they are all driven and controlled by maintenance input 134 by signal input part 136.Circuit 1400 also comprises summing amplifier 1450, drive signal output part 138, and summing amplifier 1450 is driven by main sampling section 1401 and auxiliary sampling part 1419.
Main sampling section 1401 comprises diode bridge 1404, identical current source 1402 and 1416 and sampling capacitance 1418.Diode bridge 1404 is formed by four diodes 1406,1408,1410 and 1412.The input of current source 1402 is connected to the anode of diode 1406 and 1408.The negative electrode of diode 1406 is connected to the anode of signal input part 136 and diode 1410.The negative electrode of diode 1408 is connected to the anode of diode 1412, the positive input terminal 1454 of one end of sampling capacitance 1418 and summing amplifier 1450.The negative electrode of diode 1410 and 1412 is connected to the input of current source 1416, and its output is connected to negative voltage power supply 710 places.Finally, the other end of sampling capacitance 1418 is connected on earth terminal 140.
Auxiliary sampling part 1419 comprises diode bridge 1422 and 1436, the current source 1420,1432,1434 and 1446 identical with current source 1402 and 1416, the sampling capacitance 1448 identical with sampling capacitance 1418.Diode bridge 1422 and 1436 comprises respectively four diodes 1424,1426,1428,1430 and diode 1438,1440,1442,1444.Diode bridge 1422 and 1436 is identical with diode bridge 1404.Diode bridge 1422 and 1436 is driven by current source 1420 and 1434 respectively, instead of current source 1402; Diode bridge 1422 and 1436 is driven by current source 1432 and 1446, instead of current source 1416; The output of diode bridge 1420 drives the input of diode bridge 1436, and the output of diode bridge 1436 is connected to the negative input end 1452 of ground connection sampling capacitance 1448 and summing amplifier 1450.
In operation, in the time that current source 1402 and 1416 is connected under the control of maintenance input 134, the voltage of the sampling capacitance 1418 trace signals inputs 136 of main sampling section 1401.In the time that current source 1402 and 1416 disconnects subsequently, the voltage on sampling capacitance 1418 remains on the voltage place of signal input part 136.Equally, in auxiliary sampling part 1419, in the time that current source 1420,1432,1434 and 1446 is connected, the voltage of sampling capacitance 1448 is followed the trail of the voltage of input signal 136; In the time that current source 1420,1432,1434 and 1436 disconnects, the voltage on sampling capacitance 1448 maintains.Because identical sampling capacitance 1418 and 1448 and the same number of diode bridge 1422 and 1436 of twice for auxiliary sampling part 1419, auxiliary sampling part 1419 produces the distortion of twice, this distortion produces in main sampling section 1401.It is identical that the distortion of this counteracting is reduced to the distortion receiving with main sampling section 1401.As shown in the figure, in the time adding the signal of main sampling section 1401 and distortion, distortion and signal are divided into half by the negative input end 1452 of summing amplifier 1450.In this mode, the distortion being produced by diode bridge is removed in summing amplifier 1450, and only the output signal of half has been eliminated.
Although two diode bridges 1422 and 1436 are identical with diode bridge 1404, each diode bridge has four diodes, and as shown in figure 14, the diode of any quantity, type, size also can be in the present invention.For example, if three diode bridges are identical with the diode electric bridge of main sampling section 1401, the negative input end 1452 of summing amplifier 1450 is divided the signal that is input to summing amplifier 1450 equally.Equally, although circuit 1400 represented by two identical capacitors 1418 and 1448, the diode of other quantity, type, size also can be in the present invention.Similarly, although current source 1402,1416,1420,1432,1434 and 1446 is all identical, dissimilar current source can be used for current source to 1402 and 1416,1420 and 1432,1434 and 1446.
In Figure 15 indication circuit 1500, the BJT of combination and diode change, and comprise the characteristic that distortion of the present invention is eliminated.As shown in the figure, circuit 1500 comprises main sampling section 1401 and auxiliary sampling part 1503 and summing amplifier 1524.Main sampling section 1401 is basic identical with the main sampling section 1401 described in Figure 14.But auxiliary sampling part 1503 is used BJT, diode and resistance, control the distortion that auxiliary sampling part 1503 produces.
Auxiliary sampling part 1503 comprises identical current source 1502 and 1523, electric bridge 1501 and the sampling capacitance 1448 identical with sampling capacitance 1418.Electric bridge 1501 comprises resistance 1504,1506,1512,1514,1516 and 1522, diode 1530,1532,1534 and 1536, and BJT1508,1510,1518 and 1520.The input of current source 1502 is connected to positive voltage source 142, and the output of current source 1502 is connected to the emitter of BJT1508 and 1510.The base stage of BJT1508 is connected to one end of resistance 1504 and 1512.The base stage of BJT1510 is connected to one end of resistance 1506 and the other end of resistance 1512.The other end of resistance 1504 is connected to the collector electrode of BJT1508 and the anode of diode 1530.The other end of resistance 1506 is connected to the collector electrode of BJT1510 and the anode of diode 1532.The negative electrode of diode 1530 is connected to the anode of signal input part 136 and diode 1534.The negative electrode of diode 1534 is connected to one end of resistance 1514 and the collector electrode of BJT1518.The negative electrode of diode 1532 is connected to ground connection sampling capacitance 1448, the negative input end 1526 of summing amplifier 1524 and the anode of diode 1536.The negative electrode of diode 1536 is connected to one end of resistance 1516 and the collector electrode of BJT1520.One end of the other end of resistance 1514 and resistance 1522 is connected to the base stage of BJT1518.The other end of resistance 1516 and 1522 is connected to the base stage of BJT1520.BJT1518 and 1520 emitter are connected to the input of current source 1523, and the output of current source 1523 is connected to negative voltage power supply 710.
In operation, electric bridge 1501 produces distortion, and this distortion is determined by the value of resistance 1504,1506,1512,1514,1516 and 1522.As shown in the label in Figure 15 " RF " and " RG ", resistance 1504,1506,1514 and 1516 has identical value, and resistance 1512 and 1522 has identical value.The distortion that the distortion that electric bridge 1501 produces produces with electric bridge 1401 becomes RG/ (RG+RF)+1 ratio.Therefore, the distortion that auxiliary sampling part 1503 produces and sampled signal amount are removed by summing amplifier 1524, and this summing amplifier 1524 is by the value control of RG and RF.
The circuit 1600 that Figure 16 presentation graphs 2 circuit 200 change, due to the right switched linear of input redirect switch and nonlinear resistance, circuit 1600 has been eliminated distortion.As shown in the figure, circuit 1600 comprises that the input redirect switch of main and auxiliary sampling part 1602 and 1604 is to 1622 and 1624, instead of input redirect switch is to 1602 and 1604.Input redirect switch has source resistance 1606 and drain resistance 1610 to 1622 switch 120.Input redirect switch has drain resistance 1608 and source resistance 1612 to 1622 switch 122.Input redirect switch has source resistance 1614 and drain resistance 1618 to 1624 switch 220.Input redirect switch has source resistance 1620 and drain resistance 1616 to 1624 switch 222.Except switch is replaced to switch in Fig. 2 to 118 and 218 to 1622 and 1624, the element of circuit 1600 and be connected substantially identical with Fig. 2 circuit 200.
In order to eliminate the nonlinear resistance of switch 120 and 122, the transistor layout of circuit 1600 is best, to such an extent as to resistance 1614,1616,1618 and 1620 is identical with resistance 1606,1608,1610 and 1612, the electricity of switch 220 and 222 is led or is big or small identical with switch 120 and 122.This relation can illustrate by following formula: (W120/L120)/(W220/L220)=(W122/L122)/(W222/L222)=R1614/R1606=R1618/R1610=R1616/R1608=R1620/R1612=G120/G22 0=G122/G222.
W120, W122, W220 and W222 are the channel widths of switch 120,122,220 and 222, L120, L122, L220 and L222 are the channel lengths of switch 120,122,220 and 222, R1606, R1610, R1608, R1612, R1614, R1618, R1616 and R1620 are the linearity end resistance of switch 120,122,220 and 222 source electrodes and drain electrode.If parasitic gate, source electrode and the capacitance of drain of switch 120,122,220 and 222 are left in the basket, this relation can illustrate by following formula: (W120/L120)/(W220/L220)=(W122/L122)/(W222/L222)=(R16l4+R1618)/(R1606+R1610)=(R1616+R1620)/(R1608+R1612)=G120/G220=G122/G222.
The linearity end resistance of the switch 220 and 222 identical with the linearity end resistance of switch 120 and 122 is provided, and in the time that distortion is combined together, the switch 220 and 222 that linear end resistance is identical produces corresponding distortion.
The present invention can describe and carry out according to it, and for the purpose of illustrating, object of the present invention is unrestricted, and right of the present invention is subject to the restriction of power interpellation book.
Claims (7)
1. eliminate the circuit of harmonic distortion in sampling and holding circuit for one kind, it is characterized in that: this circuit comprises an auxiliary sampling part, harmonic carcellation distortion, a part for the sampling harmonic distortion producing corresponding to above-mentioned main sampling section, wherein, above-mentioned auxiliary sampling part comprises at least one input switch device, in the time that input signal is used for the output of at least one input switch device, produce a part of harmonic carcellation distortion, to receive the input signal of input; A kind of combinational circuit, combines the harmonic distortion of sampling distortion and counteracting, to such an extent as to the sampling harmonic distortion of at least a portion is offset in the harmonic distortion of above-mentioned counteracting, and only eliminates the output signal of an above-mentioned part.
2. a kind of circuit of eliminating harmonic distortion in sampling and holding circuit according to claim 1, it is characterized in that: auxiliary sampling part produces the harmonic distortion of above-mentioned counteracting, to such an extent as to the harmonic distortion of offsetting is larger than the sampling harmonic distortion of above-mentioned at least a portion, then, reduce the harmonic distortion of offsetting, to such an extent as to the harmonic distortion of offsetting is substantially equal to the sampling harmonic distortion of at least a portion; Auxiliary sampling part further comprises a sampling capacitance circuit, the input signal that the output of above-mentioned at least one the input switch device of sampling provides; At least one above-mentioned input switch device comprises an input redirect switch, transistor bridge, a diode bridge that diode connects; The electric bridge of at least one above-mentioned input switch device comprises a transistor and a resistance; Above-mentioned sampling capacitance circuit comprises a Single Capacitance device; Above-mentioned sampling capacitance circuit comprises a capacitor network.
3. a kind of circuit of eliminating harmonic distortion in sampling and holding circuit according to claim 2, it is characterized in that: at least one above-mentioned input switch device produces harmonic carcellation distortion, to such an extent as to by the reduced size of at least one the input switch device in corresponding main sampling section, make the harmonic distortion of counteracting larger than the sampling harmonic distortion of above-mentioned at least a portion; Above-mentioned sampling capacitance circuit reduces the harmonic distortion of offsetting, and by the also little electric capacity of sampling capacitance circuit than in corresponding main sampling section, makes the harmonic distortion of offsetting be substantially equal to the sampling harmonic distortion of at least a portion.
4. a kind of circuit of eliminating harmonic distortion in sampling and holding circuit according to claim 2, is characterized in that: auxiliary sampling part, by total capacitance larger in main sampling section, produces the harmonic distortion of offsetting; Auxiliary sampling part further comprises a base resistance, and the output that is used for connecting at least one input switch device is to sampling capacitance circuit, and wherein the size of this base resistance has roughly the same size with the base resistance in corresponding main sampling section; Auxiliary sampling part also comprises a capacity load, is connected to the output of at least one input switch device, and wherein due to the parasitic capacitance in auxiliary sampling part, this capacitive load causes distortion; Due to the parasitic capacitance in main sampling section, auxiliary sampling part has been eliminated a part of distortion substantially; Auxiliary sampling part also comprises multiple cascade sampled points, and an extra switching device is connected to the output of above-mentioned at least one input switch device, produces distortion; Due to input power resistance, substantially eliminate the distortion of at least a portion; Due to the end resistance of at least one input switch device in above-mentioned main sampling section, the end resistance of above-mentioned at least one input switch device produces distortion, the distortion of having offset at least a portion.
5. a kind of circuit of eliminating harmonic distortion in sampling and holding circuit according to claim 1, is characterized in that: said method comprises the signal that receives at least one input switch device input; On at least one input switch device of auxiliary sampling part, produce and offset distortion, a part of sampling distortion producing corresponding to main sampling section; Control inputs signal application is in the output of at least one input switch device; The harmonic distortion of sampling distortion and counteracting is combined, to such an extent as to the sampling harmonic distortion of at least a portion is offset in the harmonic distortion of above-mentioned counteracting, and only eliminate the output signal of an above-mentioned part.
6. a kind of circuit of eliminating harmonic distortion in sampling and holding circuit according to claim 2, it is characterized in that: because auxiliary sampling part has larger total capacitance than main sampling section, the harmonic distortion of counteracting is larger than the sampling harmonic distortion of above-mentioned at least a portion; Because sampling capacitance circuit has than the less electric capacity of corresponding main sampling section up-sampling electric capacity, reduce the harmonic distortion of offsetting, to such an extent as to the harmonic distortion of offsetting is substantially equal to the sampling harmonic distortion of at least a portion.
7. a kind of circuit of eliminating harmonic distortion in sampling and holding circuit according to claim 2, it is characterized in that: the method connects the output of capacity load at least one input switch device, wherein, due to the parasitic capacitance in auxiliary sampling part, capacity load produces distortion; Due to the parasitic capacitance in main sampling section, auxiliary sampling part has been eliminated the distortion of at least a portion substantially.
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| CN110688684A (en) * | 2019-08-08 | 2020-01-14 | 国网宁夏电力有限公司电力科学研究院 | A nonlinear load simulation device |
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| CN110688684A (en) * | 2019-08-08 | 2020-01-14 | 国网宁夏电力有限公司电力科学研究院 | A nonlinear load simulation device |
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Address after: 215000 Building 1, No. 150, Jici Road, science and Technology City, high tech Zone, Suzhou City, Jiangsu Province Patentee after: Suzhou Baker Microelectronics Co.,Ltd. Address before: Room 1404, building 3, No. 209, Zhuyuan Road, high tech Zone, Suzhou, Jiangsu 215011 Patentee before: SUZHOU BAKER MICROELECTRONICS Co.,Ltd. |
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| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20140903 |