CN203801035U

CN203801035U - Decoder with BNC output

Info

Publication number: CN203801035U
Application number: CN201320815604.2U
Authority: CN
Inventors: 胡金军
Original assignee: Hangzhou Hikvision Digital Technology Co Ltd
Current assignee: Hangzhou Hikvision Digital Technology Co Ltd
Priority date: 2013-12-10
Filing date: 2013-12-10
Publication date: 2014-08-27
Anticipated expiration: 2023-12-10

Abstract

The utility model provides a decoder with BNC output, comprising: a decoder main board and a BNC interface board connected to the output end of the decoder main board; wherein, the decoder main board includes a network subsystem sequentially coupled through a PCIE interface , Calpella platform subsystem and decoding output subsystem. The utility model decodes the front-end code stream through a central processing unit (CPU), converts it into BNC analog data through a BNC output logic unit and a digital-to-analog converter, and finally outputs and displays it from a BNC interface board.

Description

Decoder with BNC output

Technical Field

The utility model relates to a video monitoring technical field, in particular to decoder with BNC output.

Background

The universal decoder integrates a decoder and a separator, and is a video and audio decoder capable of performing network decoding on coding equipment of various security monitoring manufacturers.

The decoding equipment of the current security monitoring system is roughly divided into two types: an embedded decoder and a soft decoding server.

The main function of the embedded decoder is to decode the video transmitted from the network and put it on the wall in the network monitoring project. The decoding circuit is mainly decoded by ARM main control chips, DSP (microprocessor) and other special decoding chips and output through a BNC (Bayonet Nut Connector) interface. In particular, the BNC interface is a connector for coaxial cables

The soft decoding server mainly comprises a PC mainboard and a plurality of video cards. And the PC mainboard runs a windows operating system. The soft decoding server usually only supports mainstream interfaces such as VGA, DVI and the like, but not supports BNC interface.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a decoder with BNC output to solve the problem that the soft server of decoding in the equipment of current security protection monitored control system does not support the BNC interface.

In order to solve the above technical problem, the utility model provides a decoder with BNC output, include: the decoder comprises a decoder mainboard and a BNC interface board connected with the output end of the decoder mainboard; wherein,

the decoder mainboard comprises a network subsystem, a Calpella platform subsystem and a decoding output subsystem which are sequentially coupled through a PCIE interface.

Preferably, in the decoder with BNC output, the network subsystem includes a front-end code stream and a network card connected to the front-end code stream through RJ45 interface.

Preferably, in the decoder with BNC output, the callella platform subsystem includes a central processing unit, a memory unit providing a memory for the central processing unit, and a south bridge connected to the central processing unit through an FDI interface and a DMI interface.

Preferably, in the decoder with BNC output, the decoded output subsystem includes a BNC output logic unit and a digital-to-analog converter connected to the BNC output logic unit.

Preferably, in the decoder with BNC output, the decoded output subsystem includes two BNC output logic unit inputs, and each BNC output logic unit corresponds to an eight-way digital-to-analog converter output.

Preferably, the decoder with BNC output further comprises a power supply, a fan and an LED indicator panel respectively connected to the decoder main board.

The utility model provides a decoder with BNC output has following beneficial effect: the utility model discloses after decoding the front end code stream through Central Processing Unit (CPU), export logical unit and digital analog converter through BNC and convert BNC analog data into, export the demonstration from BNC interface board at last.

Drawings

Fig. 1 is a schematic diagram of a decoder with BNC output of the present invention;

FIG. 2 is a schematic diagram of a decoder motherboard with a decoder having a BNC output according to the present invention;

fig. 3 is a BNC hardware logic diagram of the decoder with BNC output of the present invention.

Detailed Description

The decoder with BNC output according to the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more fully apparent from the following description and appended claims. It should be noted that the drawings are in simplified form and are not to precise scale, and are provided for convenience and clarity in order to facilitate the description of the embodiments of the present invention.

As shown in fig. 1, the utility model provides a decoder with BNC output has realized BNC and has decoded the demonstration based on windows XP Embedded operating system, specifically includes: the decoder comprises a decoder mainboard 11 and a BNC interface board 12 connected with the output end of the decoder mainboard 11, and further comprises a power supply 13, a fan 14 and an LED indicator light panel 15 which are respectively connected with the decoder mainboard 11.

The architecture of the decoder motherboard is further illustrated as shown in fig. 2. The decoder motherboard includes a network subsystem 21, a callella platform subsystem 22 and a decoding output subsystem 23 coupled in sequence. The network subsystem 21, the callella platform subsystem 22 and the decoding output subsystem 23 are connected through a PCIE interface.

Specifically, the network subsystem 21 is used as a medium for data transmission, and calls an interface provided by a driver to transfer a network code stream to a system to implement decoding. The network subsystem 21 specifically includes a front-end code stream 211 and a network card 212 connected to the front-end code stream 211 through an RJ45 interface 222.

Preferably, the network card 212 is a network card with a model number of RTL 8111D.

Further, the callella platform subsystem 22 is a core part of the whole system, and is used for implementing decoding. The callella platform subsystem 22 specifically includes a Central Processing Unit (CPU) 221, a memory unit 222 for providing a memory for the Central Processing Unit (CPU) 221, and a south bridge (PCH) 225 connected to the Central Processing Unit (CPU) 221 through an FDI interface 223 and a DMI interface 224.

Preferably, the Central Processing Unit (CPU) 221 is an intra-area central processing unit (arandale CPU), and is mainly responsible for starting and running an operating system and application programs, so as to ensure system scheduling of the whole device.

Preferably, the memory unit 222 adopts DDR3 to provide memory for system and application program operation.

Specifically, the south bridge (PCH) 225 mainly implements platform control and provides some low-speed peripheral interfaces including USB, SATA, SPI, SMBus, HAD, PCIE, LPC, and the like.

Specifically, the central processing unit 221 and the south bridge 225 are configured to transmit through an FDI interface 223 and a DMI interface 224, where the FDI interface 223 is responsible for transmitting data, and the DMI interface 224 is responsible for transmitting video signals.

Further, the decoding output subsystem 23 is configured to convert the decoded code stream into a BNC output, and specifically includes a BNC output logic unit 231 and a digital-to-analog converter 232 connected to the BNC output logic unit 231.

Preferably, the BNC output logic unit 231 is a CX25821 chip.

Preferably, the digital-to-analog converter 232 is a digital-to-analog converter of model SAA 7121H.

Specifically, the code stream on the PCIE bus is converted into bt.656 by CX25821 and then into BNC output via SAA 7121.

Based on this, the decoder motherboard adopts an X86 architecture callella platform, decodes the incoming front-end code stream of the network by using the CPU, and then sends the decoded data to the BNC output logic unit via the PCH to be converted into BNC output by the SAA 7121.

As further shown in fig. 3, the decode output subsystem includes two BNC output logic cell inputs, each BNC output logic cell corresponding to an eight-way digital-to-analog converter output. After the CPU decodes the code stream, the decoded data is sent to the south bridge, and the code stream is converted into a related image system through the peripheral chip and is output through the provided PCIE interface. Specifically, one BNC output logic unit supports 8-way BNC output, and a plurality of BNC output logic units are adopted to support a plurality of BNC outputs.

The above description is only for the preferred embodiment of the present invention and is not intended to limit the scope of the present invention, and any modification and modification made by those skilled in the art according to the above disclosure are all within the scope of the claims.

Claims

1. A decoder having a BNC output, comprising: the decoder comprises a decoder mainboard and a BNC interface board connected with the output end of the decoder mainboard; wherein,

2. The decoder with BNC output of claim 1, wherein said network subsystem comprises a front end code stream and a network card connected to said front end code stream through an RJ45 interface.

3. The decoder with BNC output of claim 1, wherein said callella platform subsystem comprises a cpu, a memory unit providing memory for said cpu, and a south bridge connected to said cpu through an FDI interface and a DMI interface.

4. The decoder with a BNC output of claim 1, wherein said decoded output subsystem comprises a BNC output logic element and a digital-to-analog converter connected to said BNC output logic element.

5. The decoder with BNC output according to claim 4, wherein said decoded output subsystem comprises two BNC output logic cell inputs, each BNC output logic cell corresponding to an eight-way digital-to-analog converter output.

6. The decoder with a BNC output according to any of claims 1-5, further comprising a power supply, a fan, and an LED indicator light panel respectively connected to said decoder motherboard.