CN203800900U - Low-cost on-chip oscillator - Google Patents
Low-cost on-chip oscillator Download PDFInfo
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- CN203800900U CN203800900U CN201420147586.XU CN201420147586U CN203800900U CN 203800900 U CN203800900 U CN 203800900U CN 201420147586 U CN201420147586 U CN 201420147586U CN 203800900 U CN203800900 U CN 203800900U
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- bias current
- reference voltage
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- comparator
- oscillator
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- 239000003990 capacitor Substances 0.000 claims description 9
- 230000005540 biological transmission Effects 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 238000012886 linear function Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
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Abstract
The utility model provides a low-cost on-chip oscillator which can greatly reduce the area and the manufacture and design cost of a chip. The on-chip oscillator comprises a comparator, a bias current generator, a reference voltage generation circuit and a charging path, wherein bias current provided by the bias current generator is connected to the reference voltage generation circuit and the charging path, a bias current source k*IB is formed in the reference voltage generation circuit, and a bias current source IB is formed in the charging path; and the bias current source k*IB in the reference voltage generation circuit is connected in series with a resistor R0 and grounded, and a voltage dividing node is placed between the bias current source k*IB and the resistor R0. The low-cost on-chip oscillator not only has advantages of traditional oscillators, but also greatly reduces the area and the manufacture cost of the chip; and to engineers, the difficulties in period calculation and circuit design are reduced, and the design and development time of the chip is shortened.
Description
Technical field
The utility model relates to a kind of upper oscillator.
Background technology
Oscillator is after enable signal arrives, and inner oneself circulation vibrated, and produces the clock signal of output certain frequency, offers digital system or other digital modules, and it is worked in order.Oscillator can be integrated on same silicon chip with other circuit modules, forms oscillator on sheet.
Schematic diagram and oscillogram referring to traditional scheme shown in Fig. 1,2.Wherein: resistance R 1 and R2 series connection dividing potential drop, for comparator provides reference voltage; Resistance R 0 and capacitor C 0 form RC charging path; Switch A and switch B are operated in phase place on the contrary; Bias current generator provides its work required bias current for comparator; Frequency-halving circuit pulse signals frequency division, obtains the clock signal of duty ratio 50%.
1> clock cycle Tcycle=Tch+Tdl; Tch wherein: capacitor charging time; Tdl: feedback delay discharge time
Work as Tdl<<Tch, Tcycle ≈ Tch;-----------------formula (1)
Tch=R0*C0*ln[(R1+R2)/R1];-----------------formula (2)
The pluses and minuses of 2> traditional scheme:
Advantage: Tch is not subject to the impact of mains voltage variations, but is still subject to the impact (can compensate) of temperature factor;
Tdl is subject to the impact of supply voltage and variations in temperature, but relatively very little;
When Tdl is during much smaller than Tch, Tcycle is subject to the impact of mains voltage variations very little.
Shortcoming: can find out from traditional scheme schematic diagram and expression formula (2):
Typical case: (R1+R2)/R1=26/8=3.25 → Tch=1.18*R0*C0------------formula (3)
Limiting case: (R1+R2)/R1=9 → Tch=2.2*R0*C0------------formula (4)
(1) parameter factors ln[(R1+R2)/R1] efficiency is lower, be ln[(R1+R2)/R1] less, this just makes the value of resistance R 0 or capacitor C 0 larger, and large R0 or C0 just need larger chip area, cause chip area to increase, thereby increased the cost of chip.In addition,, if R0 and C0 are definite, under limiting case, the maximum clock cycle is also limited, only has 2.2*R0*C0.
(2) resistance R 1 and R2 series connection dividing potential drop, for comparator provides reference voltage.In order to reduce the current power dissipation of oscillator, generally need to adopt R1 and the R2 of larger resistance, cause further taking more chip area, chip cost rises.
(3) factor ln[(R1+R2)/R1] be nonlinear function, if want, by it, adjust linearly cycle of oscillation, can give and calculate and design and bring certain difficulty, also extended designing and developing the time of chip.
Utility model content
The problems referred to above that exist in order to solve traditional scheme, the utility model proposes oscillator circuit structure on a kind of new sheet, can save to a great extent chip area, reduce manufacture and the design cost of chip.
Basic scheme of the present utility model is as follows:
An oscillator on low-cost sheet, comprises comparator, bias current generator, generating circuit from reference voltage and charging path, and bias current generator provides its work required bias current for comparator; The switch B ground connection of connecting with capacitor C 0 on charging path; The anti-phase input of comparator is connected to the dividing potential drop node of generating circuit from reference voltage, and the normal phase input end of comparator has two-way wiring, and a road is through described capacitor C 0 ground connection, separately leads up to switch A ground connection; Switch A and switch B are set to opposite phase, controlled by the output of comparator; Its special character is:
The bias current that described bias current generator provides also accesses respectively generating circuit from reference voltage and charging path, forms bias current sources K*IB in generating circuit from reference voltage, in charging path, forms bias current sources IB; The bias current sources K*IB ground connection of connecting with resistance R 0 in described generating circuit from reference voltage, dividing potential drop node is between bias current sources K*IB and resistance R 0.
Based on above-mentioned basic scheme, the utility model is also done following optimization and is limited:
Above-mentioned bias current sources K*IB and bias current sources IB are realized by two PMOS pipes that are biased respectively, and the bias voltage that described bias current generator provides is connected to respectively the grid of two PMOS pipes.
Above-mentioned switch B is managed by PMOS or transmission gate is realized.
Above-mentioned switch A is realized by NMOS pipe.
The utility model not only possesses the advantage of traditional scheme, can save to a great extent chip area again simultaneously, has reduced the manufacturing cost of chip; For engineering staff, also reduced the difficulty of computation of Period and circuit design, thereby shortened designing and developing the time of chip.
Accompanying drawing explanation
Fig. 1 is traditional scheme schematic diagram.
Fig. 2 is traditional scheme oscillogram.
Fig. 3 is the utility model scheme schematic diagram.
Fig. 4 is the utility model scheme oscillogram.
Fig. 5 is the utility model scheme application example circuit diagram.
Fig. 6 is the electronic circuit figure of the utility model scheme application example.
Embodiment
Schematic diagram and oscillogram referring to the utility model scheme shown in Fig. 3,4:
Wherein: bias current K*IB flows through resistance R 0 provides reference voltage for comparator; Bias current IB and capacitor C 0 form charging path; The control end of switch A is connected to the output of comparator, and the control end of switch B is connected to the output of comparator through inverter, so that switch A is operated in contrary phase place with switch B.Bias current generator not only provides its work required bias current for comparator, but also bias current K*IB and IB are provided; Frequency-halving circuit pulse signals frequency division, obtains the clock signal of duty ratio 50%.
1> clock cycle Tcycle=Tch+Tdl; Tch wherein: capacitor charging time; Tdl: feedback delay discharge time
Work as Tdl<<Tch, Tcycle ≈ Tch;--------------formula (5)
Tch*IB=R0*K*IB*C0 → Tch=K*R0*C0 (IB is cancelled);--------formula (6)
The advantage of 2> the utility model scheme:
(1) there is the same of traditional scheme:
Tch is not subject to the impact of mains voltage variations, but is still subject to the impact (can compensate) of temperature factor;
Tdl is subject to the impact of supply voltage and variations in temperature, but relatively very little;
When Tdl is during much smaller than Tch, Tcycle is subject to the impact of mains voltage variations very little.
(2) factor K specific factor ln[(R1+R2)/R1] more efficient.In order further to save area, the optional K that goes is larger, and R0 or C0 will be smaller, more can save chip area, reduces chip cost.
In addition, if R0 and C0 determine, under limiting case, the resulting maximum clock cycle of this programme can larger (value of getting K be larger).
(3) compare traditional scheme, in this scheme, resistance R 1 and R2 are removed, and the substitute is two bias current sources IB and K*IB.And bias current is generally to be produced by PMOS pipe, than resistance R 1 and R2, PMOS pipe small-sized, this has saved chip area to a great extent, has reduced the cost of chip;
When actual realization, if the resistance capacitance square value of choosing hour, the utility model scheme is reducing chip area, and cost-saving upper advantage will be more obvious.
(4) than factor ln[(R1+R2)/R1], factor K is linear function, can adjust flexibly and easily like this cycle of oscillator.For engineering staff, reduced the difficulty of computation of Period and circuit design, thereby shortened designing and developing the time of chip.
Below lift again example imbody marked improvement of the present utility model.
Referring to the specific implementation circuit shown in Fig. 5 and Fig. 6, wherein the electronic circuit figure shown in Fig. 6 is a kind of typical implementation, can certainly be realized by the physical circuit of other structures.
With reference to 3, two current source K*IB of figure and IB, by two PMOS pipes that are biased, realized respectively; Switch A is realized by NMOS pipe, and switch B is realized by PMOS pipe (or transmission gate).
Under certain technique, selector kind is as follows: resistance square value is 1KOhm/ square, and electric capacity square value is 2.12fF/um^2.
For TCH=1.2*Ru*Cu(performance period for example Ru=160KOhm, Cu=6pF) oscillator:
Being designed to of traditional scheme: choose (R1+R2)/R1=26/8, R0=Ru, C0=Cu;
Being designed to of this example: K=6, R0=Ru, C0=Cu/5;
By actual cloth domain measurement size, this example can be saved area approximately 30% than traditional scheme.If the resistance capacitance square value of choosing more hour, on chip area, advantage can be more obvious saving for this programme.
Claims (4)
1. an oscillator on low-cost sheet, comprises comparator, bias current generator, generating circuit from reference voltage and charging path, and bias current generator provides its work required bias current for comparator; The switch B ground connection of connecting with capacitor C 0 on charging path; The anti-phase input of comparator is connected to the dividing potential drop node of generating circuit from reference voltage, and the normal phase input end of comparator has two-way wiring, and a road is through described capacitor C 0 ground connection, separately leads up to switch A ground connection; Switch A and switch B are set to opposite phase, controlled by the output of comparator;
It is characterized in that:
The bias current that described bias current generator provides also accesses respectively generating circuit from reference voltage and charging path, forms bias current sources K*IB in generating circuit from reference voltage, in charging path, forms bias current sources IB; The bias current sources K*IB ground connection of connecting with resistance R 0 in described generating circuit from reference voltage, dividing potential drop node is between bias current sources K*IB and resistance R 0.
2. oscillator on low-cost sheet according to claim 1, it is characterized in that: described bias current sources K*IB and bias current sources IB are realized by two PMOS pipes that are biased respectively, and the bias voltage that described bias current generator provides is connected to respectively the grid of two PMOS pipes.
3. oscillator on low-cost sheet according to claim 1 and 2, is characterized in that: described switch B is managed by PMOS or transmission gate is realized.
4. oscillator on low-cost sheet according to claim 3, is characterized in that: described switch A is realized by NMOS pipe.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420147586.XU CN203800900U (en) | 2014-03-28 | 2014-03-28 | Low-cost on-chip oscillator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420147586.XU CN203800900U (en) | 2014-03-28 | 2014-03-28 | Low-cost on-chip oscillator |
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| Publication Number | Publication Date |
|---|---|
| CN203800900U true CN203800900U (en) | 2014-08-27 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420147586.XU Withdrawn - After Issue CN203800900U (en) | 2014-03-28 | 2014-03-28 | Low-cost on-chip oscillator |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103916099A (en) * | 2014-03-28 | 2014-07-09 | 西安华芯半导体有限公司 | Low-cost on-chip oscillator |
-
2014
- 2014-03-28 CN CN201420147586.XU patent/CN203800900U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103916099A (en) * | 2014-03-28 | 2014-07-09 | 西安华芯半导体有限公司 | Low-cost on-chip oscillator |
| CN103916099B (en) * | 2014-03-28 | 2016-08-17 | 西安紫光国芯半导体有限公司 | Agitator in a kind of low cost sheet |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20140827 Effective date of abandoning: 20160817 |
|
| C25 | Abandonment of patent right or utility model to avoid double patenting |