CN203707088U - Test structure used for monitoring overlay accuracy of integrated circuit - Google Patents
Test structure used for monitoring overlay accuracy of integrated circuit Download PDFInfo
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- CN203707088U CN203707088U CN201420042194.7U CN201420042194U CN203707088U CN 203707088 U CN203707088 U CN 203707088U CN 201420042194 U CN201420042194 U CN 201420042194U CN 203707088 U CN203707088 U CN 203707088U
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Abstract
The utility model provides a test structure used for monitoring the overlay accuracy of an integrated circuit, which at least comprises a first metal layer, an insulating layer, a plurality of parallel first unit resistors, a plurality of parallel second unit resistors and a second metal layer, wherein the first metal layer is provided with a first resistor and a second resistor; the insulating layer is located on the first metal layer and provided with a plurality of metal through holes; the plurality of first unit resistors and the plurality of second unit resistors are located between the first resistor and the second resistor, the head ends of the plurality of first unit resistors and the head ends of the plurality of second unit resistors are connected to the first resistor and the second resistor respectively; the second metal layer is located on the insulating layer and provided with a strip-shaped resistor which is horizontally projected among the unit resistors; the intervals between the unit resistors and a projection of the strip-shaped resistor on the first metal layer increase or decrease progressively; one ends of the two resistors and one end of the strip-shaped resistor are connected to a bonding pad; the tail end of the unit resistor is contacted with the metal through hole, and projections of the first unit resistors and the second unit resistors are axially symmetric or centrally symmetric relative to the strip-shaped resistor on the first metal layer; and the minimum distance between the first unit resistor and the second unit resistor is less than or equal to the width of the strip-shaped resistor. The test structure can effectively monitor the overlay accuracy in the manufacturing process of the circuit and improves the product yield.
Description
Technical field
The utility model relates to ic manufacturing technology field, particularly relates to a kind of test structure for monitoring integrated circuit alignment precision.
Background technology
Integrated circuit in semiconductor fabrication develops into from the discrete device of common simple function the integrated circuit of integrating high-density multifunction; By initial IC to large scale integrated circuit and very lagre scale integrated circuit (VLSIC) subsequently, until the ultra large scale integrated circuit of today, the area of device further dwindles, the integrated level of semiconductor chip improves constantly, and makes the three-dimensional structure of various components and parts in production be broken down into the litho pattern of tens layers two dimension.In order to reach good device performance, each litho pattern not only will have characteristic line breadth size accurately, also will ensure its accurate aligning alignment precision between layers.
In semiconductor fabrication, the monitoring of existing alignment precision can only be for the production of the test of sample on line and is obtained some wafers and permit the data of Acceptance Tests (WAT).And when in wafer manufacture process in reality, it has occurred when abnormal production line is upper, be difficult to effectively monitor skew in a small amount, and be difficult to monitor how many alignment side-play amounts.Therefore be only difficult to illustrate that by collecting the test data of some WAT wafer has occurred in each photoetching process how many skews and side-play amount are separately how many.Therefore be necessary to propose a kind of new test structure for monitoring integrated circuit alignment precision.
Utility model content
The shortcoming of prior art in view of the above, the purpose of this utility model is to provide a kind of test structure for monitoring integrated circuit alignment precision, can not accurately reflect less offset amount and the problem that is offset number between each lithography layer for solving prior art by collecting WAT test data.
For achieving the above object and other relevant objects, the utility model provides a kind of test structure for monitoring integrated circuit alignment precision, and described test structure at least comprises:
Be provided with the first metal layer of first, second resistance and be positioned at described the first metal layer top and there is the insulating barrier of some metal throuth holes;
Between described first, second resistance and head end be connected in accordingly respectively first, second cell resistance some parallel to each other of described first, second resistance;
Be positioned at the second metal level of described insulating barrier top;
Described the second metal level has the bar resistor of floor projection between described first, second cell resistance;
Described some first, second cell resistance parallel to each other and the described bar resistor distance between projection on described the first metal layer is respectively increasing or decreasing;
Described first, second resistance and bar resistor one end connect respectively first, second, third pad for testing accordingly;
Described some metal throuth holes respectively projection also contact with it in described first, second cell resistance end;
Described first, second cell resistance about described bar resistor the projection on described the first metal layer axisymmetricly or Central Symmetry distribute;
Minimum range between described first module resistance and second unit resistance is less than or equal to the width of described bar resistor.
As a kind of preferred version of the test structure for monitoring integrated circuit alignment precision of the present utility model, the resistance of described first, second resistance equates.
As a kind of preferred version of the test structure for monitoring integrated circuit alignment precision of the present utility model, the resistance of described first, second cell resistance is at least 100 times of described first, second resistance.
As a kind of preferred version of the test structure for monitoring integrated circuit alignment precision of the present utility model, described first, second cell resistance and the described bar resistor distance between projection on the first metal layer becomes arithmetic progression successively.
As a kind of preferred version of the test structure for monitoring integrated circuit alignment precision of the present utility model, described first, second cell resistance by its put in order since second first or its resistance of second unit resistance become successively Geometric Sequence and first first or the resistance of second unit resistance respectively accordingly with described second first or second unit resistance identical.
As a kind of preferred version of the test structure for monitoring integrated circuit alignment precision of the present utility model, described its internal structure of first, second cell resistance is square wave-shaped configuration.
As a kind of preferred version of the test structure for monitoring integrated circuit alignment precision of the present utility model, the live width of described first, second cell resistance is 10 nanometer to 500 nanometers.
As a kind of preferred version of the test structure for monitoring integrated circuit alignment precision of the present utility model, described first, second resistance respectively about described bar resistor axisymmetricly or Central Symmetry distribute.
As a kind of preferred version of the test structure for monitoring integrated circuit alignment precision of the present utility model, described first, second resistance is parallel with described bar resistor respectively.
As a kind of preferred version of the test structure for monitoring integrated circuit alignment precision of the present utility model, described first, second resistance is in vertical distribution with described first, second cell resistance respectively accordingly.
As mentioned above, test structure for monitoring integrated circuit alignment precision of the present utility model, be positioned at described first by setting, between the second resistance and head end be connected in accordingly respectively described first, some parallel to each other first of the second resistance, second unit resistance, make described some parallel to each other first, second unit resistance about floor projection in described the second metal level in described first, bar resistor between second unit resistance axisymmetricly or Central Symmetry distribute, arrange described some parallel to each other first simultaneously, second unit resistance and the described bar resistor distance between projection on described the first metal layer is respectively increasing or decreasing, there is following beneficial effect: make the second metal level in the time there is alignment skew, any one first module resistance or second unit resistance in any one group in the first module resistance that described bar resistor is parallel to each other with two groups or second unit resistance are connected by the metal throuth hole in insulating barrier, by measuring the first pad and the 3rd pad, electric current and voltage between the second pad and the 3rd pad, calculate the resistance between above-mentioned two pads.Described first, second cell resistance and the described bar resistor distance between projection on described the first metal layer has certain " resistance-distance " relation with the each cell resistance resistance setting in advance, resistance in the resistance calculating and described " resistance-distance " relation is compared, can judge described the second metal level and occurred the direction of how many side-play amounts and skew.Can effectively monitor the alignment precision between each lithography layer, improve and produce the yield that sheet is produced.
Brief description of the drawings
Fig. 1 is the schematic top plan view of a kind of test structure for monitoring integrated circuit alignment precision of the present utility model.
Fig. 2, Fig. 3 are two kinds of different generalized sections of Fig. 1.
Fig. 4, Fig. 5, Fig. 6 are another three kinds of schematic top plan view for the test structure of monitoring integrated circuit alignment precision of the present utility model.
Fig. 7 is the internal structure schematic diagram of first, second cell resistance of the present utility model.
Element numbers explanation
10a the first resistance
10b the second resistance
11a first module resistance
11b second unit resistance
12a the first pad
12b the second pad
12c the 3rd pad
13a, 13b metal throuth hole
14 bar resistors
A the first metal layer
B insulating barrier
C the second metal level
Embodiment
By specific instantiation, execution mode of the present utility model is described below, those skilled in the art can understand other advantages of the present utility model and effect easily by the disclosed content of this specification.The utility model can also be implemented or be applied by other different embodiment, and the every details in this specification also can be based on different viewpoints and application, carries out various modifications or change not deviating under spirit of the present utility model.
Refer to Fig. 1～Fig. 7.It should be noted that, the diagram providing in the present embodiment only illustrates basic conception of the present utility model in a schematic way, satisfy and only show with assembly relevant in the utility model in graphic but not component count, shape and size drafting while implementing according to reality, when its actual enforcement, kenel, quantity and the ratio of each assembly can be a kind of random change, and its assembly layout kenel also may be more complicated.
Embodiment mono-
As shown in Figure 1, expression be the schematic top plan view of a kind of test structure for monitoring integrated circuit alignment precision of the present utility model, what Fig. 2 and Fig. 3 represented respectively is the generalized section of Fig. 1 along AA' and BB' different directions.Wherein the first metal layer A in Fig. 2 is provided with the first resistance 10a and the second resistance 10b as shown in Figure 1, described the first resistance 10a is identical with the internal structure of the second resistance 10b, its internal structure is square-wave form as shown in Figure 6, and the first resistance of this square-wave form or the live width of the second resistance are 10 nanometer to 500 nanometers.The present embodiment is as a kind of preferred version, and the resistance of described first, second resistance equates.Can make the resistance of this first, second resistance is 10 ohm to 50 ohm simultaneously.
Between described the first resistance 10a and the second resistance 10b, be provided with some first module resistance 11a and second unit resistance 11b; Some high value resistors that described first module resistance 11a is distribution parallel to each other, and the head end of the high value resistor of these some parallel distributions is connected to described the first resistance 10a; Equally, described second unit resistance 11b is also some high value resistors of distribution parallel to each other, and the head end of the high value resistor of these some distributions parallel to each other is connected to described the second resistance 10b; As a kind of preferred version of the present embodiment, relatively described the first resistance of described first, second cell resistance, the second resistance are high value resistor, and its resistance is at least 100 times of described first, second resistance.
As shown in Figure 2, that be positioned at described the first metal layer A top is insulating barrier B, described insulating barrier B is provided with some metal throuth hole 13a or 13b, as shown in Figure 1, described some metal throuth hole 13a or the projection accordingly of 13b difference are in the terminal position of described first module resistance 11a and second unit resistance 11b, in Fig. 2, the some metal throuth hole 13a in shown insulating barrier B contact with the end of the first module resistance 11a in described the first metal layer; Equally, the some metal throuth hole 13b in described insulating barrier B contact with the end of the second unit resistance 11b in described the second metal level.
That be positioned at described insulating barrier B top is the second metal level C as shown in Figure 3, and described the second metal level C has a bar resistor 14.In the present embodiment, because the resistance value of described the first resistance and described the second resistance is identical, therefore, the present embodiment also can make the resistance of described bar resistor 14 identical with the resistance of the second resistance with described the first resistance.The width of bar resistor 14 described in the present embodiment can value be 20 microns to 50 microns.As shown in Figure 1, the floor projection of described bar resistor 14 on described the first metal layer A is between described some first module resistance 11a and some second unit resistance 11b.
As shown in Figure 1, the distance d between some first module resistance 11a parallel to each other and some second unit resistance 11b parallel to each other and the projection of described bar resistor on described the first metal layer described in the present embodiment is respectively the rule variation of increasing or decreasing.As shown in Figure 1, described first module resistance 11a parallel to each other and described second unit resistance 11b parallel to each other are about the distribution that is centrosymmetric of described bar resistor 14.
The position of described the first resistance 10a and described second resistance 10b projection on described the first metal layer about described bar resistor can be arbitrarily.The position that can make described the first resistance 10a and described second resistance 10b projection on described the first metal layer about described bar resistor axisymmetricly or Central Symmetry distribute.As shown in Figure 1, the position of described the first resistance 10a and described second resistance 10b projection on described the first metal layer about described bar resistor is that axial symmetry distributes, wherein, what Fig. 1 represented as a kind of optimal way of the present embodiment is the parallel distribution mode during axial symmetry distributes, that is described the first resistance 10a is parallel with the projection of described bar resistor on described the first metal layer with described the second resistance 10b.Described first, second cell resistance parallel to each other can be arbitrarily with the relative position relation of described first, second resistance accordingly.As a kind of optimal way of the present embodiment, as shown in Figure 1, described first, second cell resistance also may be selected to be vertical distribution with the relative position of described first, second resistance accordingly.Described first, second cell resistance is respectively perpendicular to connected first, second resistance.
The purpose of this utility model is the alignment precision of monitoring integrated circuit in manufacture process, that is to say, in ic manufacturing process, in the first metal layer, may contain some device architecture, after described insulating barrier has been carried out, utilize lithography registration the device architecture in described the second metal level need to be aimed at some device architecture in described the first metal layer.Bar resistor in first, second cell resistance that the utility model utilization designs in described the first metal layer and alignment procedures on the second metal level comes in contact to monitor alignment precision.
As shown in Figure 1, for convenience of calculation, by described first, second cell resistance and described bar resistor, the distance between projection on the first metal layer sets gradually as arithmetic progression.Be that in Fig. 1, d is tolerance, its value is definite value, and according to the selection range of the device architecture parameter of institute's alignment in prior art, in the present embodiment, the span of d is 5 nanometer to 20 nanometers.Due to the distribution that is centrosymmetric of the projection on described the first metal layer about described bar resistor of first module resistance described in the present embodiment and described second unit resistance, therefore in the first module resistance 11a shown in Fig. 1 and second unit resistance 11b, the length between its adjacent two cell resistance is successively decreased one by one respectively and increases progressively.Minimum range between described first module resistance and described second unit resistance can select to be less than or equal to the width of described bar resistor.As a kind of preferred version of the present embodiment, the minimum range between described first module resistance and described second unit resistance equals the width of described bar resistor.As shown in Figure 1 first module resistance 11a to count first cell resistance and described bar resistor distance between projection on described the first metal layer be from left to right 0, equally, the distance that described second unit resistance 11b counts between first cell resistance and the projection of described bar resistor on described the first metal layer is from right to left 0, as shown in Figure 3, that is described first or the first longer cell resistance of second unit resistance just contact with described bar resistor 14 by the metal throuth hole in the insulating barrier of described the first metal layer top.In described first module resistance, start to count to the right successively from first cell resistance, other cell resistance and the described bar resistor distance between projection on described the first metal layer is followed successively by 2d, 3d, 4d Described second unit resistance and the described bar resistor distance between projection on described the first metal layer is also like this.
The utility model is for making convenience of calculation, described first, second cell resistance by its put in order since second first or its resistance of second unit resistance become successively Geometric Sequence and first first or the resistance of second unit resistance respectively accordingly with described second first or second unit resistance identical.If establish R=1000 Ω, the first cell resistance resistance of described first module resistance can be set to 10R, from left to right successively rehearsal second, the 3rd ... cell resistance resistance is followed successively by 10R, 5R, 2.5R ...From left to right successively rehearsal second, the 3rd ... the resistance of cell resistance, one is 0.5 times of the previous resistance that is adjacent thereafter.
As shown in Figure 3, in the time of the device architecture forming in described the second metal level C, if alignment is inaccurate, device architecture drifts about, the bar resistor 14 being in described the second metal level can move to the left or to the right, therefore, this bar resistor 14 may contact with one or several metal throuth hole 13a in Fig. 3, also may contact with one or several described metal throuth hole 13b, thereby first module resistance 11a or second unit resistance 11b in bar resistor and described the first metal layer A couple together by the metal throuth hole in described insulating barrier.Suppose total N of described first module resistance one, described bar resistor respectively with described first module resistance first cell resistance, the first two cell resistance, first three cell resistance from left to right ... top n cell resistance forms contact, and total resistance of the first module resistance in parallel forming between described bar resistor and described the first resistance is respectively: 10R, 5R, 2.5R ... 10R*0.5
n-1if taking first cell resistance and the firm accessible position of described bar resistor as datum mark, the excursion of the described bar resistor drift distance corresponding with the resistance obtaining after a series of parallel connections of above formation is respectively: 0～d, d～2d, 2d～3d ... (N-1) * d～N*d, therefore forms " resistance-distance " relation; Equally, if described bar resistor is to the direction drift of described second unit resistance 11b, form one or several contact with metal throuth hole 13b shown in Fig. 3, the excursion of the described bar resistor drift distance that a series of resistance obtaining after in parallel of the resistance of the cell resistance after the parallel connection that described bar resistor forms after connecting with described second unit resistance and formation is corresponding is the same with above-mentioned situation.
As shown in Figure 1, the right-hand member of described the first resistance 10a, the second left end of resistance 10b and one end of described bar resistor connect respectively the first pad 12a, the second pad 12b and the 3rd pad 12c for measuring current and voltage accordingly.In the time of the drift of the device architecture generation above-mentioned two situations in described alignment layer, measure respectively electric current and voltage between the first pad 12a and the 3rd pad 12c, the second pad 12b and the 3rd pad 12c, respectively these two groups of voltage and currents are done to ratio and draw resistance, after this resistance and calculating in above-mentioned two situations a series of in parallel, resistance is made comparisons, can learn the drift distance of the described bar resistor corresponding with this resistance, therefore the also drift distance of device architecture in known institute alignment layer.
Fig. 1 has illustrated that in alignment layer, the situation of left and right drift occurs device architecture, if in the time that in alignment layer, device architecture generation is drifted about up and down, the structure 90-degree rotation shown in Fig. 1 can be placed, just can measure the drift up and down of device architecture in alignment layer, generally, can not learn in advance in described alignment layer, which kind of drift can occur device architecture, it is likely to drift about up and down, or left and right drift, or upper left, lower-left, upper right, any in the middle of bottom right drift, therefore, conventionally together with the structure obtaining after structure 90-degree rotation as shown in Figure 1 being combined with the structure shown in Fig. 1, be placed on wafer, and measure accordingly respectively described the first pad 12a and the 3rd pad 12c, electric current and voltage between the second pad 12b and the 3rd pad 12c also calculates resistance and could specify the drift which kind of direction described drift is actually.
The utility model why arrange have axial symmetry distribute or Central Symmetry distribute first module resistance and second unit resistance be the drift for the live width of device architecture in clear and definite institute alignment layer, if that is in the time that the live width of device architecture has drift, the width of described bar resistor is widened identical width to the direction of described first module resistance and second unit resistance simultaneously, therefore, measure electric current and voltage between described the first pad 12a and the 3rd pad 12c, the second pad 12b and the 3rd pad 12c be not 0 and the resistance that draws identical.Can judge that thus live width drift instead of up and down or other drifts such as left and right has occurred described bar resistor.The present embodiment also can described first module resistance and second unit resistance between minimum range be set to be less than the width of described bar resistor.The difference that this setting and the above first module resistance and the minimum range between second unit resistance are set to the setting that equals described bar resistor width be only the datum mark of the calculated cell resistance after in parallel different and in parallel after the excursion of described bar resistor drift distance corresponding to the resistance that obtains different, in addition, other enforcement principles are all identical.
Embodiment bis-
The test structure for monitoring integrated circuit alignment progress described in embodiment mono-of the present utility model is described first, second cell resistance about the distribution that is centrosymmetric of described bar resistor, as a kind of preferred version, described first, second resistance is parallel distribution about described bar resistor simultaneously.Except the structure of embodiment mono-, the present embodiment can also described first, second cell resistance be set to axial symmetry distribution about described bar resistor, as shown in Figure 4, what represent is that described first, second cell resistance distributes axisymmetricly about described bar resistor, and simultaneously described first, second resistance is parallel distribution about described bar resistor.As a kind of preferred version, in this embodiment, described first, second cell resistance is set to vertical distribution with the position of described first, second resistance respectively accordingly.Except above-mentioned different from embodiment mono-, other are that technical characterictic is all identical with embodiment mono-.
Embodiment tri-
As shown in Figure 5, be expressed as the structural representation that described first, second cell resistance distributes axisymmetricly about described bar resistor, simultaneously described first, second resistance also distributes axisymmetricly about described bar resistor, and simultaneously described first, second resistance and described bar resistor form an angle.As a kind of preferred version, in this embodiment, described first, second cell resistance is set to vertical distribution with the position of described first, second resistance respectively accordingly.Except above-mentioned technical characterictic is different from embodiment bis-, other are that technical characterictic is all identical with embodiment bis-with embodiment mono-.
Embodiment tetra-
As shown in Figure 6, be expressed as described first, second cell resistance about the described bar resistor structural representation distributing that is centrosymmetric, simultaneously described first, second resistance is about the distribution that is also centrosymmetric of described bar resistor, and described first, second resistance and described bar resistor form an angle.As a kind of preferred version, in this embodiment, described first, second cell resistance is set to vertical distribution with the position of described first, second resistance respectively accordingly.Except above-mentioned technical characterictic is different from embodiment bis-, other are that technical characterictic is all identical with embodiment mono-, embodiment bis-and embodiment tri-.
In above embodiment mono-to embodiment tetra-, described first, second cell resistance is vertical distribution with the position of described first, second resistance respectively accordingly.Except described this vertical distribution mode, described first, second cell resistance also can be the angled distribution mode that contacts with the position of described first, second resistance respectively accordingly, therefore described first, second cell resistance respectively accordingly with on angled contact distribution mode basis, the position of described first, second resistance, can also form respectively identical new four new embodiment with the other technologies feature of above four embodiment.Therefore the above all embodiment that form described in the utility model are all within the utility model scope required for protection.
In sum, test structure for monitoring integrated circuit alignment precision of the present utility model, in the time that alignment layer generation alignment is offset, any one first module resistance or second unit resistance in any one group in the first module resistance that described bar resistor is parallel to each other with two groups or second unit resistance are connected by the metal throuth hole in insulating barrier, by measuring electric current and the voltage between the first pad and the 3rd pad, the second pad and the 3rd pad, calculate the resistance between above-mentioned two pads.Resistance in the resistance calculating and described " resistance-distance " relation is compared, can judge described the second metal level and occurred the direction of how many side-play amounts and skew.Can effectively monitor the alignment precision between each lithography layer, improve and produce the yield that sheet is produced.So the utility model has effectively overcome various shortcoming of the prior art and tool high industrial utilization.
Above-described embodiment is illustrative principle of the present utility model and effect thereof only, but not for limiting the utility model.Any person skilled in the art scholar all can, under spirit of the present utility model and category, modify or change above-described embodiment.Therefore, have in technical field under such as and conventionally know that the knowledgeable modifies or changes not departing from all equivalences that complete under spirit that the utility model discloses and technological thought, must be contained by claim of the present utility model.
Claims (10)
1. for a test structure for monitoring integrated circuit alignment precision, it is characterized in that, the described test structure for monitoring integrated circuit alignment precision at least comprises:
Be provided with the first metal layer of first, second resistance and be positioned at described the first metal layer top and there is the insulating barrier of some metal throuth holes;
Between described first, second resistance and head end be connected in accordingly respectively first, second cell resistance some parallel to each other of described first, second resistance;
Be positioned at the second metal level of described insulating barrier top;
Described the second metal level has the bar resistor of floor projection between described first, second cell resistance;
Described some first, second cell resistance parallel to each other and the described bar resistor distance between projection on described the first metal layer is respectively increasing or decreasing;
Described first, second resistance and bar resistor one end connect respectively first, second, third pad for testing accordingly;
Described some metal throuth holes respectively projection also contact with it in described first, second cell resistance end;
Described first, second cell resistance about described bar resistor the projection on described the first metal layer axisymmetricly or Central Symmetry distribute;
Minimum range between described first module resistance and second unit resistance is less than or equal to the width of described bar resistor.
2. the test structure for monitoring integrated circuit alignment precision according to claim 1, is characterized in that: the resistance of described first, second resistance equates.
3. the test structure for monitoring integrated circuit alignment precision according to claim 2, is characterized in that: the resistance of described first, second cell resistance is at least 100 times of described first, second resistance.
4. the test structure for monitoring integrated circuit alignment precision according to claim 1, is characterized in that: described first, second cell resistance and the described bar resistor distance between projection on the first metal layer becomes arithmetic progression successively.
5. the test structure for monitoring integrated circuit alignment precision according to claim 1, is characterized in that: described first, second cell resistance by its put in order since second first or its resistance of second unit resistance become successively Geometric Sequence and first first or the resistance of second unit resistance respectively accordingly with described second first or second unit resistance identical.
6. the test structure for monitoring integrated circuit alignment precision according to claim 1, is characterized in that: described its internal structure of first, second cell resistance is square wave-shaped configuration.
7. the test structure for monitoring integrated circuit alignment precision according to claim 1, is characterized in that: the live width of described first, second cell resistance is 10 nanometer to 500 nanometers.
8. the test structure for monitoring integrated circuit alignment precision according to claim 1, is characterized in that: described first, second resistance respectively about described bar resistor axisymmetricly or Central Symmetry distribute.
9. the test structure for monitoring integrated circuit alignment precision according to claim 8, is characterized in that: described first, second resistance is parallel with described bar resistor respectively.
10. the test structure for monitoring integrated circuit alignment precision according to claim 8 or claim 9, is characterized in that: described first, second resistance is in vertical distribution with described first, second cell resistance respectively accordingly.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201420042194.7U CN203707088U (en) | 2014-01-22 | 2014-01-22 | Test structure used for monitoring overlay accuracy of integrated circuit |
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| CN201420042194.7U CN203707088U (en) | 2014-01-22 | 2014-01-22 | Test structure used for monitoring overlay accuracy of integrated circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105448761A (en) * | 2014-08-26 | 2016-03-30 | 北大方正集团有限公司 | Method and device for testing expanding and shrinking value of semiconductor technology |
| CN109905127A (en) * | 2019-03-21 | 2019-06-18 | 苏州神指微电子有限公司 | A kind of sampling resistor arrangement of two-step ADC |
-
2014
- 2014-01-22 CN CN201420042194.7U patent/CN203707088U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105448761A (en) * | 2014-08-26 | 2016-03-30 | 北大方正集团有限公司 | Method and device for testing expanding and shrinking value of semiconductor technology |
| CN105448761B (en) * | 2014-08-26 | 2018-06-26 | 北大方正集团有限公司 | The test method and device of semiconductor technology harmomegathus value |
| CN109905127A (en) * | 2019-03-21 | 2019-06-18 | 苏州神指微电子有限公司 | A kind of sampling resistor arrangement of two-step ADC |
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Granted publication date: 20140709 Termination date: 20190122 |