CN203675066U - Pulse D type trigger employing floating gate MOS pipe - Google Patents

Abstract

The utility model discloses a pulse D-type flip-flop adopting a floating gate MOS tube, comprising: an inverter chain for inverting and delaying a clock signal, which is composed of three inverters connected in cascade; two differential configurations The pull-down multi-input floating gate MOS transistor, the switching state of these two multi-input floating gate MOS transistors is controlled by the clock signal, the delayed inversion signal of the clock signal, the data input signal and its inversion signal, so that the data signal and its inversion signal The inverted signal can be sampled within a very narrow pulse width after the edge of the clock signal; a pair of cross-coupled pMOS transistors is used to latch the differential output signal; two output inverters are used for two complementary output The terminal signal is buffered. The beneficial effects of the utility model are: the structure is simpler, the number of tubes used is less, and the speed and power consumption are better. And because the number of tubes connected in series in the traditional pull-down MOS tube cascade network is reduced, the utility model can work at a lower power supply voltage.

Description

Adopt the pulsed D D-flip flop of floating-gate MOS tube

Technical field

The utility model relates to a kind of pulsed D D-flip flop, and more specifically, it relates to a kind of pulsed D D-flip flop that adopts floating-gate MOS tube.

Background technology

The importants such as trigger is the basic tfi module of digital system, its speed, power consumption, area and reliability to digital system.In many trigger structures, adopt the trigger of difference structure to have to provide complementary double track output, low-power consumption and the feature such as simple in structure simultaneously and come into one's own.The edge triggered flip flop of difference structure can adopt MS master-slave type design, also can adopt pulsed design.The former is made up of two-stage differential type latch, and the latter only has single latch to form.Pulse trigger be by clock rise (decline) along near short pulse of generation drive latch, realize the sampling to input data, this means input data can clock effectively along after arrival, be 0 can be even to bear its settling time.Therefore the speed of pulse trigger is faster than conventional trigger, and has lower power consumption, can be applicable to the design of high-performance digital systems.Adopt the existing multiple design of pulse trigger of the differential cascade switch designs of common metal-oxide-semiconductor formation to be disclosed, and adopt the trigger of novel many input floating-gate MOS devices design, the current published MS master-slave type structure of only having.

Many input floating-gate MOS tubes are new devices that propose in recent years a kind of has functional strong, the feature such as threshold value control is flexible, in multiple fields such as simulation, numeral and neural nets, its application have been carried out to further investigation so far.The double level polysilicon CMOS technique of the processing technology of this device and standard is completely compatible, and its basic structure, capacitor model and symbol thereof represent as shown in Figure 1.It has multiple input grids and a floating boom utmost point, and wherein floating boom is formed by ground floor polysilicon, and multiple input control grid are formed by second layer polysilicon.Between input and floating boom, realize coupling by electric capacity.V in figure _frepresent the voltage on floating boom, V ₀for underlayer voltage, V ₁, V ₂..., V _nfor applied signal voltage.C ₀be the coupling capacitance between floating boom and substrate, it is mainly by gate oxide capacitor C _oxform C ₁, C ₂..., C _nfor the coupling capacitance between each input grid and floating boom.Net charge Q on floating boom _fprovided by following formula:

$Q_F=\underset{i=0}{\overset{n}{\mathrm{\Σ}}}{C}_i(V_F-V_i)=V_F\underset{i=0}{\overset{n}{\mathrm{\Σ}}}{C}_i-\underset{i=0}{\overset{n}{\mathrm{\Σ}}}{C}_i{V}_i;---\left(1\right)$

For n raceway groove floating-gate MOS tube, substrate ground connection, therefore V ₀=0.Suppose that the initial charge on floating boom is zero, according to law of conservation of charge, can be obtained fom the above equation:

$V_F=\underset{i=1}{\overset{n}{\mathrm{\Σ}}}{w}_i{V}_i;---\left(2\right)$

$w_i=\frac{C_i}{C_0+\underset{j=1}{\overset{n}{\mathrm{\Σ}}}{C}_j};---\left(3\right)$

If V _tfor the threshold voltage of the pipe seen into by floating boom end, work as V _f>V _tshi Guanzi conducting.Can be found out by formula (2) and (3), input floating-gate MOS tube more and can, to the weighted sum of each grid input signal, go to control " opening " and " pass " of metal-oxide-semiconductor by the summed result calculating.The weighted sum computing of noticing all input signals that it carries out on floating boom utilizes capacitance coupling effect to carry out with voltage mode, and this has shown that it has the low-power consumption characteristic more outstanding than current-mode summation technology.

Adopt the d type flip flop of the difference structure of many input floating-gate MOS tubes design (to see document L.F.C.Sinencio as shown in Figure 2, A.D.Sanchez, and J.R.Angulo, " Anovel serial multiplier using floating-gate transistors; " Proc.of ISCAS, vol.2, pp.861-864, May2004.).In this trigger, adopt many inputs floating-gate MOS tube to substitute the metal-oxide-semiconductor switch cascade network in traditional differential configuration trigger, this makes circuit structure obtain very significantly simplifying, and owing to having reduced the serial connection number of metal-oxide-semiconductor, this circuit can be worked under lower supply voltage.But what this trigger adopted is MS master-slave type design, the differential latches that it has two employings to input floating-gate MOS tube more forms, and therefore the performance such as speed and power consumption is not as similar pulse trigger.

Summary of the invention

The purpose of this utility model is to overcome deficiency of the prior art, provides the aspects such as a kind of speed, power consumption to be all better than the pulsed D D-flip flop of the employing floating-gate MOS tube of MS master-slave type floating-gate MOS trigger.

The pulsed D D-flip flop of this employing floating-gate MOS tube, comprises clock signal is carried out to the chain of inverters of inverse delayed, drop-down many input floating-gate MOS tubes of pair of differential configuration, pMOS pipe and two output inverters of pair of cross coupling;

Described chain of inverters of clock signal being carried out to inverse delayed is formed by inverter serial connection, comprising: the first inverter X1, the second inverter X2 and the 3rd inverter X3; The input termination clock signal clk of described the first inverter X1, the input of the second inverter X2 described in the output termination of this first inverter X1, the input of the 3rd inverter X3 described in the output termination of this second inverter X2, the output of the 3rd inverter X3 forms the inverse delayed signal node clkp of clock signal;

Drop-down many input floating-gate MOS tubes of described pair of differential configuration, comprising: the first N-shaped inputs floating-gate MOS tube m1 more and the second N-shaped is inputted floating-gate MOS tube m2 more; Described the first N-shaped is inputted floating-gate MOS tube m1 more, the source ground of this pipe, and output in the middle of the drain electrode of this pipe connects, is labeled as the first intermediate output node

, 4 input grids of this more than first inputs floating-gate MOS tube m1 connect respectively data input signal D, described clock signal clk, described clock inverse delayed signal node clkp and ground; Described the second N-shaped is inputted floating-gate MOS tube m2 more, the source ground of this pipe, and the drain electrode of this pipe connects another middle output, is labeled as the second intermediate output node Q _m, 4 input grids of this more than second inputs floating-gate MOS tube m2 connect respectively oppisite phase data input signal

described clock signal clk, described clock inverse delayed signal node clkp and ground;

The pMOS pipe of described pair of cross coupling, comprises p-type metal-oxide-semiconductor m3 and p-type metal-oxide-semiconductor m4; Described p-type metal-oxide-semiconductor m3, the source electrode of this pipe meets power supply V _dD, the drain electrode of this pipe connects described the first intermediate output node

, the grid of this pipe meets described the second intermediate output node Q _m; Described p-type metal-oxide-semiconductor m4, the source electrode of this pipe meets power supply V _dD, the drain electrode of this pipe meets described the second intermediate output node Q _m, the grid of this pipe connects described the first intermediate output node

Described two output inverters, comprising: the 4th output inverter X4 and the 5th output inverter X5; Described the 4th output inverter X4, the first intermediate output node described in the input termination of the 4th output inverter X4

, the output of the 4th output inverter X4 forms the first output signal Q of described d type flip flop; Described the 5th output inverter X5, the second intermediate output node Q described in the input termination of the 5th output inverter X5 _m, the output of the 5th output inverter X5 forms the second output signal of described d type flip flop

The beneficial effects of the utility model are: with the difference type pulse trigger comparison of traditional employing metal-oxide-semiconductor, the difference type pulse trigger of floating-gate MOS tube is inputted in the employing the utility model proposes more, structurally more simple, the number of tubes adopting is less, and owing to having reduced the pipe number being connected in series in conventional drop metal-oxide-semiconductor cascade network, make the utility model can work in lower supply voltage.Input the MS master-slave D-flip flop comparison of floating-gate MOS tube with existing employing, still less, speed and power consumption are more excellent for the pipe number that the pulse trigger the utility model proposes adopts more.

Accompanying drawing explanation

Fig. 1 is that N-type is inputted floating-gate MOS tube structure chart, capacitor model and pipe symbol more;

Fig. 2 is the differential type MS master-slave D-flip flop that adopts many input floating-gate MOS tubes;

Fig. 3 is the pulsed D D-flip flop that floating-gate MOS tube is inputted in employing described in the utility model more;

Fig. 4 adopts the analog result of HSPICE software to the pulsed D D-flip flop shown in Fig. 3;

Fig. 5 is the two-divider that adopts the pulsed D D-flip flop the utility model proposes to form;

Fig. 6. for adopting the analog result of HSPICE software to two-divider shown in Fig. 4.

Embodiment

Below in conjunction with drawings and Examples, the utility model is described further.Although the utility model is described in connection with preferred embodiment, should know, do not represent that the utility model is limited in described embodiment.On the contrary, the utility model is by alternative, modified model and the equivalent contained in the scope of the present utility model that can be included in attached claims restriction.

As shown in Figure 3, the pulsed D D-flip flop of this employing floating-gate MOS tube, comprises clock signal is carried out to the chain of inverters of inverse delayed, drop-down many input floating-gate MOS tubes of pair of differential configuration, pMOS pipe and two output inverters of pair of cross coupling;

Described chain of inverters of clock signal being carried out to inverse delayed is formed by inverter serial connection, comprising: the first inverter X1, the second inverter X2 and the 3rd inverter X3; The input termination clock signal clk of described the first inverter X1, the input of the second inverter X2 described in the output termination of this first inverter X1, the input of the 3rd inverter X3 described in the output termination of this second inverter X2, the output of the 3rd inverter X3 forms the inverse delayed signal node clkp of clock signal;

Drop-down many input floating-gate MOS tubes of described pair of differential configuration, comprising: the first N-shaped inputs floating-gate MOS tube m1 more and the second N-shaped is inputted floating-gate MOS tube m2 more; Described the first N-shaped is inputted floating-gate MOS tube m1 more, the source ground of this pipe, and output in the middle of the drain electrode of this pipe connects, is labeled as the first intermediate output node

, 4 input grids of this more than first inputs floating-gate MOS tube m1 connect respectively data input signal D, described clock signal clk, described clock inverse delayed signal node clkp and ground; Described the second N-shaped is inputted floating-gate MOS tube m2 more, the source ground of this pipe, and the drain electrode of this pipe connects another middle output, is labeled as the second intermediate output node Q _m, 4 input grids of this more than second inputs floating-gate MOS tube m2 connect respectively oppisite phase data input signal

described clock signal clk, described clock inverse delayed signal node clkp and ground;

The pMOS pipe of described pair of cross coupling, comprises p-type metal-oxide-semiconductor m3 and p-type metal-oxide-semiconductor m4; Described p-type metal-oxide-semiconductor m3, the source electrode of this pipe meets power supply V _dD, the drain electrode of this pipe connects described the first intermediate output node

, the grid of this pipe meets described the second intermediate output node Q _m; Described p-type metal-oxide-semiconductor m4, the source electrode of this pipe meets power supply V _dD, the drain electrode of this pipe meets described the second intermediate output node Q _m, the grid of this pipe connects described the first intermediate output node

Described two output inverters, comprising: the 4th output inverter X4 and the 5th output inverter X5; Described the 4th output inverter X4, the first intermediate output node described in the input termination of the 4th output inverter X4

, the output of the 4th output inverter X4 forms the first output signal Q of described d type flip flop; Described the 5th output inverter X5, the second intermediate output node Q described in the input termination of the 5th output inverter X5 _m, the output of the 5th output inverter X5 forms the second output signal of described d type flip flop

The structure of circuit and operation principle are: this trigger comprises that the N-shaped that clock signal is carried out to chain of inverters (by X1, X2 and X3 are composed in series), the pair of differential configuration of inverse delayed inputs pMOS pipe m3 and m4, two inverter X4 and X5 that output signal is cushioned of floating-gate MOS tube m1 and m2, pair of cross coupling more.Many input floating-gate MOS tube m1 are controlled by inverse delayed signal clkp and the data input signal D of clock signal clk, this clock signal.Many input floating-gate MOS tube m2 are by the inverse delayed signal clkp of clock signal clk, this clock signal and the inversion signal of data input signal

control.Wherein two grids of floating-gate MOS tube m1 and m2 be all connected to respectively clk and clkp signal be for make this trigger only in a very short pulse duration after rising edge clock signal in pellucidity, realize sampling input data.

Only have when clk=1(high level), clkp=1(high level), D or

also while being high level, the magnitude of voltage after the weighted sum obtaining on floating boom just can be greater than the threshold voltage of floating-gate MOS tube, makes corresponding floating-gate MOS tube conducting.Be t the time of delay of supposing the each inverter in chain of inverters _pd, so only 3t after rising edge clock _pdpulse duration in, latch is just in pellucidity.At this moment, if D=1, floating-gate MOS tube m1 conducting, intermediate output signal node

pull down to (

), this makes pMOS pipe m4 conducting, pMOS pipe m3 cut-off, intermediate output signal node Q _mbe pulled to V _dD(be Q _m=1),

and Q _magain respectively through the buffering of output inverter X4 and X5, obtain this trigger output signal Q=1 and

otherwise, if now

floating-gate MOS tube m2 conducting, intermediate output signal node Q _mpulling down to (is Q _m=0), this makes pMOS pipe m3 conducting, pMOS pipe m4 cut-off, intermediate output signal node be pulled to V _dD(

),

and Q _magain respectively through the buffering of output inverter X4 and X5, obtain this trigger output signal Q=0 and

in the time that clk or clkp are low level, floating-gate MOS tube m1 and m2 are all in cut-off state, and output difference sub-signal is kept by cross-linked pMOS pipe.

Adopt TSMC 0.35 μ m double level polysilicon CMOS technological parameter, get supply voltage V _dD=1.5V, clock frequency is 100MHz, and floating-gate MOS input coupling capacitance is 100fF, and each output node load capacitance is 100fF, to the HSPICE analog result of trigger shown in Fig. 3 as shown in Figure 4.Analog result shows, this trigger is the edge triggered flip flop that a rising edge triggers.Adopt above-mentioned identical parameters and input data signal, through HSPICE software simulation, table 1 has provided the comparative result (all not containing clock network) of the MS master-slave D-flip flop of the employing floating-gate MOS tube shown in pulse trigger and the Fig. 2 the utility model proposes, wherein t _{p (clk-Q)}for clock edge is to the delay of output.

Table 1. adopts the comparison of the d type flip flop of floating-gate MOS tube

Can find out that the pulsed D D-flip flop of the employing floating-gate MOS tube the utility model proposes is compared with adopting the MS master-slave D-flip flop of floating-gate MOS tube, it is few that the trigger that the utility model proposes has pipe number, postpones feature little and low in energy consumption.For the function of the trigger that further checking the utility model proposes, Fig. 5 has provided the two-divider that adopts the pulsed D D-flip flop the utility model proposes to form.Adopt above-mentioned same process parameter, get supply voltage V _dD=1.5V, clock frequency is 100MHz, and each output node load capacitance is 100fF, and to the HSPICE analog result of circuit shown in Fig. 5 as shown in Figure 6, this analog result has been verified the validity of the flip flop design scheme that proposes again.

Claims (1)

1. A pulse D-type flip-flop that adopts a floating gate MOS transistor is characterized in that: it includes an inverter chain that carries out an inversion delay to a clock signal, a pair of pull-down multi-input floating gate MOS transistors of a differential configuration, a pair of Cross-coupled pMOS transistors and two output inverters; The inverter chain for inverting and delaying the clock signal is composed of inverters connected in series, including: a first inverter X1, a second inverter X2 and a third inverter X3; the first The input terminal of the inverter X1 is connected to the clock signal clk, the output terminal of the first inverter X1 is connected to the input terminal of the second inverter X2, and the output terminal of the second inverter X2 is connected to the third inverter X2. The input end of the inverter X3, the output end of the third inverter X3 forms the inversion delay signal node clkp of the clock signal; the pair of differentially configured pull-down multi-input floating gate MOS transistors includes: the first n type multi-input floating-gate MOS transistor m1 and the second n-type multi-input floating-gate MOS transistor m2; the source of the first n-type multi-input floating-gate MOS transistor m1 is grounded, and the drain of the transistor is connected to the intermediate output end, labeled as the first intermediate output node

, the four input gates of the first multi-input floating gate MOS transistor m1 are respectively connected to the data input signal D, the clock signal clk, the clock inversion delay signal node clkp and ground; the second n-type multi-input Floating gate MOS transistor m2, the source of this transistor is grounded, the drain of this transistor is connected to another intermediate output terminal, marked as the second intermediate output node Q _m , the four input gates of the second multi-input floating gate MOS transistor m2 The poles are respectively connected to the inverting data input signal

The clock signal clk, the clock inversion delay signal node clkp and ground; The pair of cross-coupled pMOS transistors includes p-type MOS transistor m3 and p-type MOS transistor m4; the source of the p-type MOS transistor m3 is connected to the power supply V _DD , and the drain of the transistor is connected to the first an intermediate output node

, the gate of the transistor is connected to the second intermediate output node Q _m ; the source of the p-type MOS transistor m4 is connected to the power supply V _DD , and the drain of the transistor is connected to the second intermediate output node Q _m , the gate of the transistor is connected to the first intermediate output node

The two output inverters include: a fourth output inverter X4 and a fifth output inverter X5; the fourth output inverter X4, the input terminal of the fourth output inverter X4 is connected to the first intermediate output node

, the output terminal of the fourth output inverter X4 forms the first output signal Q of the D-type flip-flop; the fifth output inverter X5, the input terminal of the fifth output inverter X5 is connected to the second intermediate output node Q _m , the output terminal of the fifth output inverter X5 forms the second output signal of the D-type flip-flop

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