CN203674211U - Array substrate and display device - Google Patents

Abstract

The utility model discloses an array substrate, which comprises a gate line and a data line formed on the substrate, and a plurality of pixel units defined by the gate line and the data line, and each pixel unit is divided into a thin film transistor area and a Light-emitting region; at least one thin-film transistor is formed in the thin-film transistor region, and the thin-film transistor includes a source-drain electrode layer, an active layer, a gate insulating layer and a gate formed sequentially on the substrate; in the light-emitting region An anode is formed above the substrate, the anode is connected to the drain of the source-drain electrode layer, the anode and the gate are made of the same material and formed in one process, an organic light-emitting layer and a cathode are sequentially formed above the anode, and the The anode, the organic light-emitting layer and the cathode in the region corresponding to the anode jointly form an organic light-emitting diode; a pixel definition layer is also formed on the thin film transistor. The method of the utility model reduces the number of masks, thereby saving the production process and production cost.

Description

Array substrate and display device

technical field

The utility model relates to the field of display technology, in particular to an array substrate, a manufacturing method thereof, and a display device.

Background technique

A conventional top-emitting AMOLED display device is shown in Figure 1, including: a first grid 2 formed on a substrate 1, a second grid 2' and grid lines (not shown in the figure), formed on the first grid electrode 2, the second grid 2' and the gate insulation layer 3 on the gate line, the first active layer 4 and the second active layer 4' formed on the gate insulation layer 3, and the first active layer 4' formed on the first active layer 4 and the etch barrier layer 5 on the second active layer 4', the first source and drain layer 6 (including the first source and the first drain) and the second source and drain formed on the etch barrier layer 5 layer 6' (including the second source and the second drain), and the passivation layer 7 formed on the first source and drain layer 6 and the second source and drain layer 6'. Among them, the first gate 2, the gate insulating layer 3, the first active layer 4, the etch stop layer 5 and the first source-drain layer 6 form a switching thin film transistor (switching TFT), and the second gate 2', gate insulating The layer 3, the second active layer 4', the etching stop layer 5 and the second source-drain layer 6' form a driving thin film transistor (driving TFT).

The passivation layer 7 is formed on the first source-drain layer 6 and the second source-drain layer 6', on which a via hole for connecting the anode 8 (opaque) to the second source-drain layer 6' is formed, and the anode 8 is formed on over the passivation layer 7. A pixel definition layer 11 and an organic light-emitting layer 9 are also formed on the anode 8 , and a transparent cathode 10 is formed on the organic light-emitting layer 9 .

Among them, the active layer is usually an oxide semiconductor material, that is, the formed TFT is OxideTFT, so an additional etching stopper layer 5 is needed to prevent the oxide semiconductor material from being damaged when the source and drain layers are etched, which affects the TFT. performance. Therefore, the fabrication of the above-mentioned AMOLED display device usually requires 7 times of mask process (mask) formation (gate, via hole on the gate insulating layer, active layer, via hole on the etch stop layer, source and drain layer, passivation layer The via hole on the upper layer and the pixel definition layer each have a mask), the process is complicated and the cost is high.

Utility model content

(1) Technical problems to be solved

The technical problem to be solved by the utility model is: how to reduce the manufacturing process and cost of the display device.

(2) Technical solution

In order to solve the above technical problems, the utility model provides an array substrate, including gate lines and data lines formed on the substrate, and a plurality of pixel units defined by the gate lines and data lines, characterized in that each The pixel unit is divided into a thin film transistor area and a light emitting area;

The thin film transistor region is formed with at least one thin film transistor, and the thin film transistor includes a source and drain electrode layer, an active layer, a gate insulating layer and a gate sequentially formed on the substrate;

An anode is formed above the substrate of the light-emitting region, the anode is connected to the drain of the source-drain electrode layer, the anode and the gate are made of the same material and formed in one process, and an organic light-emitting layer and an organic light-emitting layer are sequentially formed above the anode a cathode, and the anode and the organic light-emitting layer and the cathode in the region corresponding to the anode jointly form an organic light-emitting diode;

A pixel definition layer is also formed on the thin film transistor.

Wherein, the organic light emitting layer and the cathode cover the entire substrate area, and the pixel definition layer is formed between the thin film transistor and the organic light emitting layer.

Wherein, the pixel definition layer also covers the regions corresponding to the gate lines and data lines.

Wherein, the material of the active layer is an oxide semiconductor.

Wherein, the material of the grid and the anode is a metal or a conductive metal compound with reflective properties.

Wherein, the metal with reflective properties includes: Ag, Au, Al, Ti or Cr; the conductive metal compound includes: AlX, MoX or CuX.

Wherein, the thickness of described gate and anode is:

The present invention also provides a display device, comprising the array substrate described in any one of the above.

(3) Beneficial effects

The array substrate of the utility model adopts a top gate structure, and the source and drain electrodes are located under the active layer and the gate (the etching barrier layer may not be required), so that the number of masks is reduced when manufacturing the array substrate, thereby saving the production process. and production costs.

Description of drawings

FIG. 1 is a schematic structural diagram of an array substrate of an existing top-emitting OLED display device;

2 is a schematic structural view of the array substrate finally formed by the method of the present invention;

Fig. 3 is a structural schematic diagram of forming a source-drain electrode layer on the substrate in the method for manufacturing the array substrate of the present invention;

Fig. 4 is the structural representation of forming photoresist pattern on the basis of Fig. 3;

Fig. 5 is a schematic structural view of forming an active layer and an etching barrier material film on the basis of Fig. 4;

Fig. 6 is a schematic structural view of forming an active layer and an etching barrier pattern on the basis of Fig. 5;

FIG. 7 is a schematic structural view of forming a gate insulating layer on the basis of FIG. 6;

FIG. 8 is a schematic structural view of forming a via hole on the gate insulating layer based on FIG. 7;

FIG. 9 is a schematic structural view of forming a gate material film on the basis of FIG. 8;

Fig. 10 is a structural schematic diagram of forming a grid and an anode on the basis of Fig. 9;

FIG. 11 is a schematic structural diagram of forming a pixel definition layer on the basis of FIG. 10 .

Detailed ways

Below in conjunction with accompanying drawing and embodiment, the specific embodiment of the utility model is described in further detail. The following examples are used to illustrate the utility model, but not to limit the scope of the utility model.

The array substrate provided by the present invention includes gate lines and data lines formed on the substrate, and a plurality of pixel units defined by the gate lines and data lines. As shown in FIG. 2, each pixel unit is divided into a thin film transistor area E and a light emitting area F;

The thin film transistor region E is formed with at least one thin film transistor, and the thin film transistor includes a source-drain electrode layer (including a source electrode 102 a and a drain electrode 102 b ), an active layer 104 , an etch stop layer 105 ( The etch stop layer 105 ), the gate insulating layer 106 and the gate 109 may also be absent. The material of the active layer 104 is an oxide semiconductor, such as IGZO.

An anode 110 is formed above the substrate 101 in the light emitting region F, and the anode 110 is connected to the drain 102b of the source-drain electrode layer. The anode 110 is made of the same material as the gate 109 and is formed in one process. An organic light-emitting layer 112 and a cathode 113 are sequentially formed above the anode, and the organic light-emitting layer 112 and the cathode 113 of the anode 110 and the region corresponding to the anode 110 (ie region F) jointly form an organic light-emitting diode. The thin film transistor is used to drive an organic light emitting diode.

A pixel definition layer 111 is also formed on the thin film transistor. Since the organic light-emitting layer 112 and the cathode 113 cover the entire area of the substrate 101 during manufacture, in order to prevent the light emission from the organic light-emitting layer 112 corresponding to the region E of the thin-film transistor and the light emitted from the light-emitting region F from affecting the performance of the thin-film transistor, the pixel definition layer 111 formed between the thin film transistor and the organic light emitting layer 112 . The pixel definition layer 111 also covers areas corresponding to gate lines and data lines.

The array substrate of this embodiment is an array substrate of a top-emitting OLED display device, so the materials of the grid 109 and the anode 110 are metals or conductive metal compounds with reflective properties, such as: Ag, Au, AlX, MoX, CuX, Al , Ti or Cr, etc., where AlX, MoX or CuX are conductive metal compounds. The thickness of grid 109 and anode 110 is:

Also provided is a method for manufacturing the above-mentioned array substrate, including the following steps:

In step 1, patterns of data lines and source-drain electrode layers are formed on the substrate 101 (transparent substrate, such as a glass substrate or a quartz substrate). Specifically, this step may be to form a source-drain metal thin film on the substrate 101 (which may be formed by sputtering, evaporation or chemical vapor deposition CVD), and then pass a patterning process (usually including photoresist coating, exposure, development, etching, etc.) etching, photoresist stripping, etc.) to form patterns of the source electrode 102a and the drain electrode 102b, as shown in FIG. 3 .

Step 2, forming a pattern of an active layer on the substrate shown in FIG. 3 . Specifically include:

The photoresist is coated on the substrate 101 in FIG. 3 , and as shown in FIG. 4 , the photoresist is exposed and developed to remove the photoresist in the active layer and the etching barrier layer region A, and the photoresist 103 remains.

As shown in Figure 5, the active layer material films 104' are sequentially formed, except that the active layer material films 104' in the active layer area A are covered on the substrate 101, and the active layer material films 104' in other areas are covered. on the photoresist 103 . In FIG. 5 , a layer of etch barrier material film 105 ′ can also be formed on the source layer material film 104 ′.

As shown in FIG. 6 , the remaining photoresist 103 is stripped to form a pattern of the active layer 104 . In this embodiment, the material of the active layer is an oxide semiconductor, such as IGZO. In FIG. 6 , the pattern of the etch stop layer 105 can also be formed (the etch stop layer 105 is optional).

Step 3, forming a pattern including a gate insulating layer, and exposing a region where the drain is connected to the anode to be formed. This step specifically includes:

As shown in FIG. 7 , a gate insulating layer 106 is formed on the substrate after step two.

As shown in FIG. 8 , in this embodiment, a via hole 107 passing through the gate insulating layer 106 is formed in the region where the drain electrode 102 b is connected to the anode to be formed by a patterning process. Of course, the gate insulating film of the anode region and the region where the drain is connected to the anode to be formed can also be directly etched away by a patterning process, so as to finally form the gate insulating layer 106 .

Step 4, forming a pattern including grid lines, grids and anodes. This step specifically includes:

As shown in FIG. 9 , a gate material film 108 is formed on the substrate after step three.

As shown in FIG. 10 , the pattern of the gate 109 is formed in the gate region C through a patterning process, and the pattern of the anode 110 is formed in the anode region D. After the gate 109 is formed, a thin film transistor with a top gate structure (including the source 102 a , the drain 102 b , the active layer 104 , the etch stop layer 105 , the gate insulating layer 106 and the gate 109 ) is formed.

In this embodiment, since the anode 110 reflects the light emitted by the organic luminescent material, the material of the grid 109 and the anode 110 is a metal with reflective properties or a conductive metal compound, which can be Ag, Au, AlX, MoX, CuX , Al, Ti or Cr, where AlX, MoX or CuX are conductive metal compounds. The thickness of grid 109 and anode 110 is:

Step five, forming a pattern including a pixel definition layer, an organic material layer and a transparent cathode. Specifically include:

As shown in Figure 11, the area E (i.e. the thin film transistor area) on the substrate after step 4 forms the pixel definition layer 111 through a patterning process, and the area F where the pixel definition layer 111 is not formed is the pixel area, that is, the organic light-emitting layer. The light-emitting area, generally, the pixel definition layer 111 is mainly used to block the area corresponding to the TFT, the gate line and the data line, so as to prevent the active layer 104 of the oxide semiconductor in the thin film transistor from being illuminated, thereby ensuring the performance of the thin film transistor.

On the basis of Figure 11, the organic light-emitting layer 112 and the cathode 113 are sequentially formed, as shown in Figure 2, the anode 110, the organic light-emitting layer 112 and the cathode 113 corresponding to the region F together form an organic light-emitting diode, thereby forming an array of OLED display devices substrate.

In the manufacturing method of the array substrate of the present embodiment, a mask (ie, a patterning process) is used in Steps 1 to 5, and a total of 5 masks are used. Compared with the existing seven-time masking process of the array substrate, the times of masking are reduced, and the process flow and cost are saved.

The utility model also provides a display device, including the above-mentioned array substrate. The display device can be any product or component with a display function such as an OLED panel, a mobile phone, a tablet computer, a television set, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.

The above embodiments are only used to illustrate the utility model, but not to limit the utility model. Those of ordinary skill in the relevant technical fields can also make various changes and modifications without departing from the spirit and scope of the utility model. , so all equivalent technical solutions also belong to the category of the utility model, and the patent protection scope of the utility model should be defined by the claims.

Claims (8)

1. An array substrate, comprising gate lines and data lines formed on the substrate, and a plurality of pixel units defined by the gate lines and data lines, characterized in that each of the pixel units is divided into thin film transistor regions and luminous regions; The thin film transistor region is formed with at least one thin film transistor, and the thin film transistor includes a source and drain electrode layer, an active layer, a gate insulating layer and a gate formed sequentially on the substrate; An anode is formed above the substrate of the light-emitting region, the anode is connected to the drain of the source-drain electrode layer, the anode and the gate are made of the same material and formed in one process, and an organic light-emitting layer and an organic light-emitting layer are sequentially formed above the anode A cathode, and the anode and the organic light-emitting layer and the cathode in the region corresponding to the anode jointly form an organic light-emitting diode; A pixel definition layer is also formed on the thin film transistor. the 2 . The array substrate according to claim 1 , wherein the organic light emitting layer and the cathode cover the entire substrate area, and the pixel definition layer is formed between the thin film transistor and the organic light emitting layer. the 3 . The array substrate according to claim 2 , wherein the pixel definition layer also covers areas corresponding to the gate lines and the data lines. the 4 . The array substrate according to claim 1 , wherein a material of the active layer is an oxide semiconductor. the 5. The array substrate according to any one of claims 1-3, characterized in that, the material of the grid and the anode is metal with reflective properties. the 6 . The array substrate according to claim 5 , wherein the metal with reflective properties comprises: Ag, Au, Al, Ti or Cr. the 7. The array substrate according to any one of claims 1 to 3, wherein the thicknesses of the grid and the anode are:

8. A display device, comprising the array substrate according to any one of claims 1-7. the

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