CN203645536U - Quasi-resonance fly-back converter and controller thereof - Google Patents
Quasi-resonance fly-back converter and controller thereof Download PDFInfo
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- CN203645536U CN203645536U CN201320892170.6U CN201320892170U CN203645536U CN 203645536 U CN203645536 U CN 203645536U CN 201320892170 U CN201320892170 U CN 201320892170U CN 203645536 U CN203645536 U CN 203645536U
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Abstract
The utility model discloses a quasi-resonance fly-back converter and a controller thereof. The quasi-resonance fly-back converter comprises a switch tube which controls power supply of input voltage, and is characterized in that the controller comprises a zero-cross detection comparator, a minimum locking logic circuit and a driving pulse generating module, wherein the zero-cross detection comparator detects oscillation voltages, which are generated after the switch tube is switched off, of the quasi-resonance fly-back converter, and generates a minimum detection signal when the oscillation voltage is minimal; the minimum locking logic circuit is connected with the output end of the zero-cross detection comparator to receive the minimum detection signal, and counts the minimums of the minimum detection signal to emit an effective minimum signal when a selected minimum occurs; and the driving pulse generating module is coupled to the output end of the minimum locking logic circuit, and emits a trigger signal under instruction of the effective minimum signal to switch on the switch tube.
Description
Technical field
The utility model relates to quasi-resonance (QR) technology in electric power management circuit, relates in particular to a kind of quasi-resonance inverse excitation type converter and controller thereof.
Background technology
The application of electric power management circuit is very extensive, most electric power management circuits all need built-in or external MOSFET, the current value that flows through MOSFET by detection can obtain the voltage signal relevant to this current value or current signal, then controls the turn-on and turn-off of this MOSFET according to this voltage signal or current signal.
The application of quasi-resonance (QR) inverse excitation type converter is very extensive.The principal character of this framework is to realize no-voltage conducting (ZVS) work, can effectively reduce switching loss, helps to weaken electromagnetic interference (EMI) signal simultaneously.Figure 1A is the schematic diagram of quasi-resonance inverse excitation type converter 10, and it can comprise resistance R
p, transformer 101, inductance L
p, switching tube M
1, capacitor C
p, diode D
0, output capacitor C
out, and controller 100.Quasi-resonance inverse excitation type converter 10 is substantially the same with the principle of traditional inverse excitation type converter, and difference is switching tube M
1the conducting moment different.Those skilled in the art can understand, quasi-resonance inverse excitation type converter 10 can adopt other suitable structures, and is not limited to the embodiment shown in Figure 1A.Take Figure 1A as example, controller 100 produces and drives signal Drv for control switch pipe M
1turn-on and turn-off, thereby control inputs voltage V
inbreak-make.As switching tube M
1when conducting, input voltage V
inconvert output voltage V to via transformer 101
out, and in transformer 101 storage power.As switching tube M
1have no progeny in pass, input voltage V
inno longer power to transformer 101, the energy storing in transformer 101 continues to provide output voltage V
out.After the energy release in the secondary winding of transformer 101 is complete (being after transformer 101 magnetic fluxs reset completely), at switching tube M
1drain electrode there is sine-wave oscillation voltage, its frequency of oscillation is by L
p, C
pdetermine, decay factor is by R
pdetermine.For traditional inverse excitation type converter, its operating frequency is fixed, therefore switching tube M
1conducting likely appears at any position (comprising summit and the lowest point) of oscillating voltage again.And quasi-resonance inverse excitation type converter 10 has increased magnetic-reset measuring ability (normally being realized by the auxiliary winding of transformer 101), so as in the time to detect that oscillating voltage touches the bottom actuating switch pipe M
1to realize no-voltage conducting (or low-voltage conducting), this will reduce switching loss, reduce EMI noise.
Figure 1B is the switching tube M in Figure 1A
1both end voltage V is leaked in source
dSwith respect to the oscillogram of time T.Switching tube M
1voltage V when conducting
dSbe 0, switching tube M
1voltage V has no progeny in pass
dSfor height, and after the energy release in the secondary winding of transformer 101 is complete (being that transformer flux resets completely), at switching tube M
1drain electrode there is sine-wave oscillation voltage, the trough as shown in Figure 1B and crest.Quasi-resonance inverse excitation type converter 10 has magnetic-reset measuring ability, so as in the time to detect that oscillating voltage touches the bottom (for example, time t1 and t2) actuating switch pipe M
1to realize no-voltage conducting, i.e. the lowest point conducting.
Fig. 1 C is the Organization Chart of the controller 100 of traditional quasi-resonance inverse excitation type converter.Controller 100 can comprise zero passage detection comparator 103, timer 104, with door 106, driving pulse generation module 107 and driver module 108.Zero passage detection comparator 103 for detection of the magnetic-reset (DEM signal) of transformer 101 thus in the time the lowest point of oscillating voltage being detected, export the lowest point detection signal ZCD.Timer 104, for frequency limitation, with at timer time inner shield the lowest point detection signal ZCD, prevents that self-excitation (free-running) frequency from exceeding the upper limit.Frequency limitation value is fixed as 125kHz conventionally, i.e. timer time 8 μ s, thus frequency is remained under the 150kHz starting point frequency of CISPR-22EMI standard.Only have after the lowest point detection signal ZCD that zero passage detection comparator 103 is exported appears at the timer time of timer 104, just export index signal to driving pulse generation module 107 with door 106.In one embodiment, driving pulse generation module 107 can be realized with rest-set flip-flop 107, and driving pulse generation module 107 sends triggering signal in the situation that S termination is received index signal, drives signal Drv actuating switch pipe M so that driver module 108 produces
1.On the other hand, driving pulse generation module 107 (for example,, in the time that the output voltage/electric current of transformer 101 exceedes threshold value) in the situation that R termination is received effective PWM COMP signal produces driver module 108 and drives signal Drv on-off switching tube M
1.
Under quasi-resonance mode of operation, when detecting the lowest point and timer 104, zero passage detection comparator 103 finishes timing, export index signal to driving pulse generation module 107 with door 106, it sends driver module 108 and drives signal Drv actuating switch pipe M
1.If at the timer time of timer 104, (for example, s) there is the lowest point in time window in 8 μ, can not overturn with door 106, thereby not allow actuating switch pipe M
1, zero passage detection comparator 103 can continue to detect the lowest point below.In the time of low input and high output loading, the degaussing time of transformer 101 is longer, can exceed 8 μ s, thereby controller 100 will be at first the lowest point (its appear at timer time finish after) actuating switch pipe M
1.But, along with power demand reduces, the degaussing time shorten of transformer 101, and when degaussing time shorten is during extremely lower than 8 μ s, frequency is just by clamper.In this case, at timer time, (the lowest point for example, detecting in 8 μ time window s) can conductively-closed, i.e. switching tube M
1remain on off state, and controller 100 is by the lowest point actuating switch pipe M after exceeding 8 μ s
1.
Fig. 1 D is the switching tube M of traditional quasi-resonance inverse excitation type converter 10 of comprising the controller 100 shown in Fig. 1 C
1both end voltage V is leaked in source
dSoscillogram.The power output of quasi-resonance inverse excitation type converter 10 likely makes the required switching tube M of Cycle by Cycle energy balance
1oN time drops between two contiguous the lowest point, for example, in a switch periods, detect that the time of first the lowest point is just above 8 μ s shielding times, and controller 100 is at first the lowest point actuating switch pipe M
1(for example, time t1, t3); Several all after dates, first the lowest point in the cycle of following is dropped in 8 μ s shielding times and is left in the basket, 100 of controllers after second the lowest point actuating switch pipe M
1(for example, time t2, t4).Controller 100 is by the switch periods work to differ in size like this, and longer switch periods can be compensated by shorter switch periods, and vice versa.So-called the lowest point frequency hopping that Here it is, the lowest point frequency hopping phenomenon makes switching frequency produce great changes, and this variation meeting quilt greatly peak current saltus step compensates, and current-jump causes producing audible noise in transformer 101.
Utility model content
For the technical problem that has the lowest point frequency hopping phenomenon in prior art, the utility model provides a kind of quasi-resonance inverse excitation type converter and controller thereof, can effectively reduce or avoid the lowest point frequency hopping phenomenon.
In one embodiment, a kind of controller for quasi-resonance inverse excitation type converter is provided, described quasi-resonance inverse excitation type converter comprises the power supply of switching tube with control inputs voltage, described controller comprises: zero passage detection comparator, and it detects described quasi-resonance inverse excitation type converter and closes the oscillating voltage of the generation of having no progeny and in the time the lowest point of described oscillating voltage being detected, produce the lowest point detection signal at described switching tube; The lowest point locking logical circuit, its output that is connected to described zero passage detection comparator to be to receive described the lowest point detection signal, and described the lowest point detection signal is carried out to the lowest point counting to send effective the lowest point signal in the time there is selected the lowest point; And driving pulse generation module, it is coupled to the output of described the lowest point locking logical circuit and sends triggering signal with switching tube described in conducting under the indication of described effective the lowest point signal.
In one embodiment, described controller also comprises: timer, and it is to carrying out timing and allowing signal in the described time cycle to after date output for the time cycle of highest frequency restriction; Gate circuit, it is connected to described the lowest point locking logical circuit and described timer, and export index signal in the time receiving the permission signal of effective the lowest point signal that described the lowest point locking logical circuit sends and the output of described timer, described driving pulse generation module sends described triggering signal in response to receiving described index signal; And driver module, its output that is connected to described driving pulse generation module is with the triggering signal that receives described driving pulse generation module and send and produce and drive signal with switching tube described in conducting.
In one embodiment, described the lowest point locking logical circuit comprises: the lowest point logical circuit of counter circuit, and it is connected to described zero passage detection comparator with the lowest point locking signal that receives described the lowest point detection signal and a selected the lowest point of indication is counted to export in the lowest point in each switch periods to described the lowest point detection signal; And the lowest point mask logic circuit, it is connected to described zero passage detection comparator and described the lowest point logical circuit of counter circuit to receive described the lowest point detection signal and described the lowest point locking signal, and sends described effective the lowest point signal in the time of the described selected the lowest point detecting in the detection signal of described the lowest point.
In one embodiment, described the lowest point locking logical circuit also comprises: the lowest point counting replacement logical circuit, its be connected to the output of described the lowest point mask logic circuit and in the time that described the lowest point mask logic circuit is not exported effective the lowest point signal in a switch periods, provide reset signal to described the lowest point logical circuit of counter circuit to reselect a new selected the lowest point.
In one embodiment, described the lowest point locking logical circuit also comprises: the lowest point counting replacement logical circuit, it is connected to the output of described the lowest point mask logic circuit and in the time that described the lowest point mask logic circuit is not exported effective the lowest point signal in a switch periods, provides reset signal to described the lowest point logical circuit of counter circuit so that described the lowest point logical circuit of counter circuit selects the previous the lowest point of described selected the lowest point as new selected the lowest point.
In one embodiment, described gate circuit is and door that it exports described index signal in the time receiving described effective the lowest point signal and described permission signal.
In one embodiment, described driving pulse generation module is rest-set flip-flop.
In one embodiment, an input of described rest-set flip-flop be connected to the output of described gate circuit and lower limit frequency both, and in the time receiving the described index signal of described gate circuit or described lower limit frequency switching tube described in conducting.
In one embodiment, another input of described rest-set flip-flop receives the pulse-modulated signal of indicating the output voltage/electric current of described quasi-resonance inverse excitation type converter whether to exceed threshold value, and described rest-set flip-flop turn-offs described switching tube in the time that the output voltage/electric current that receives the described quasi-resonance inverse excitation type converter of indication exceedes the pulse-modulated signal of threshold value.
In one embodiment, described selected the lowest point is N the lowest point in a switch periods, and wherein N is positive integer.
In one embodiment, provide a kind of quasi-resonance inverse excitation type converter, it comprises controller as above.
In one embodiment, described quasi-resonance inverse excitation type converter also comprises: transformer, it converts input voltage to output voltage, and described switching tube is coupled to described transformer to control the power supply of described input voltage to described transformer.
In one embodiment, described transformer comprises: auxiliary winding, described zero passage detection comparator is connected to described auxiliary winding to detect the described oscillating voltage on described auxiliary winding and produce the lowest point detection signal in the time the lowest point of described oscillating voltage being detected.
The utility model has solved the deficiencies in the prior art, and a kind of quasi-resonance inverse excitation type converter with the lowest point lock function is provided.By increasing the function of the lowest point locking, once controller is selected in certain the lowest point actuating switch pipe M
1, just can remain locked in this lowest point actuating switch pipe M
1.For example, and in the time that power output significantly changes, increased power is when this lowest point cannot be detected, controller can be subject to the control of lower limit frequency, actuating switch pipe M
1, and reselect and be locked in previous the lowest point actuating switch pipe M in the next cycle
1; Or next the lowest point can be selected and be locked in to power reduction when making this lowest point drop in the shielding time.Owing to being substantially locked in fixing the lowest point actuating switch pipe M
1, can not there is not again the phenomenon of the lowest point frequency hopping, the audible noise while having avoided the lowest point frequency hopping.
Accompanying drawing explanation
Figure 1A is the schematic diagram of quasi-resonance inverse excitation type converter.
Figure 1B is the oscillogram that both end voltage is leaked in the switching tube source in quasi-resonance inverse excitation type converter.
Fig. 1 C is the inner bay composition of the controller of traditional quasi-resonance inverse excitation type converter.
Fig. 1 D is the oscillogram that both end voltage is leaked in the switching tube source of traditional quasi-resonance inverse excitation type converter.
Fig. 2 A is according to the inner bay composition of the controller of the quasi-resonance inverse excitation type converter of the utility model one embodiment.
Fig. 2 B is according to the specific implementation schematic diagram of the lowest point locking logical circuit of the utility model one embodiment.
Fig. 2 C is the oscillogram of leaking both end voltage according to the switching tube source of the quasi-resonance inverse excitation type converter of the utility model one embodiment.
Fig. 3 is according to the specific implementation schematic diagram of the lowest point locking logical circuit of the 3rd the lowest point of control locking of the utility model one embodiment.
Embodiment
Below in conjunction with specific embodiments and the drawings, the utility model is described in further detail, but should not limit protection range of the present utility model with this.For ease of understanding, specific implementation and application with the quasi-resonance technology that increased the lowest point locking logic in quasi-resonance control are analyzed.
Fig. 2 A is according to the inner bay composition of the controller 200 of the quasi-resonance inverse excitation type converter of the utility model one embodiment.Controller 200 can be applied to quasi-resonance inverse excitation type converter as shown in Figure 1A and replace the controller 100 shown in Figure 1A.It will be understood by those skilled in the art that controller 200 can be applicable to other forms of quasi-resonance inverse excitation type converter, and be not limited to the embodiment shown in Figure 1A.For ease of understanding, be described below with reference to Figure 1A and Fig. 2 A.
In one embodiment, this effective the lowest point signal ACT sends driver module 208 via driving pulse generation module 207 and drives signal Drv actuating switch pipe M
1.In another embodiment as shown in Figure 2 A, the lowest point locking logical circuit 500 and timer 2 04 are connected to the input of gate circuit 206, and the output of gate circuit 206 is connected to driving pulse generation module 207.Timer 2 04 is to carrying out timing and allowing signal to gate circuit 206 in this time cycle to after date output for the time cycle (being timer time) of highest frequency restriction.That is, in timer time, gate circuit 206 shields effective the lowest point signal ACT, thereby prevents that self-excitation (free-running) frequency from exceeding the upper limit.Highest frequency limits value is fixed as 125kHz conventionally, and corresponding timer time can setting-up time be 8 μ s, but the utility model is not limited to this and can be suitable for as required other highest frequency restrictions.Only have after effective the lowest point signal ACT that locking logical circuit 500 in the lowest point is exported appears at the timer time of timer 2 04 (timer 2 04 output allow signal to gate circuit 206 after), gate circuit 206 is just exported index signal to driving pulse generation module 207.For example, gate circuit 206 can be and door that it just exports described index signal in the time that two inputs are all useful signal.In other are realized, gate circuit 206 can be realized by other gate.
Driving pulse generation module 207 can be realized with rest-set flip-flop 207 or other triggering logical circuits, driving pulse generation module 207 sends triggering signal to driver module 208 in the situation that S termination is received from gate circuit 206 index signal, and driver module 208 and then generation drive signal Drv with actuating switch pipe M
1.In addition, driving pulse generation module 207 is also received the pulse-modulated signal (PWM COMP) of indicating the output voltage/electric current of quasi-resonance inverse excitation type converter 10 whether to exceed threshold value in R termination, and the pulse-modulated signal that exceedes threshold value in the output voltage/electric current that receives indication quasi-resonance inverse excitation type converter 10 (for example, the effective PWM COMP of high level) time send triggering signal to driver module 208, driver module 208 and then produce and drive signal Drv with on-off switching tube M
1.
Once the lowest point locking logical circuit 500 is selected in certain the lowest point actuating switch pipe M
1, locking logical circuit 500 in the lowest point remains locked in this selected the lowest point, and sends effective the lowest point signal ACT with actuating switch pipe M this selected the lowest point detected in each switch periods time
1.When power output significantly changes, for example, when in the time of high output loading, the degaussing time of transformer 101 is grown (increased power) and makes this selected the lowest point to be detected or when in the time of low output loading, the degaussing time of transformer 101 shorter (power reduction) makes this selected the lowest point drop in the shielding time of timer 2 04, the lowest point locking logical circuit 500 can not exported effective the lowest point signal ACT, and driving pulse generation module 207 can be subject to lower limit frequency f so
lowcontrol.For example, driving pulse generation module 207 can be rest-set flip-flop, and an input (for example, S input) of this rest-set flip-flop is connected to output and the lower limit frequency f of gate circuit 206
lowboth, thus when in a switch periods, do not receive from gate circuit 206 index signal time according to lower limit frequency f
lowcarry out actuating switch pipe M
1, this Time Controller 200 is operated in fixing lower limit frequency f
low.If this thing happens, the lowest point locking logical circuit 500 will reselect the lowest point that will lock in the next cycle.For example, if increased power is when this selected the lowest point cannot be detected, locking logical circuit 500 in the lowest point can select to be locked in previous the lowest point actuating switch pipe M
1; If power reduction drops in shielding time of timer 2 04 during to this selected the lowest point, the lowest point locking logical circuit 500 selects to be locked in next the lowest point actuating switch pipe M
1.
The controller 200 of the quasi-resonance inverse excitation type converter shown in Fig. 2 A is compared Figure 1B has increased the lowest point locking logical circuit 500, because it is locked in fixing the lowest point actuating switch pipe M substantially
1, reduced or eliminated the phenomenon that occurs the lowest point frequency hopping, the audible noise while effectively having avoided the lowest point frequency hopping.
Fig. 2 B is according to the specific implementation schematic diagram of the lowest point locking logical circuit 500 of the utility model one embodiment, and it comprises the lowest point logical circuit of counter circuit 501, the lowest point mask logic circuit 502 and the lowest point counting replacement logical circuit 503.The lowest point logical circuit of counter circuit 501 for example receives the lowest point detection signal ZCD(that exported by zero passage detection comparator 203, its high level burst pulse represents that the lowest point appears in oscillating voltage), and the high level burst pulse in each switch periods is counted to the lowest point detection signal ZCD, judge and the number of the lowest point in each switch periods, detected and be chosen in which the lowest point (for example, N the lowest point) actuating switch pipe M
1.The lowest point logical circuit of counter circuit 501 is exported the lowest point locking signal K
n-1to the lowest point mask logic circuit 502, fix on N the lowest point actuating switch pipe M with indicating lock
1.Select the selected the lowest point that will lock, the lowest point locking signal K that the lowest point logical circuit of counter circuit 501 is exported once it should be noted that the lowest point logical circuit of counter circuit 501
n-1in follow-up switch periods, be locked as determined selected the lowest point, need until this selected the lowest point is invalid to reset.
The lowest point mask logic circuit 502 receives the lowest point locking signal K that the lowest point logical circuit of counter circuit 501 is exported
n-1and from the lowest point detection signal ZCD of zero passage detection comparator 203, and for example, when detecting that this selected the lowest point in the detection signal ZCD of the lowest point (, N the lowest point) time export effective the lowest point signal ACT, and before this selected the lowest point and the lowest point be left in the basket (shielding) occurring afterwards.The lowest point locking signal K that, the lowest point logical circuit of counter circuit 501 is exported
n-1make the lowest point mask logic circuit 502 by front N-1 the high level burst pulse shielding of the lowest point detection signal ZCD of input, only under the triggering of N burst pulse control signal, send effective the lowest point signal ACT with control switch pipe M
1conducting, realizes controller 500 and is locked in N the lowest point conducting.
The lowest point counting replacement logical circuit 503 detects effective the lowest point signal ACT of the lowest point mask logic circuit 502 final outputs.In the time that the lowest point logical circuit of counter circuit 501 is selected in N the lowest point conducting, if power output increases, make does not have N the lowest point in fixing switch periods, and N-1 the lowest point conductively-closed before, the lowest point mask logic circuit 502 can not exported effective the lowest point signal ACT in this switch periods, the output that is the lowest point mask logic circuit 502 maintains low level " 0 ", in this switch periods, there will be the situation that there is no the lowest point conducting.In addition, if power output reduces, while making effective the lowest point signal ACT drop within time cycle (being the timer time of timer 2 04) of highest frequency restriction, this effective the lowest point signal ACT also can be shielded by gate circuit 206, in this switch periods, also there will be the situation that there is no the lowest point conducting.As mentioned above, in the situation that there is no the lowest point conducting, driving pulse generation module 207 can be according to lower limit frequency f
lowcarry out actuating switch pipe M
1, therefore can not affect the operation of controller 500.In addition, if the lowest point counting replacement logical circuit 503 does not detect effective the lowest point signal ACT in a switch periods, exporting reset signal Reset makes it reselect a new selected the lowest point (for example, N-1 the lowest point) and is locked in this new the lowest point actuating switch pipe M to the lowest point logical circuit of counter circuit 501
1.Further, in the time that the selected the lowest point in the detection signal ZCD of the lowest point is dropped within time cycle of highest frequency restriction, the lowest point logical circuit of counter circuit 501 reselects a rear the lowest point of this selected the lowest point as new selected the lowest point.
Fig. 2 C is according to the switching tube M of the quasi-resonance inverse excitation type converter of the utility model one embodiment
1both end voltage V is leaked in source
dSoscillogram.As shown in the figure, the controller lock of this quasi-resonance inverse excitation type converter fixes on second the lowest point actuating switch pipe M
1thereby, avoided the lowest point saltus step.
Fig. 3 is according to the specific implementation schematic diagram of the lowest point locking logical circuit 500 of the 3rd the lowest point of control locking of the utility model one embodiment.
The lowest point logical circuit of counter circuit 501 receives the lowest point detection signal ZCD being exported by zero passage detection comparator 203 and is chosen in which the lowest point (for example, N the lowest point) actuating switch pipe M
1.The lowest point logical circuit of counter circuit 501 is exported the lowest point locking signal K
n-1to the lowest point mask logic circuit 502, fix on N the lowest point actuating switch pipe M with indicating lock
1.In the time that power output is higher, the 101 demagnetization times of transformer are longer, and the lowest point logical circuit of counter circuit 501 is selected in first the lowest point actuating switch pipe M substantially
1, the number that the lowest point detected in this cycle is 1, and this logic output K1 is low level " 0 ", and K2 is low level " 0 ".In the time that power output reduces, the demagnetization time of transformer 101 shortens, and when degaussing time shorten is when lower than 8 μ s, frequency is just by clamper.In this case, the lowest point meeting conductively-closed detecting in 8 μ s time windows, makes switching tube M
1remain on blocking state, therefore the lowest point logical circuit of counter circuit 501 will be chosen in second the lowest point (it will exceed s) actuating switch pipe M of 8 μ
1.Once the lowest point logical circuit of counter circuit 501 is selected in second the lowest point actuating switch pipe M
1, the lowest point number detecting in this cycle is 2, and logic output K1 is high level " 1 ", and K2 is low level " 0 ", and output K1 is locked in to high level " 1 ".In the time that power output continues to reduce, second the lowest point also can be shielded by the shielding time of 8 μ s, and the lowest point logical circuit of counter circuit 501 will the 3rd the lowest point, (it exceedes s) actuating switch pipe M of 8 μ
1once the lowest point logical circuit of counter circuit 501 is selected in the 3rd the lowest point actuating switch pipe M
1, the lowest point number detecting in this cycle is 3, and this logic output K1 is low level " 0 ", and K2 is high level " 1 ", and output K2 is locked in to high level " 1 ".When being shielded the lowest point logical circuit of counter circuit 501 by the shielding time of 8 μ s, the 3rd the lowest point will exceed the lowest point actuating switch pipe M of 8 μ s
1, the lowest point conducting below can no longer lock control.
The lowest point mask logic circuit 502 receives the lowest point locking signal K1, K2 that the lowest point logical circuit of counter circuit 501 exports and the lowest point detection signal ZCD from zero passage detection comparator 203, and for example, when detecting that this selected the lowest point in the detection signal of the lowest point (, N the lowest point) time export effective the lowest point signal ACT, and before this selected the lowest point and the lowest point be left in the basket (shielding) occurring afterwards.When K1 is " 0 " and K2 during for " 0 ", carry out conducting in first the lowest point, the lowest point mask logic circuit 502 is not carried out shielding processing to the lowest point detection signal ZCD of input, and effective the lowest point signal ACT of its output is identical with the lowest point detection signal ZCD of input.When K1 is " 1 " and K2 during for " 0 ", the lowest point mask logic circuit 502 can be by first burst pulse shielding of the lowest point detection signal ZCD of input, and effective the lowest point signal ACT of output only exports high level narrow pulse signal, control switch pipe M in the time of the 2nd the lowest point
1conducting.When K1 is " 0 " and K2 during for " 1 ", the lowest point mask logic circuit 502 can be by the first two burst pulse shielding of the lowest point detection signal ZCD of input, and effective the lowest point signal ACT of output only exports high level narrow pulse signal, control switch pipe M in the time of the 3rd the lowest point
1conducting.
The lowest point counting replacement logical circuit 503 detects effective the lowest point signal ACT of the lowest point mask logic circuit 502 final outputs.In the time that the lowest point logical circuit of counter circuit 501 is selected in the 3rd the lowest point conducting, now K1 is locked as " 0 " and K2 is locked as " 1 ", if power output increases, the 3rd the lowest point in fixing switch periods, do not detected, and two the lowest point conductively-closeds before, in this switch periods, can not export effective the lowest point signal ACT, i.e. the output of the lowest point mask logic circuit 502 maintains low level " 0 ", in this switch periods, there will be the situation that there is no the lowest point conducting.The lowest point counting replacement logical circuit 503 detects in a switch periods there is no the lowest point conducting, exports reset signal Reset and makes its replacement K1 for " 1 " and K2 are " 0 " to the lowest point logical circuit of counter circuit 501, carries out conducting second the lowest point.
In the time that the lowest point logical circuit of counter circuit 501 is selected in second the lowest point conducting, now K1 is locked as " 1 " and K2 is locked as " 0 ", if power output increases, second the lowest point in fixing switch periods, do not detected, an and the lowest point conductively-closed before, in this switch periods, can not export effective the lowest point signal ACT, i.e. the output of the lowest point mask logic circuit 502 maintains low level " 0 ", in this switch periods, there will be the situation that there is no the lowest point conducting.The lowest point counting replacement logical circuit 503 detects in a switch periods there is no the lowest point conducting, exports reset signal Reset and makes its replacement K1 for " 0 " and K2 are " 0 " to the lowest point logical circuit of counter circuit 501, carries out conducting in first the lowest point.
As mentioned above, in the utility model, the lowest point locking logical circuit 500 is by carrying out the lowest point counting to the lowest point detection signal ZCD and being selected in N the lowest point actuating switch pipe M
1, remain locked in N the lowest point actuating switch pipe M simultaneously
1, effectively reduce or avoided the lowest point frequency hopping.When power output significantly changes, for example, when increased power is when this lowest point cannot be detected, can reselect and be locked in N-1 the lowest point actuating switch pipe M
1; Or in the time that power reduction drops in the shielding time to this lowest point, can select and be locked in N+1 the lowest point actuating switch pipe M
1.Controller 500, under different power output conditions, can be locked in certain fixing the lowest point actuating switch pipe M like this
1, can not there is not again the phenomenon of the lowest point frequency hopping, the audible noise while having avoided the lowest point frequency hopping.For example, locking logical circuit 500 in the lowest point generally can be locked in second the lowest point (or the 3rd the lowest point) actuating switch pipe M
1, until power output significantly changes.In fact, the number of the lowest point that can lock is more, logic is more complicated, in the time there is more the lowest point, now power output reduces, and peak current diminishes relatively, although there will be the lowest point frequency hopping, but very I is to ignore for the noise that now can listen, and therefore only control locks front 3 the lowest point or front 4 the lowest point conventionally.
By reference to the accompanying drawings embodiment of the present utility model is described above; but the utility model is not limited to above-mentioned embodiment; above-mentioned embodiment is only schematic; rather than restrictive; those of ordinary skill in the art is under enlightenment of the present utility model; not departing from the scope situation that the utility model aim and claim protect, also can make a lot of forms, within these all belong to protection range of the present utility model.
Claims (13)
1. for a controller for quasi-resonance inverse excitation type converter, described quasi-resonance inverse excitation type converter comprises the power supply of switching tube with control inputs voltage, it is characterized in that, described controller comprises:
Zero passage detection comparator, it detects described quasi-resonance inverse excitation type converter and closes the oscillating voltage of the generation of having no progeny and in the time the lowest point of described oscillating voltage being detected, produce the lowest point detection signal at described switching tube;
The lowest point locking logical circuit, its output that is connected to described zero passage detection comparator to be to receive described the lowest point detection signal, and described the lowest point detection signal is carried out to the lowest point counting to send effective the lowest point signal in the time there is selected the lowest point; And
Driving pulse generation module, it is coupled to the output of described the lowest point locking logical circuit and sends triggering signal with switching tube described in conducting under the indication of described effective the lowest point signal.
2. the controller for quasi-resonance inverse excitation type converter as claimed in claim 1, is characterized in that, described controller also comprises:
Timer, it is to carrying out timing and allowing signal in the described time cycle to after date output for the time cycle of highest frequency restriction;
Gate circuit, it is connected to described the lowest point locking logical circuit and described timer, and export index signal in the time receiving the permission signal of effective the lowest point signal that described the lowest point locking logical circuit sends and the output of described timer, described driving pulse generation module sends described triggering signal in response to receiving described index signal; And
Driver module, its output that is connected to described driving pulse generation module is with the triggering signal that receives described driving pulse generation module and send and produce and drive signal with switching tube described in conducting.
3. the controller for quasi-resonance inverse excitation type converter as claimed in claim 1, is characterized in that, described the lowest point locking logical circuit comprises:
The lowest point logical circuit of counter circuit, it is connected to described zero passage detection comparator with the lowest point locking signal that receives described the lowest point detection signal and a selected the lowest point of indication is counted to export in the lowest point in each switch periods to described the lowest point detection signal; And
The lowest point mask logic circuit, it is connected to described zero passage detection comparator and described the lowest point logical circuit of counter circuit to receive described the lowest point detection signal and described the lowest point locking signal, and sends described effective the lowest point signal in the time of the described selected the lowest point detecting in the detection signal of described the lowest point.
4. the controller for quasi-resonance inverse excitation type converter as claimed in claim 3, is characterized in that, described the lowest point locking logical circuit also comprises:
The lowest point counting replacement logical circuit, its be connected to the output of described the lowest point mask logic circuit and in the time that described the lowest point mask logic circuit is not exported effective the lowest point signal in a switch periods, provide reset signal to described the lowest point logical circuit of counter circuit to reselect a new selected the lowest point.
5. the controller for quasi-resonance inverse excitation type converter as claimed in claim 3, is characterized in that, described the lowest point locking logical circuit also comprises:
The lowest point counting replacement logical circuit, it is connected to the output of described the lowest point mask logic circuit and in the time that described the lowest point mask logic circuit is not exported effective the lowest point signal in a switch periods, provides reset signal to described the lowest point logical circuit of counter circuit so that described the lowest point logical circuit of counter circuit selects the previous the lowest point of described selected the lowest point as new selected the lowest point.
6. the controller for quasi-resonance inverse excitation type converter as claimed in claim 2, is characterized in that, described gate circuit is and door that it exports described index signal in the time receiving described effective the lowest point signal and described permission signal.
7. the controller for quasi-resonance inverse excitation type converter as claimed in claim 2, is characterized in that, described driving pulse generation module is rest-set flip-flop.
8. the controller for quasi-resonance inverse excitation type converter as claimed in claim 7, it is characterized in that, an input of described rest-set flip-flop be connected to the output of described gate circuit and lower limit frequency both, and in the time receiving the described index signal of described gate circuit or described lower limit frequency switching tube described in conducting.
9. the controller for quasi-resonance inverse excitation type converter as claimed in claim 8, it is characterized in that, another input of described rest-set flip-flop receives the pulse-modulated signal of indicating the output voltage/electric current of described quasi-resonance inverse excitation type converter whether to exceed threshold value, and described rest-set flip-flop turn-offs described switching tube in the time that the output voltage/electric current that receives the described quasi-resonance inverse excitation type converter of indication exceedes the pulse-modulated signal of threshold value.
10. the controller for quasi-resonance inverse excitation type converter as claimed in claim 1, is characterized in that, described selected the lowest point is N the lowest point in a switch periods, and wherein N is positive integer.
11. 1 kinds of quasi-resonance inverse excitation type converters, is characterized in that, comprise the controller as described in any one in claim 1-10.
12. quasi-resonance inverse excitation type converters as claimed in claim 11, is characterized in that, also comprise:
Transformer, it converts input voltage to output voltage, and described switching tube is coupled to described transformer to control the power supply of described input voltage to described transformer.
13. quasi-resonance inverse excitation type converters as claimed in claim 12, is characterized in that, described transformer comprises:
Auxiliary winding, described zero passage detection comparator is connected to described auxiliary winding to detect the described oscillating voltage on described auxiliary winding and produce the lowest point detection signal in the time the lowest point of described oscillating voltage being detected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201320892170.6U CN203645536U (en) | 2013-12-30 | 2013-12-30 | Quasi-resonance fly-back converter and controller thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320892170.6U CN203645536U (en) | 2013-12-30 | 2013-12-30 | Quasi-resonance fly-back converter and controller thereof |
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| CN203645536U true CN203645536U (en) | 2014-06-11 |
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| CN201320892170.6U Expired - Lifetime CN203645536U (en) | 2013-12-30 | 2013-12-30 | Quasi-resonance fly-back converter and controller thereof |
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| CN (1) | CN203645536U (en) |
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| CN113678359A (en) * | 2019-04-12 | 2021-11-19 | 斯兰纳亚洲有限公司 | Quasi-resonant auto-tuning controller |
| CN113765338A (en) * | 2020-06-02 | 2021-12-07 | 立锜科技股份有限公司 | Flyback type power conversion circuit and its conversion control circuit and control method |
| CN114649933A (en) * | 2020-12-17 | 2022-06-21 | 南京志行聚能科技有限责任公司 | Valley bottom locking system for switching power supply |
| CN114696626A (en) * | 2022-04-11 | 2022-07-01 | 上海南芯半导体科技股份有限公司 | Control circuit of flyback converter |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104066260A (en) * | 2014-07-17 | 2014-09-24 | 矽力杰半导体技术(杭州)有限公司 | LED detecting circuit, driving circuit and lighting system |
| CN104066260B (en) * | 2014-07-17 | 2016-08-24 | 矽力杰半导体技术(杭州)有限公司 | A kind of LED testing circuit and drive circuit and illuminator |
| CN113678359A (en) * | 2019-04-12 | 2021-11-19 | 斯兰纳亚洲有限公司 | Quasi-resonant auto-tuning controller |
| CN113765338A (en) * | 2020-06-02 | 2021-12-07 | 立锜科技股份有限公司 | Flyback type power conversion circuit and its conversion control circuit and control method |
| CN113765338B (en) * | 2020-06-02 | 2024-05-28 | 立锜科技股份有限公司 | Flyback power conversion circuit and conversion control circuit and control method thereof |
| CN112217379A (en) * | 2020-09-28 | 2021-01-12 | 杭州茂力半导体技术有限公司 | Staggered switching power supply and control circuit and control method thereof |
| CN112217379B (en) * | 2020-09-28 | 2021-11-23 | 杭州茂力半导体技术有限公司 | Staggered switching power supply and control circuit and control method thereof |
| CN114649933A (en) * | 2020-12-17 | 2022-06-21 | 南京志行聚能科技有限责任公司 | Valley bottom locking system for switching power supply |
| CN114696626A (en) * | 2022-04-11 | 2022-07-01 | 上海南芯半导体科技股份有限公司 | Control circuit of flyback converter |
| CN119891575A (en) * | 2024-12-24 | 2025-04-25 | 西安电子科技大学 | Single-tube quasi-resonance wireless charging zero-voltage switch and control method thereof |
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