CN203608273U - Time domain accumulator applied to TDI-CIS - Google Patents
Time domain accumulator applied to TDI-CIS Download PDFInfo
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Abstract
本实用新型涉及微电子学的模拟集成电路设计领域，为消除模拟域电路累加过程中的非理想效应，减小累加器电路的复杂度，降低整体电路的芯片面积和功耗，使累加器电路可应用在低功耗环境中，本实用新型采用的技术方案是，应用于TDI-CIS的时域累加器，包括像素阵列，还包括：采样保持开关S/H，采样开关Sn、VCDL压控延时线、PD相位检测电路、TDC电路、两个D触发器、三个反相器、计数器和寄存器；采用电路采样模拟电压信号和参考电压信号进行转换累加，转换累加的过程在时间域内完成，在完成预期累加级数之后由相位检测器完成累加时间的输出；随后计数器和TDC电路对此时间信号进行量化。本实用新型主要应用于模拟集成电路设计。
The utility model relates to the field of analog integrated circuit design of microelectronics. In order to eliminate the non-ideal effect in the accumulation process of analog domain circuits, reduce the complexity of the accumulator circuit, reduce the chip area and power consumption of the overall circuit, and make the accumulator circuit It can be applied in a low power consumption environment. The technical solution adopted by the utility model is that the time domain accumulator applied to TDI-CIS includes a pixel array, and also includes: sample and hold switch S/H, sample switch Sn, VCDL voltage control Delay line, PD phase detection circuit, TDC circuit, two D flip-flops, three inverters, counters and registers; use circuits to sample analog voltage signals and reference voltage signals for conversion and accumulation, and the process of conversion and accumulation is completed in the time domain , the output of the accumulation time is completed by the phase detector after the expected number of accumulation stages is completed; the counter and TDC circuit then quantize this time signal. The utility model is mainly applied to the design of analog integrated circuits.
Description
Technical field
The utility model relates to microelectronic analog integrated circuit design field, particularly a kind of time domain accumulator that is applied to TDI-CIS.
Background technology
TDI(Time Delay and Integration time delay integration) imaging technique is a kind of linear array scanning mode, its principle is for utilizing multistage pixel cell to carry out multiexposure, multiple exposure to same moving target, is equivalent to and extends light signal time of integration.It is cumulative that the TDI working method of existing CIS (CMOS Image Sensor cmos image sensor) is divided into analog domain cumulative sum numeric field.
Referring to Fig. 1, analog domain is cumulative is by integrator, the signal of each pixel output to be added up, cumulative is that the mode being added with analog signal is carried out, and finally the signal after cumulative is carried out to ADC (analog-to-digital conversion) and quantizes to obtain corresponding digital code system.Referring to Fig. 2, numeric field is cumulative is that the signal of each pixel output is directly carried out to ADC quantification, then in the mode of digital code, synchronizing signal is added up, and finally again the digital code after cumulative is added up to progression to be reduced to final Signal coding divided by TDI-CIS.
At least there is following shortcoming and defect in above-mentioned technology:
Analog domain accumulator circuit is made up of a large amount of electric capacity and switch and amplifier.The non-ideal factors such as capacitance mismatch, the electric leakage of switch subthreshold value, switching capacity KTC noise and amplifier imbalance all can affect precision and the speed of accumulator.Numeric field accumulator is had relatively high expectations for ADC's, and for the TDI-CIS circuit of the cumulative progression of height, summation circuit need to consume very large chip area.The technology of the above-mentioned non-ideal factor of existing solution all can increase the complexity of integrated circuit, and then causes the area of circuit and the increase of power consumption.
Summary of the invention
For overcoming the deficiencies in the prior art, the utility model is intended to eliminate the non-ideal effects in analog domain circuit cumulative process, reduce the complexity of accumulator circuit, reduce chip area and the power consumption of integrated circuit, accumulator circuit be can be applicable in low-power consumption environment, the technical solution adopted in the utility model is, be applied to the time domain accumulator of TDI-CIS, comprise pel array, also comprise: sampling maintained switch S/H, sampling switch Sn, VCDL voltage control delay line, PD phase detecting circuit, TDC circuit, two d type flip flops, three inverters, counter and register,
Pixel array exposure signal is connected with sampling maintained switch S/H one end separately respectively with reset signal, and the other end of sampling maintained switch S/H is all connected with the control end of VCDL, and the size of analog signal determines the time of delay of VCDL; The output of VCDL is connected with the input of next stage VCDL, and two VCDL complete the cumulative of a time quantum, completes the cumulative cascade N VCDL that needs of N level; The output of the VCDL of afterbody is all connected with one end of sampling switch Sn, and sampling switch Sn is for having added up switch; The other end of Sn is connected with one end of PD phase detectors; PD phase detectors complete the output of cumulative time quantum.
The output of described PD phase detecting circuit is connected with the input of described TDC circuit, output low level significance bit; The output of described PD phase detecting circuit is connected with the input of first d type flip flop, and the output of first d type flip flop is connected with the input of second d type flip flop, output control signal; The output of second d type flip flop is connected with the input of TDC and the input of register respectively, register output low level significance bit; Clock signal is connected with the input of first d type flip flop respectively, is connected with the input of counter, is connected with the input of an inverter, and the output of inverter is connected with the input of second d type flip flop; The output of counter is connected with the input of register.
TDC circuit is made up of some Q triggers, amplifier, decoder, and some amplifiers are connected in series successively, a corresponding Q trigger D end, the Q termination decoder of first Q trigger, second the Q trigger of connecting of output of each amplifier
termination decoder, all the other Q triggers the like, and the clock end of all Q triggers links together.
Be applied to the time domain accumulation method of TDI-CIS, realize by means of aforementioned accumulator, and comprise the steps: in the time of the time domain accumulator work that is applied to TDI-CIS, adopt circuit sampling analog voltage signal and reference voltage signal to change cumulative, change cumulative process and complete in time-domain, after completing the cumulative progression of expection, complete the output of cumulative time by phase detectors; Counter and TDC circuit quantize this time signal subsequently, thereby the deadline is to digital conversion.
The utility model possesses following technique effect:
The utility model embodiment provides a kind of time domain accumulator of the TDI-CIS of being applied to circuit, and analog voltage signal is converted into the time quantum operation that adds up, and completing after the cumulative progression of expectation, by TDC circuit, the time quantum finally obtaining is carried out to digital translation.It is voltage-operated that this cumulative process does not relate to analog domain, eliminated the non-ideal effects of analog domain circuit.In guaranteeing cumulative precision, the complexity that can reduce circuit makes it on domain, more be easy to realize, not only can complete CDS correlated-double-sampling, can further reduce power consumption simultaneously, and the speed of time domain circuit conversion is fast, the accumulator reading circuit making can be applicable in low-power consumption high velocity environment.Foregoing circuit and concrete implementation method, realized the quantification of analog signal added up, and met the needs in practical application.
Accompanying drawing explanation
Fig. 1 is the TDI-CIS analog domain summation circuit principle schematic that prior art provides;
Fig. 2 is the TDI-CIS numeric field summation circuit principle schematic that prior art provides;
Fig. 3 is the cumulative reading circuit principle schematic of TDI-CIS time domain that the utility model provides;
Fig. 4 is the circuit structure diagram of VCDL voltage control delay line;
Fig. 5 is sub-TDC circuit structure diagram;
Fig. 6 is cumulative time sequential routine figure;
In accompanying drawing, the list of parts of each label representative is as follows:
VCDL: voltage control delay line; S/H: sampling maintained switch;
The Sn:n level switch that added up; PD: phase detectors;
TDC: time-to-digit converter; MSBs: highest significant position; LSBs: least significant bit;
Vsig (nm): the capable m row of n pixel integration signal; Vrst (nm): the capable m row of n pixel reset signal.
Embodiment
Analog voltage signal is changed by the voltage-controlled delay unit of accumulator circuit, obtains the time residual quantity corresponding with analog voltage, and this time residual quantity that time residual quantity continues and next analog voltage is corresponding is added, and obtains cumulative time quantum.Completing after the cumulative progression of expectation, by TDC(Time Digital Converter time-to-digit converter) time quantum finally obtaining carries out digital translation by circuit.It is voltage-operated that this cumulative process does not relate to analog domain, eliminated the non-ideal effects of analog domain.In guaranteeing cumulative precision, in order to eliminate the non-ideal effects in analog domain circuit cumulative process, reduce the complexity of accumulator circuit, reduce chip area and the power consumption of integrated circuit, accumulator circuit be can be applicable in low-power consumption environment, and the utility model provides the time domain accumulator of a kind of TDI-CIS of being applied to.
Referring to Fig. 3, realize circuit and comprise: sampling maintained switch S/H, Sn, VCDL voltage control delay line, PD phase detecting circuit, TDC circuit, two d type flip flops, three inverters, counter and registers.
Pixel exposure signal is connected with sampling maintained switch S/H one end separately respectively with reset signal, and the other end of sampling maintained switch S/H is all connected with the control end of VCDL, and the circuit theory diagrams of VCDL are referring to Fig. 4.The size of analog signal determines the time of delay of VCDL.The output of VCDL is connected with the input of next stage VCDL, and two VCDL complete the cumulative of a time quantum, completes the cumulative cascade N VCDL that needs of N level.The output of the VCDL of afterbody is all connected with one end of sampling switch Sn, and Sn is for having added up switch.The other end of Sn is connected with one end of PD phase detectors.PD completes the output of cumulative time quantum.Concrete sequential operation is referring to Fig. 6.
The output of described PD phase detecting circuit is connected with the input of described TDC circuit, output low level significance bit, and the circuit theory diagrams of TDC are referring to Fig. 5; The output of described PD phase detecting circuit is connected with the input of first d type flip flop, and the output of first d type flip flop is connected with the input of second d type flip flop, output control signal; The output of second d type flip flop is connected with the input of TDC and the input of register respectively, register output low level significance bit; Clock signal is connected with the input of first trigger respectively, is connected with the input of counter, is connected with the input of an inverter, and the output of inverter is connected with the input of second d type flip flop; The output of counter is connected with the input of register.
Be applied to the time domain accumulator of TDI-CIS in the time of work, circuit sampling analog voltage signal and reference voltage signal are changed cumulative, change cumulative process and complete in time-domain, after completing the cumulative progression of expection, complete the output of cumulative time by phase detectors.Counter and TDC circuit quantize this time signal subsequently, thereby the deadline is to digital conversion.
For making the purpose of this utility model, technical scheme and advantage clearer, below in conjunction with accompanying drawing, the utility model execution mode is described in further detail.
With figure tri-, this figure method of work is described, described below:
M-numeral when this integrated circuit is divided into time in cumulative stage and T-D() translate phase composition.Time in the cumulative stage is completed by two groups of voltage controlled delay lines, and T-D conversion is completed by counter and TDC circuit.
One, time in the cumulative stage
Take the cumulative reading circuit of the line time in dotted line frame in circuit shown in figure tri-as example, sampling maintained switch S/H samples to pixel exposure signal Vsig and reset signal Vrst respectively, and these two kinds of signals are controlled respectively VCDL separately.There is time delay in the input of VCDL and the transmission of the signal of output, delay time is relevant with sampled signal magnitude.Two groups of VCDL transmission delays are respectively TVsigo=TVsigi+GVsig+b, TVrsto=TVrsti+GVrst+b.These two time delays residual quantity are Δ T=TVrsto-TVsigo=Δ TIN+G (Vrst-Vsig)=Δ TIN+G Δ VIN, have completed CDS correlated-double-sampling.First group of output signal Vsig(11) and Vrst (11) rising edge while simultaneously arriving, Δ TIN (1)=0.Second group of S/H carries out exposure signal Vsig(12 to pixel again) and reset signal Vrst(12) sampling, the signal of previous stage VCDL output enters the VCDL of the second level, and secondary Output rusults is Δ T (2)=TVrsto-TVsigo=Δ TIN (1)+G Δ VIN (2).Carry out successively, Output rusults is T (3)=TVrsto-TVsigo=Δ TIN (2)+G Δ VIN (3) for the third time.The N time Output rusults is T (N)=TVrsto-TVsigo=Δ TIN (N-1)+G Δ VIN (N).Complete after specific progression cumulative, Sn switch closure, transfers to subsequent conditioning circuit to be quantified as digital code value this time quantum output by PD phase detectors.In circuit shown in figure tri-, work as Vsig(18) and reset signal Vrst(18) to complete eight grades of times after sampling cumulative.Remaining row time accumulate mode is similar.
Two, T-D translate phase
After time in the cumulative stage completes, by the corresponding time pulse signal of the PD phase detectors specific cumulative progression of output.At the rising edge of time pulse signal, clk signal accesses the input of first d type flip flop, inverter sum counter.Counter starts to calculate clock pulse number simultaneously.The output of PD phase detectors accesses the input of sub-TDC, as the enabling signal of sub-TDC.The output of PD phase detectors accesses the input of first d type flip flop, as the enabling signal of inhibit signal.The output signal of inverter enters the input of second d type flip flop as clock pulse.The input of the output connexon TDC of second d type flip flop and the input of register, as stop signal and the register enabling signal of sub-TDC.The pulse number of register-stored counter, completes the high position data conversion of high-order time quantum.The low data conversion of sub-TDC output deadline amount.For specific reference clock, counter and sub-TDC complete each N bit data conversion.Obtain final 2N bit data.
Take a kind of time domain accumulator that is applied to TDI-CIS as example, analyze its operation principle below, described below:
Still describe as an example of a line time summation circuit example, referring to sequential schematic diagram shown in figure six.First group of S/H switch closure, Vsig (11) and Vrst (11) control respectively the pulse that voltage controlled delay line produces corresponding frequencies separately, and first group of S/H disconnects subsequently, obtains Δ T (11)=0.Next carry out cumulative process for the first time, second group of S/H closure, Vsig (12) and Vrst (12) control respectively the pulse of voltage controlled delay line generation corresponding frequencies, and second group of S/H disconnects again subsequently, obtains Δ T (2)=G Δ V (2).For the second time in cumulative process, the 3rd group of S/H closure, Vsig (13) and the pulse that Vrst(13) control voltage controlled delay line produces corresponding frequencies, the 3rd group of S/H disconnects again, obtains Δ T (3)=Δ T (2)+G Δ V (3).Carry out successively 8 grades and add up, suppose that the time obtaining after cumulative 8 grades is 106ns.This time quantum is exported by phase detectors and is changed by TDC.
T-D translate phase comprises high-order conversion and low level conversion.Clk frequency is 100MHz, and temporal resolution is 10ns.First the add up high position conversion of time quantum, 5 bit data conversions are carried out in high-order conversion, calculate clock pulse number by counter.106ns is by rolling counters forward, because temporal resolution is 10ns, 10*10=100ns, so amount to 10 integer pulses, the corresponding code value obtaining is 01010, this result store in register so that and low level transformation result be added.
Next carry out low level conversion, low level translate phase carries out 5 bit data conversions.Time after high-order translate phase remaining poor be 106-100=6ns, TDC circuit is poor conversion more than time to this.In TDC circuit, single reverser time delay is 1ns, enabling signal start delay chain, and stop signal, after the time of transmission 6ns, is recorded the state of each trigger, and exports 5 encoded radios by decoder.Digital code after remaining poor conversion of 6ns is 10011.The digital code that high-order translate phase and low level translate phase are obtained is directly added, and obtains 10 final digit numeric codes 101010011.
Visible, that the time domain accumulator that is applied to TDI-CIS has not only obviously promoted in guaranteeing precision is cumulative, conversion and reading speed, use multiple row share reading circuit structure in this advantage become more outstanding.
Claims (2)
1. one kind is applied to the time domain accumulator of TDI-CIS, comprise: pel array, it is characterized in that, also comprise: sampling maintained switch S/H, sampling switch Sn, VCDL voltage control delay line, PD phase detecting circuit, TDC circuit, two d type flip flops, three inverters, counter and registers;
Pixel array exposure signal is connected with sampling maintained switch S/H one end separately respectively with reset signal, and the other end of sampling maintained switch S/H is all connected with the control end of VCDL, and the size of analog signal determines the time of delay of VCDL; The output of VCDL is connected with the input of next stage VCDL, and two VCDL complete the cumulative of a time quantum, completes the cumulative cascade N VCDL that needs of N level; The output of the VCDL of afterbody is all connected with one end of sampling switch Sn, and sampling switch Sn is for having added up switch; The other end of Sn is connected with one end of PD phase detectors; PD phase detectors complete the output of cumulative time quantum;
The output of described PD phase detecting circuit is connected with the input of described TDC circuit, output low level significance bit; The output of described PD phase detecting circuit is connected with the input of first d type flip flop, and the output of first d type flip flop is connected with the input of second d type flip flop, output control signal; The output of second d type flip flop is connected with the input of TDC and the input of register respectively, register output low level significance bit; Clock signal is connected with the input of first d type flip flop respectively, is connected with the input of counter, is connected with the input of an inverter, and the output of inverter is connected with the input of second d type flip flop; The output of counter is connected with the input of register.
2. the time domain accumulator that is applied to TDI-CIS as claimed in claim 1, it is characterized in that, TDC circuit is made up of some Q triggers, amplifier, decoder, some amplifiers are connected in series successively, a corresponding Q trigger D end, the Q termination decoder of first Q trigger, the Q termination decoder of second Q trigger of connecting of output of each amplifier, all the other Q triggers the like, and the clock end of all Q triggers links together.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103546695A (en) * | 2013-10-18 | 2014-01-29 | 天津大学 | Time Domain Accumulation Method and Accumulator Applied to TDI-CIS |
| WO2016150182A1 (en) * | 2015-03-25 | 2016-09-29 | 华为技术有限公司 | Time-to-digital converter in phase-locked loop |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103546695A (en) * | 2013-10-18 | 2014-01-29 | 天津大学 | Time Domain Accumulation Method and Accumulator Applied to TDI-CIS |
| CN103546695B (en) * | 2013-10-18 | 2016-05-25 | 天津大学 | Be applied to time domain accumulation method and the accumulator of TDI-CIS |
| WO2016150182A1 (en) * | 2015-03-25 | 2016-09-29 | 华为技术有限公司 | Time-to-digital converter in phase-locked loop |
| US10673445B2 (en) | 2015-03-25 | 2020-06-02 | Huawei Technologies Co., Ltd. | Time-to-digital converter in phase-locked loop |
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