CN203519954U - Array substrate and display device - Google Patents
Array substrate and display device Download PDFInfo
- Publication number
- CN203519954U CN203519954U CN201320632830.7U CN201320632830U CN203519954U CN 203519954 U CN203519954 U CN 203519954U CN 201320632830 U CN201320632830 U CN 201320632830U CN 203519954 U CN203519954 U CN 203519954U
- Authority
- CN
- China
- Prior art keywords
- static electricity
- layer
- shield layer
- electricity shield
- array base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 90
- 230000003068 static effect Effects 0.000 claims abstract description 125
- 230000005611 electricity Effects 0.000 claims description 116
- 229910052751 metal Inorganic materials 0.000 claims description 50
- 239000002184 metal Substances 0.000 claims description 50
- 239000012528 membrane Substances 0.000 claims description 24
- 239000000463 material Substances 0.000 claims description 22
- 238000009413 insulation Methods 0.000 claims description 18
- 238000002161 passivation Methods 0.000 claims description 16
- 239000004033 plastic Substances 0.000 claims description 16
- 239000002245 particle Substances 0.000 claims description 13
- 239000010409 thin film Substances 0.000 claims description 10
- VYMDGNCVAMGZFE-UHFFFAOYSA-N phenylbutazonum Chemical compound O=C1C(CCCC)C(=O)N(C=2C=CC=CC=2)N1C1=CC=CC=C1 VYMDGNCVAMGZFE-UHFFFAOYSA-N 0.000 claims description 4
- 230000015556 catabolic process Effects 0.000 abstract description 8
- 230000007246 mechanism Effects 0.000 abstract description 3
- 230000035939 shock Effects 0.000 abstract 2
- 238000000034 method Methods 0.000 description 59
- 229920002120 photoresistant polymer Polymers 0.000 description 48
- 239000010408 film Substances 0.000 description 27
- 230000008569 process Effects 0.000 description 24
- 238000002360 preparation method Methods 0.000 description 17
- 239000004973 liquid crystal related substance Substances 0.000 description 14
- 239000000203 mixture Substances 0.000 description 13
- 238000011161 development Methods 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 6
- 230000008859 change Effects 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- 238000012360 testing method Methods 0.000 description 5
- 239000004020 conductor Substances 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 230000008020 evaporation Effects 0.000 description 4
- 238000001704 evaporation Methods 0.000 description 4
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical class [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 4
- 238000001755 magnetron sputter deposition Methods 0.000 description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 229910052804 chromium Inorganic materials 0.000 description 3
- 239000011651 chromium Substances 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000011159 matrix material Substances 0.000 description 3
- 229910052750 molybdenum Inorganic materials 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 229910001092 metal group alloy Inorganic materials 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005421 electrostatic potential Methods 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
Images
Landscapes
- Liquid Crystal (AREA)
Abstract
The utility model relates to the technical field of display, in particular to an array substrate and a display device with the array substrate used. The array substrate comprises a substrate body, the substrate body is provided with a plurality of pixel units and a driving circuit for driving the pixel units, the edge of the substrate body is further provided with a grounding lead and a first electrostatic protection layer electrically connected with the grounding lead. In the array substrate and the display device, through arrangement of the grounding lead and the first electrostatic protection layer, during static shock, electrostatic charge is discharged by utilizing the grounding lead and the first electrostatic protection layer, therefore, an effective static shock protection mechanism is formed, damage, caused by electrostatic breakdown, to the driving circuit is avoided, and the reliably of products is improved greatly.
Description
Technical field
The utility model relates to display technique field, the display device that is specifically related to a kind of array base palte and applies this array base palte.
Background technology
Panel display apparatus than traditional CRT display have frivolous, driving voltage is low, there is no the advantages such as flashing and long service life, wherein, liquid crystal indicator as a kind of panel display apparatus because it has that picture is stable, image fidelity, elimination radiation, save space and save the advantages such as energy consumption, be widely used in the electronic products such as TV, mobile phone, display device, occupied the leading position in plane demonstration field.
Liquid crystal indicator mainly comprises liquid crystal panel and Circuits System etc., and liquid crystal panel comprises array base palte and the color membrane substrates being oppositely arranged, and is provided with a plurality of pixel cells on array base palte, and Circuits System is for generation of the signal of controlling each pixel cell.
Each pixel cell in existing liquid crystal indicator generally includes a thin film transistor (TFT) TFT(Thin Film Transistor, thin film transistor (TFT)), the thin film transistor (TFT) of each pixel cell need to be connected with respective drive circuit, driving circuit is a part for Circuits System, is used to each TFT that driving signal is provided.
In order to reduce overall dimensions and the manufacturing cost of liquid crystal indicator, in prior art, part driving circuit normally directly can be produced on relatively simple gate driver circuit on array base palte, replace by external driving chip as driving circuit.This kind of set-up mode can reduce the volume of display device, and manufacture craft is simple, improves the size of liquid crystal indicator and reduces cost of manufacture.
The Electrostatic Protection Design of electronic product is to guarantee one of its essential condition that can normally work.Liquid crystal indicator in production, transportation, test and use procedure, face the static much bringing from plant equipment, human body or other electronic equipment as a kind of electronic product.Because the gate driver circuit wiring being formed on array base palte is intensive, exterior static can enter gate driver circuit by the gap between array base palte and color membrane substrates, thereby gate driver circuit is caused to damage.
In industry, the raising to the requirement of product electrostatic prevention due to client and ultimate consumer, prevents that electrostatic breakdown from having become important topic at present.For example, at a lot of liquid crystal indicators, such as mobile phone and other user terminals, all increased static and discharged ESD(Electro Static Discharge, static discharges) test, utilizes more than 2KV high pressure to carry out the antistatic capacity of test fluid crystal device.
Yet, although part liquid crystal indicator of the prior art has carried out the interpolation of shape and signal and has changed to prevent electrostatic breakdown, but under the Hi-pot test condition more than 2KV, the gate driver circuit damage still easily causing because of electrostatic breakdown, cause picture disply abnormal, even cannot normally work.
Utility model content
(1) technical matters that will solve
The purpose of this utility model is for the problems referred to above, and a kind of array base palte is provided, and this array base palte can carry out effective electrostatic defending to driving circuit disposed thereon, thus the reliability of improving product; Further, the utility model also provides a kind of display device of this array base palte of application.
(2) technical scheme
Technical solutions of the utility model are as follows:
A kind of array base palte, comprise underlay substrate, on described underlay substrate, be provided with some pixel cells and for driving the driving circuit of described pixel cell, the first static electricity shield layer that described underlay substrate edge is also provided with ground lead and is electrically connected to described ground lead.
Preferably, described the first static electricity shield layer covers described driving circuit top.
Preferably, described driving circuit comprises gate driver circuit, source electrode drive circuit and/or common electrode driving circuit.
Preferably, described pixel cell comprises thin film transistor (TFT); Described ground lead is identical with layer setting and material with gate metal layer or the source leakage metal level of described thin film transistor (TFT).
Preferably, described pixel cell also comprises gate insulation layer, passivation layer and the transparent electrode layer setting gradually, described the first static electricity shield layer is identical with layer setting and material with described transparent electrode layer, and described the first static electricity shield layer is electrically connected to described ground lead by the via hole on gate insulation layer and passivation layer.
The utility model also provides a kind of display device of applying above-mentioned any one array base palte, this display device, comprise above-mentioned any one array base palte and with described array base palte to box to box substrate.
Preferably, described to being provided with the second static electricity shield layer being electrically connected to described the first static electricity shield layer on box substrate, and described the second static electricity shield layer is corresponding with the position of described the first static electricity shield layer.
Preferably, described is color membrane substrates to box substrate.
Preferably, be also provided with flatness layer on described color membrane substrates, described the second static electricity shield layer is positioned at described flatness layer top.
Preferably, described the second static electricity shield layer is identical with described the first static electricity shield layer material and shape.
Preferably, described array base palte and described bonding by sealed plastic box to box substrate, and described sealed plastic box partly covers described the first static electricity shield layer, and the intra-zone that described sealed plastic box covers described the first static electricity shield layer is provided with conductive particle thing;
Described the first static electricity shield layer is electrically connected to by described conductive particle thing with described the second static electricity shield layer.
(3) beneficial effect
In array base palte and display device that the utility model provides, by ground lead and the first static electricity shield layer are set, when having electrostatic impact, utilize ground lead and the first static electricity shield layer that electrostatic charge is released, thereby form effective electrostatic impact preventing mechanism, avoid causing due to electrostatic breakdown the Key Circuit such as gate driver circuit to produce damage, promoted greatly the reliability of product.
Accompanying drawing explanation
Fig. 1 is the partial structurtes schematic diagram of array base palte in the utility model embodiment mono-;
Fig. 2 is the cross section structure schematic diagram of array base palte in A-B direction in Fig. 1;
Fig. 3 is the electrostatic leakage path schematic diagram of array base palte in Fig. 2;
Fig. 4 is the partial cross section structural representation of display device in the utility model embodiment bis-.
In figure: 10: array base palte; 11: gate driver circuit; 12: ground lead; 13: the second via holes; 14: the first static electricity shield layer; 21: gate insulation layer; 22: passivation layer; 24: transparent electrode layer; 31: color membrane substrates; 32: the second static electricity shield layer; 41: sealed plastic box; 42: conductive particle thing.
Embodiment
Below in conjunction with drawings and Examples, embodiment of the present utility model is described further.Following examples are only for the utility model is described, but are not used for limiting scope of the present utility model.
Array base palte provided by the utility model mainly comprises underlay substrate, the driving circuit that is provided with some pixel cells and is connected with described pixel cell on described underlay substrate, one of main improvement of the present utility model is, also be provided with the ground structure that described driving circuit is carried out to electrostatic defending, described ground structure comprises ground lead and the first static electricity shield layer being electrically connected to described ground lead; Described ground lead and the first static electricity shield layer are all arranged on the edge of underlay substrate.
In the present embodiment, utilize above-mentioned ground structure to carry out effective electrostatic impact protection to driving circuit, by ground lead and the first static electricity shield layer are set at array base palte edge, at electrostatic impact, come interim, that is to say when the outside electrostatic charge producing by array base palte and and it is when enter the gap between another substrate of box, first electrostatic charge can pass through first static electricity shield layer at edge, then by ground lead, lead away, and can not contact driving circuit, thereby can carry out electrostatic protection to driving circuit, avoid electrostatic breakdown driving circuit to cause its damage, therefore can promote the reliability of array base palte.
Above-mentioned ground lead and the first static electricity shield layer can adopt conductive material to make, for example, C r(chromium), Ti(titanium), Mo(molybdenum), Al(aluminium) or Cu(copper) etc. plain metal and metal alloy compositions thereof, can also be ITO(Indium Tin Oxides, indium tin oxide) or IZO(Indium Zinc Oxide, indium-zinc oxide) conductive material of transparent metal or its potpourri such as.
Preferably, shown in Fig. 3, the first static electricity shield layer 14 covers driving circuit 12 tops, certain the first static electricity shield layer 14 and described driving circuit 12 insulation, this kind of ground structure can form the package structure to driving circuit, further driving circuit is carried out to omnibearing protection, static is not easy to touch driving circuit 12 more, electrostatic charge is by direction shown in arrow in Fig. 3, by the first static electricity shield layer 14 and ground lead 12, derive, thereby further reduce the damage that electrostatic impact causes driving circuit, even when electrostatic potential is higher, for example, high pressure more than utilizing 2KV is to adopting the display device of this array base palte to carry out ESD when test, this kind of ground structure can be protected more reliably to driving circuit.
In above-described embodiment, the first static electricity shield layer also can be arranged on the close position of driving circuit, or depending on requirement section or all cover driving circuit, the shape of the first static electricity shield layer also can be for multiple, for example, quadrilateral, circle, ellipse or other are irregularly shaped, do not limit at this.The first static electricity shield layer also can be arranged to latticed, to play the object of saving material cost.
Below in conjunction with embodiment mono-and embodiment bis-, the utility model is described in more detail.
Embodiment mono-
In the present embodiment, array base palte mainly comprises underlay substrate, underlay substrate can be glass substrate, quartz base plate or other flexible base, boards etc., on underlay substrate, be provided with some pixel cells, each pixel cell generally includes a TFT, and TFT generally includes source electrode, grid and drain electrode etc., and each pixel cell can also comprise pixel electrode and public electrode touch-control electrode etc., in addition, touch-control electrode can also be set on array base palte.The TFT of each pixel cell need to be connected with respective drive circuit, is used to each TFT that driving signal is provided.
Above-mentioned driving circuit mainly comprises the driving circuits such as gate driver circuit, source electrode drive circuit, common electrode driving circuit and touch-control driving circuit, various driving circuits can adopt the technique of external chip to make, also can partly or entirely be arranged on array base palte, therefore, driving circuit described in the present embodiment can be in above-mentioned driving circuit any one or multiple, so long as be arranged on array base palte.
Wherein, gate driver circuit is for exporting sweep signal to the grid of TFT, source electrode drive circuit is for exporting data-signal to data line to offer the source electrode of TFT, common electrode driving circuit is for exporting common electric voltage to public electrode, and touch-control driving circuit is used to the display device with touch controllable function to provide touch-control to drive signal.
For convenience of description, shown in seeing figures.1.and.2, in the present embodiment, with widely used GOA(Gate Driver on Array, array base palte grid drives) technology, what on array base palte, arrange is that gate driver circuit is that example describes.
The first static electricity shield layer 14 that the underlay substrate edge of this array base palte is provided with ground lead 12 and is connected with ground lead 12, ground lead 12 is preferably the metal wire that conductive capability is stronger; The first static electricity shield layer 14 covers gate driver circuit 11 tops.
Pixel cell of the prior art generally includes: the gate metal layer (not shown) that comprises grid line and TFT grid setting gradually, for the gate insulation layer 21 to grid and active layer and the insulation of source-drain electrode metal interlevel, the active layer (not shown) that comprises TFT raceway groove, metal level (not shown) is leaked in the source that comprises data line and TFT source electrode and drain electrode, play insulation and the passivation layer 22 of smooth effect and comprise pixel electrode or the functional film layer such as the transparent electrode layer of public electrode 24.
Further preferred version is, the first above-mentioned static electricity shield layer 14 can be identical with layer setting and material with the transparent electrode layer 24 of pixel cell, and described the first static electricity shield layer 14 is electrically connected to described ground lead 12 by via hole; For example, when ground lead 12 arranges with layer with gate metal layer, by the via hole 13 on gate insulation layer 21 and passivation layer 22, be electrically connected to described ground lead 12.
So just can when forming transparent electrode layer 24, form the first static electricity shield layer 14, and, can when forming gate insulation layer and passivation layer, form via hole 13 simultaneously, to realize being electrically connected to of the first static electricity shield layer 14 and ground lead 12, and guarantee the insulation between the first static electricity shield layer and gate driver circuit.This kind of set-up mode can further reduce processing step, reduces technology difficulty, saves production cost.
Embodiment bis-
The utility model also provides a kind of display device of applying above-mentioned any one array base palte, this display device mainly comprise above-mentioned any one array base palte and with array base palte be oppositely arranged to box substrate.
This can be looked the difference of display device type to box substrate and be different; For example, in liquid crystal indicator, this can be color membrane substrates to box substrate, and is adopting Organic Light Emitting Diode OLED(Organic Light Emitting Diode, organic light emitting diode), in display device, this can be base plate for packaging etc. to box substrate.
Owing to being provided with the ground structure that comprises ground lead and the first static electricity shield layer on the applied array base palte of this display device, therefore can utilize ground structure to carry out effective electrostatic impact protection to the driving circuit being arranged on array base palte, thereby avoid electrostatic breakdown driving circuit to cause its damage, therefore can promote reliability and the quality of display device.
For convenience of description, the liquid crystal indicator of take in the present embodiment describes as example, meanwhile, select color membrane substrates as this liquid crystal indicator to box substrate.
In order further to strengthen the antistatic capacity of ground structure, shown in Fig. 4, in the present embodiment, also on color membrane substrates 31, be provided with the second static electricity shield layer 32(certain, the second static electricity shield layer also can be arranged on accordingly other types on box substrate), and described the second static electricity shield layer 32 is corresponding with the position of described the first static electricity shield layer 14, the first static electricity shield layer 14 is electrically connected to the second static electricity shield layer 32.
When electrostatic impact comes interim; by the second static electricity shield layer 32, the first static electricity shield layer 14 and 12 pairs of gate driver circuits of ground lead 11, form three-dimensional comprehensive electrostatic protection; exterior static cannot enter gate driver circuit 11 by the gap between array base palte 10 and color membrane substrates 31, thereby has avoided electrostatic impact to cause damage to gate driver circuit 11 completely.
The second static electricity shield layer 32 can be identical with the first static electricity shield layer 14 materials and shape, also can select according to the actual requirements the second static electricity shield layer of other materials or shape, at this, do not do particular determination.
Further, when described to box substrate, be on color membrane substrates, on color membrane substrates, be conventionally provided with flatness layer, described the second static electricity shield layer is positioned at described flatness layer top.
Because flatness layer is the outermost layer being positioned on color membrane substrates; and the second static electricity shield layer is positioned on flatness layer; therefore; this second static electricity shield layer is for being arranged at the outermost figure of color membrane substrates; like this by array base palte and color membrane substrates to box after, be convenient to the first electrostatic protection layer to be electrically connected to the second electrostatic protection layer.
Certainly, when box substrate is not color membrane substrates, the second static electricity shield layer also can not be arranged on flatness layer top, can be according to the concrete structure setting to box substrate; And, the second static electricity shield layer also can not be arranged on the outermost layer to box substrate, as long as realize being electrically connected to of the second static electricity shield layer and the first static electricity shield layer, for example, can conductive structure be set separately at array base palte and between to box substrate, utilize conductive structure structure to realize both electrical connections.
Preferred scheme is, shown in Fig. 4, because array base palte 10 is with to box substrate 31, employing sealed plastic box 41 is bonding conventionally, in order to realize being electrically connected between the first static electricity shield layer 14 and the second static electricity shield layer 32, can make sealed plastic box 41 parts cover described the first static electricity shield layer 14, the intra-zone that described sealed plastic box 41 covers described the first static electricity shield layer 14 is provided with conductive particle thing 42; Described the first static electricity shield layer 14 is electrically connected to by described conductive particle thing 42 with described the second static electricity shield layer 32.
The conductive particle thing 42 adding in sealed plastic box 41 can be skin be coated with the metals such as gold or nickel there is certain flexible spherical resin particle or other forms of conductive particle thing.
Certainly, also can in the position between the first static electricity shield layer 14 and the second static electricity shield layer 32, adopt conductive spacer by array base palte 10 and to the chock insulator matter arranging between box substrate 31, utilize conductive spacer to realize being electrically connected between the first static electricity shield layer 14 and the second static electricity shield layer 32, and conductive structure etc. needn't be set separately.
Above-mentioned display device can be: display panels, Electronic Paper, OLED display panel, LCD TV, liquid crystal display, digital album (digital photo frame), mobile phone, panel computer etc. have product or the parts of any Presentation Function.
The utility model also provides a kind of preparation method of above-mentioned array base palte, the method be included on underlay substrate, form pixel cell and with for driving the process of the driving circuit of described pixel cell, be with the main difference part of array base palte preparation method in prior art, this array base palte preparation method also comprises the process that forms ground lead and the first static electricity shield layer.
Preferably, when above-mentioned driving circuit comprises gate driver circuit, source electrode drive circuit and/or common electrode driving circuit, the process of above-mentioned formation driving circuit can comprise:
On underlay substrate, form the process of described gate driver circuit, source electrode drive circuit and/or common electrode driving circuit.
Above-mentioned ground lead can form separately, for example, at the making layer of metal layer at the edge of underlay substrate as ground lead.
Preferred scheme is, above-mentioned ground lead forms with the process that forms pixel cell simultaneously, for example, pixel cell of the prior art generally includes the gate metal layer, gate insulation layer, active layer, the source that set gradually and leaks the functional film layer such as metal level, passivation layer and transparent electrode layer, and ground lead in the present embodiment can arrange with layer with gate metal layer and material is identical, or to leak metal level identical with layer setting and material ground lead and source.
So just can when forming gate metal layer or source leakage metal level, form ground lead, can reduce processing step, reduce technology difficulty, save production cost.
Take below and when forming gate metal layer, form ground lead and the process of the formation ground lead in the utility model is described in detail as example.
The formation ground lead process providing in the present embodiment mainly comprises:
Step S11, on underlay substrate depositing metal films;
Concrete, can adopt the methods such as magnetron sputtering or evaporation on underlay substrate, to deposit layer of metal film; The selected material of metallic film can, for the alloy of the metals such as Cr, Ti, Ta, Mo, Al, Cu or metal, can be also the laminated film being comprised of multiple layer metal film.
Step S12, by composition technique, form the gate metal layer pattern of described ground lead pattern and thin film transistor (TFT) simultaneously, or leak metal layer pattern by the source that composition technique forms described ground lead pattern and thin film transistor (TFT) simultaneously; And described ground lead pattern is positioned at described underlay substrate edge.
In the utility model, composition technique, can only include photoetching process, or, comprise photoetching process and etch step, can also comprise printing, ink-jet etc. other are used to form the technique of predetermined pattern simultaneously; Photoetching process, refers to that utilize photoresist, mask plate, the exposure machine etc. of technological processs such as comprising film forming, exposure, development form the technique of figure.Can be according to the corresponding composition technique of formed structure choice in the utility model.
For example, above-mentioned steps S12 detailed process can be,
Step S1211, on metallic film, be coated with one deck photoresist;
Step S1212, adopt common mask board to explosure, the photoresist that forms region outside the photoresist reserve area of corresponding ground lead and gate metal layer and corresponding above-mentioned zone is removed region;
Step S1213, photoresist is carried out to development treatment, after development treatment, the photoresist thickness of photoresist reserve area does not change, and the photoresist that photoresist is removed region is removed;
Step S1214, by etching technics, remove the metallic film that photoresist is removed region;
Step S1215, finally peel off remaining photoresist, the metallic film staying comprises gate metal layer and the ground lead of gate electrode and grid line.
And the forming process of leaking metal level and passivation layer etc. for gate insulation layer, active layer, source is roughly the same with related process of the prior art, specifically can comprise the following steps:
Step S1221, on gate metal layer and ground lead, form to cover the gate insulation layer of whole underlay substrate;
Step S1222, adopt PECVD(Plasma Enhanced Chemical Vapor Deposition, plasma enhanced chemical vapor deposition method) or additive method depositing semiconductor layers and doping semiconductor layer successively on gate insulation layer; Then adopt the method sedimentary origins such as magnetron sputtering or evaporation to leak metal level;
Step S1223, apply one deck photoresist on leaking metal level in source;
Step S1224, by duotone mask plate, expose, the photoresist that forms region outside photoresist half reserve area of the complete reserve area of photoresist in corresponding source electrode and drain electrode region, corresponding channel region and corresponding above-mentioned zone is removed region completely;
After step S1225, development treatment, the photoresist thickness of the complete reserve area of photoresist does not change, and the photoresist that photoresist is removed region is completely completely removed, the photoresist thickness attenuation of photoresist half reserve area; Then by the photoresist of etching technics removal for the first time, remove source leakage metal level, doping semiconductor layer and the semiconductor layer in region completely, form active layer pattern;
Step S1226, by cineration technics, remove the photoresist of photoresist half reserve area, metal level is leaked in the source that exposes this region;
Metal level and doping semiconductor layer are leaked in step S1227, the source of removing photoresist half reserve area by etching technics for the second time, and remove the semiconductor layer of segment thickness, form source electrode, drain electrode and channel region;
Step S1228, peel off remaining photoresist;
Step S1229, on source electrode, drain electrode and channel region, adopt PECVD method or other modes to deposit formation passivation layer.
Similar with the forming process of ground lead, above-mentioned the first static electricity shield layer can form separately, for example, increases layer of metal layer as the first static electricity shield layer on array base palte.
Above-mentioned the first static electricity shield layer also can form when forming pixel cell, for example, the first static electricity shield layer in the present embodiment can be identical with layer setting and material with the transparent electrode layer of pixel cell, so just can when forming transparent electrode layer, form the first static electricity shield layer, this kind of method can reduce processing step, reduce technology difficulty, save production cost.
Therefore,, in the present embodiment, take and when forming transparent electrode layer, form the first static electricity shield layer and the process of formation the first static electricity shield layer in the utility model is described in detail as example.
The process of formation the first static electricity shield layer providing in the present embodiment mainly comprises:
Step S21, on the underlay substrate that is formed with gate insulation layer and passivation layer, by composition technique, formed sectional hole patterns;
Concrete, can adopt duotone mask plate to offer the first via hole in the position above passivation layer is positioned at drain electrode by composition technique, the second via hole (being via hole described in the utility model 13) is offered in position above passivation layer and gate insulation layer are positioned at ground lead, certainly, in ground lead and source, leak when metal level arranges with layer and material is identical, only need form via hole at passivation layer.
Step S22, be formed with deposit transparent metallic film on the underlay substrate of sectional hole patterns;
Concrete, can adopt the methods such as magnetron sputtering or evaporation, on passivation layer, deposit layer of transparent metallic film, transparent metal film can adopt ITO or IZO monofilm, also can be adopted as ITO and IZO composite membrane.
Step S23, by composition technique, form transparency electrode layer pattern and described the first electrostatic defending layer pattern, and described the first static electricity shield layer covers described driving circuit top and is electrically connected to ground lead by described via hole.
Specifically can comprise the following steps:
Step S2311, on transparent metal film, be coated with one deck photoresist;
Step S2312, adopt common mask board to explosure, the photoresist that forms region outside the photoresist reserve area of corresponding transparent electrode layer and the first static electricity shield layer and corresponding above-mentioned zone is removed region;
Step S2313, photoresist is carried out to development treatment, after development treatment, the photoresist thickness of photoresist reserve area does not change, and the photoresist that photoresist is removed region is removed;
Step S2314, by etching technics, remove the transparent metal film that photoresist is removed region;
Step S2315, finally peel off remaining photoresist, the transparent metal film staying is transparent electrode layer and the first static electricity shield layer, transparent electrode layer is connected with drain electrode by the first via hole, and the first static electricity shield layer is connected with ground lead by the second via hole (being the via hole 13 in the utility model).
It should be noted that, mutual insulating between transparent electrode layer and the first static electricity shield layer, thus avoid the first static electricity shield layer to cause interference to the picture disply of viewing area.
Certainly, array base palte preparation method in the present embodiment is only a kind of implementation method of preparation array base palte provided by the utility model, can also be by increasing or reduce composition technique number of times, selecting different materials or combination of materials change implementation method to realize the utility model in actual using.
The utility model also provides a kind of method of preparing above-mentioned any one display device, the method comprise the process, preparation and the described array base palte that adopt method that above-described embodiment provides to prepare array base palte to box to the process of box substrate and by described array base palte and to box substrate the process to box.
In the preparation method of this display device, the preparation method of array base palte that can be by above-described embodiment due to the preparation process of array base palte realizes, thereby obtains being provided with the array base palte of ground lead and the first static electricity shield layer.
While the second static electricity shield layer not being set on to box substrate, similar to the preparation method of box substrate and preparation method of the prior art.
Take below and box substrate is illustrated to the process of preparation to box substrate as color membrane substrates as example, concrete can be:
Step S31, on underlay substrate, coating forms the black matrix photoresist layer of one deck;
Step S32, utilize mask plate to form black matrix by composition technique;
Step S33, on underlay substrate and black matrix, form colour element layer;
Take below and first prepare green pixel layer as example describes, specifically can comprise the following steps:
The techniques such as step S3311, employing deposition or coating form green pixel photoresist layer;
Step S3312, utilize mask plate to pass through composition technique to form green pixel layer;
Step S3313, then according to identical method, make other colored pixels layers;
Step S3314, the whole flatness layer that covers in color membrane substrates top.
While being provided with the second static electricity shield layer on color membrane substrates, except above-mentioned steps, the preparation method of the color membrane substrates in the present embodiment also comprises the process that forms the second static electricity shield layer, specifically can comprise:
Step S41, described to the flatness layer of box substrate on depositing metal films;
Be specifically as follows:
Adopt the method for magnetron sputtering or evaporation, on flatness layer, deposit layer of metal film, metallic film can adopt ITO(Indium Tin Oxides, indium tin oxide) or IZO(Indium Zinc Oxide, indium-zinc oxide) monofilm, also can be adopted as ITO and IZO composite membrane; Obviously, also can adopt metal and the metal alloys thereof such as Cr, Ti, Ta, Mo, Al, Cu herein, can be also the laminated film being comprised of multiple layer metal film; At this, do not do particular determination.
Step S42, by composition technique, form described the second electrostatic defending layer pattern, and described the second static electricity shield layer is corresponding with the position of described the first static electricity shield layer;
Specifically can comprise the following steps:
Step S4211, on metallic film, be coated with one deck photoresist;
Step S4212, adopt common mask board to explosure, the photoresist that forms region outside the photoresist reserve area of corresponding the second static electricity shield layer and corresponding above-mentioned zone is removed region;
Step S4213, photoresist is carried out to development treatment; After development treatment, the photoresist thickness of photoresist reserve area does not change, and the photoresist that photoresist is removed region is removed;
Step S4214, by etching technics, remove the metallic film that photoresist is removed region;
Step S4215, finally peel off remaining photoresist, the metallic film staying is the second static electricity shield layer.
Be understandable that, when the substrate of selecting outside color membrane substrates, for example base plate for packaging when to box substrate, can not comprise the step that forms above-mentioned colour element layer pattern and flatness layer to the preparation technology of box substrate.
Further, when when adding conductive particle thing realize the electrical connection between the first static electricity shield layer and the second static electricity shield layer in sealed plastic box, by array base palte with box substrate is comprised the process of box:
Step S51, at array base palte periphery, apply sealed plastic box, and sealed plastic box partly covers the first static electricity shield layer, the intra-zone that sealed plastic box covers the first static electricity shield layer is provided with conductive particle thing;
Step S52, by array base palte with bonding by sealed plastic box to box substrate periphery, and the first static electricity shield layer is electrically connected to by conductive particle thing with the second static electricity shield layer.
Certainly, display device preparation method in the present embodiment is only a kind of implementation method of preparation display device provided by the utility model, can also be by increasing or reduce composition technique number of times, selecting different materials or combination of materials change implementation method to realize the utility model in actual using.
In sum, in array base palte and display device that the utility model embodiment provides, by being arranged on ground lead and the first static electricity shield layer on array base palte, on to box substrate, the second static electricity shield layer being electrically connected to the first static electricity shield layer is set, when having electrostatic impact, utilize ground lead, the first static electricity shield layer and the second static electricity shield layer to form omnibearing electrostatic impact preventing mechanism, avoid causing due to electrostatic breakdown the damage of driving circuit, promoted greatly the reliability of product; And above-mentioned ground lead and the first static electricity shield layer can form with the process of preparing pixel cell simultaneously, thereby can avoid too much increase preparation method's difficulty.
Above embodiment is only for illustrating the utility model; and be not limitation of the utility model; the those of ordinary skill in relevant technologies field; in the situation that not departing from spirit and scope of the present utility model; can also make a variety of changes and modification, therefore all technical schemes that are equal to also belong to protection category of the present utility model.
Claims (11)
1. an array base palte, comprise underlay substrate, on described underlay substrate, be provided with some pixel cells and for driving the driving circuit of described pixel cell, it is characterized in that the first static electricity shield layer that described underlay substrate edge is also provided with ground lead and is electrically connected to described ground lead.
2. array base palte according to claim 1, is characterized in that, described the first static electricity shield layer covers described driving circuit top.
3. array base palte according to claim 1, is characterized in that, described driving circuit comprises gate driver circuit, source electrode drive circuit and/or common electrode driving circuit.
4. array base palte according to claim 1, is characterized in that, described pixel cell comprises thin film transistor (TFT); Described ground lead is identical with layer setting and material with gate metal layer or the source leakage metal level of described thin film transistor (TFT).
5. according to the array base palte described in claim 1-4 any one, it is characterized in that, described pixel cell also comprises gate insulation layer, passivation layer and the transparent electrode layer setting gradually, described the first static electricity shield layer is identical with layer setting and material with described transparent electrode layer, and described the first static electricity shield layer is electrically connected to described ground lead by the via hole on gate insulation layer and passivation layer.
6. a display device, is characterized in that, comprise according to the array base palte described in claim 1-5 any one and with described array base palte to box to box substrate.
7. display device according to claim 6, is characterized in that, described to being provided with the second static electricity shield layer being electrically connected to described the first static electricity shield layer on box substrate, and described the second static electricity shield layer is corresponding with the position of described the first static electricity shield layer.
8. display device according to claim 6, is characterized in that, described is color membrane substrates to box substrate.
9. display device according to claim 8, is characterized in that, is also provided with flatness layer on described color membrane substrates, and described the second static electricity shield layer is positioned at described flatness layer top.
10. according to the display device described in claim 7-9 any one, it is characterized in that, described the second static electricity shield layer is identical with described the first static electricity shield layer material and shape.
11. display device according to claim 7, it is characterized in that, described array base palte and described bonding by sealed plastic box to box substrate, and described sealed plastic box partly covers described the first static electricity shield layer, the intra-zone that described sealed plastic box covers described the first static electricity shield layer is provided with conductive particle thing;
Described the first static electricity shield layer is electrically connected to by described conductive particle thing with described the second static electricity shield layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320632830.7U CN203519954U (en) | 2013-10-14 | 2013-10-14 | Array substrate and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320632830.7U CN203519954U (en) | 2013-10-14 | 2013-10-14 | Array substrate and display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203519954U true CN203519954U (en) | 2014-04-02 |
Family
ID=50378858
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201320632830.7U Expired - Lifetime CN203519954U (en) | 2013-10-14 | 2013-10-14 | Array substrate and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203519954U (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103972242A (en) * | 2014-04-22 | 2014-08-06 | 京东方科技集团股份有限公司 | Array substrate, display device and manufacturing method of array substrate |
| CN104216165A (en) * | 2014-09-09 | 2014-12-17 | 合肥京东方光电科技有限公司 | Color film base plate and liquid crystal display device |
| CN104677314A (en) * | 2015-03-02 | 2015-06-03 | 合肥京东方光电科技有限公司 | Device and method for detecting surface flatness of display panel |
| CN106652822A (en) * | 2017-02-28 | 2017-05-10 | 深圳市华星光电技术有限公司 | Array basal plate and light-emitting diode display |
| CN109166554A (en) * | 2018-10-23 | 2019-01-08 | 惠科股份有限公司 | Display device |
| CN111198627A (en) * | 2018-11-16 | 2020-05-26 | 南昌欧菲触控科技有限公司 | Conductive film and touch screen |
| CN113419647A (en) * | 2021-07-05 | 2021-09-21 | 江苏加拉泰克微电子有限公司 | Anti-dazzle anti-electromagnetic interference touch module and corresponding preparation method thereof |
-
2013
- 2013-10-14 CN CN201320632830.7U patent/CN203519954U/en not_active Expired - Lifetime
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103972242A (en) * | 2014-04-22 | 2014-08-06 | 京东方科技集团股份有限公司 | Array substrate, display device and manufacturing method of array substrate |
| CN103972242B (en) * | 2014-04-22 | 2016-12-28 | 京东方科技集团股份有限公司 | A kind of manufacture method of array base palte, display device and array base palte |
| CN104216165A (en) * | 2014-09-09 | 2014-12-17 | 合肥京东方光电科技有限公司 | Color film base plate and liquid crystal display device |
| CN104677314A (en) * | 2015-03-02 | 2015-06-03 | 合肥京东方光电科技有限公司 | Device and method for detecting surface flatness of display panel |
| US9964403B2 (en) | 2015-03-02 | 2018-05-08 | Boe Technology Group Co., Ltd. | Device and method for detecting flatness of surface of display panel |
| CN106652822A (en) * | 2017-02-28 | 2017-05-10 | 深圳市华星光电技术有限公司 | Array basal plate and light-emitting diode display |
| CN109166554A (en) * | 2018-10-23 | 2019-01-08 | 惠科股份有限公司 | Display device |
| CN111198627A (en) * | 2018-11-16 | 2020-05-26 | 南昌欧菲触控科技有限公司 | Conductive film and touch screen |
| CN113419647A (en) * | 2021-07-05 | 2021-09-21 | 江苏加拉泰克微电子有限公司 | Anti-dazzle anti-electromagnetic interference touch module and corresponding preparation method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103513459A (en) | Array substrate and preparing method thereof, display device and preparing method thereof | |
| CN203519954U (en) | Array substrate and display device | |
| US9759966B2 (en) | Array substrate and method of manufacturing the same, and display device | |
| US7102718B1 (en) | Liquid crystal display device with particular TFT structure and method of manufacturing the same | |
| US20200212071A1 (en) | Array substrate and preparation method therefor, and display panel and display device | |
| CN111736395B (en) | Display panel and display device | |
| US9366923B2 (en) | Array substrate and method of fabricating the same, and display device | |
| CN103236440B (en) | Thin-film transistor, array base palte and manufacture method thereof, display unit | |
| CN105068373A (en) | Manufacturing method of TFT (Thin Film Transistor) substrate structure | |
| CN103456744B (en) | Array base palte and preparation method thereof, display device | |
| US10825842B2 (en) | Display panel and manufacturing method thereof, display device | |
| US20170285430A1 (en) | Array Substrate and Manufacturing Method Thereof, Display Panel and Display Device | |
| CN104112758B (en) | Light emitting diode display panel and manufacturing method thereof, and display device | |
| US20200348784A1 (en) | Touch display substrate, method of manufacturing the same and display device | |
| US20230252930A1 (en) | Display panel and manufacturing method thereof | |
| US20210366936A1 (en) | Display substrate and manufacturing method thereof, display panel | |
| US20250366324A1 (en) | Display panel and display device | |
| CN106918958B (en) | Fringe field switching liquid crystal display | |
| CN103885221B (en) | Large board electrified circuit and manufacturing method of large board electrified circuit | |
| US9563082B2 (en) | Display panel and display device comprising the same | |
| CN104465672A (en) | Array substrate and display device | |
| US11022848B2 (en) | Sealing structure, manufacturing method of the same, and display device | |
| CN103165525A (en) | TFT array substrate and preparation method of ESD protection circuit on TFT array substrate | |
| CN104330908A (en) | Color film substrate and manufacturing method thereof, display panel and display device | |
| US9608013B2 (en) | Array substrate, liquid crystal panel, and manufacturing method of array substrate |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20140402 |