CN203491978U

CN203491978U - Output stage circuit, class AB amplifier and electronic device

Info

Publication number: CN203491978U
Application number: CN201320390535.5U
Authority: CN
Inventors: 黄雷; 彭彦豪
Original assignee: Fairchild Semiconductor Suzhou Co Ltd
Current assignee: Fairchild Semiconductor Suzhou Co Ltd
Priority date: 2013-06-27
Filing date: 2013-06-27
Publication date: 2014-03-19
Anticipated expiration: 2023-06-27

Abstract

This utility model discloses an output stage circuit, comprising a power supply, a quiescent current control circuit and an output terminal circuit. The output stage circuit also comprises a quiescent current equalization circuit which is configured to reduce or increase the quiescent current passing through a quiescent current bias circuit in the quiescent current control circuit when the change in voltage of the power supply is detected in order to keep the quiescent current passing through the output terminal circuit constant. The utility model also discloses a class AM amplifier and an electronic device. In use, when the voltage of the power supply rises, the quiescent current passing through the output terminal circuit of the output stage circuit is kept constant, so that the power supply rejection ratio (PSRR) of the current of the output terminal circuit can be effectively increased and the power consumption can be reduced.

Description

Output stage circuit, class AB amplifier and electronic equipment

Technical Field

The utility model relates to an output stage circuit technique of amplifier especially relates to an output stage circuit, AB class amplifier and electronic equipment.

Background

An amplifier is a device that can amplify the voltage or power of an input signal. In the amplifier, the class AB amplifier is a common type of amplifier because of its advantages of high efficiency, low distortion, low power consumption of the power amplifier transistor, and good heat dissipation.

Fig. 1 is a schematic diagram of an output stage circuit of a conventional class AB amplifier, as shown in fig. 1, when a voltage of a Power Supply VCC rises, a quiescent current flowing through output end circuits of the output stage circuit, i.e., MP1 and MN1, is increased due to a channel length modulation effect, so that a Power Supply Rejection Ratio (PSRR) of the output end circuits is reduced, and Power consumption of the device is increased.

SUMMERY OF THE UTILITY MODEL

In order to solve the problems in the prior art, the utility model provides an output stage circuit, AB class amplifier and electronic equipment.

In order to achieve the above purpose, the technical scheme of the utility model is realized like this:

the utility model provides an output stage circuit, include: power supply, quiescent current control circuit and output stage circuit, output stage circuit still includes: and the static current balancing circuit is configured to reduce or increase the static current flowing through a static current bias circuit in the static current control circuit when detecting that the voltage of the power supply changes, so that the static current flowing through the output end circuit is kept constant.

The utility model also provides a class AB amplifier, include: an output stage circuit; output stage circuit includes power supply, quiescent current control circuit and output end circuit, output stage circuit still includes: and the quiescent current balancing circuit is configured to reduce or increase the quiescent current flowing through a quiescent current bias circuit in the quiescent current control circuit when detecting that the voltage of the power supply changes, so that the quiescent current flowing through the happy end circuit is kept constant.

The utility model also provides an electronic equipment, include: mainboard, shell and AB class amplifier, output stage circuit includes power supply, quiescent current control circuit and output end circuit, output stage circuit still includes: and the static current balancing circuit is configured to reduce the static current flowing through a static current bias circuit in the static current control circuit when detecting that the voltage of the power supply changes, so that the static current flowing through the output end circuit is kept constant.

The utility model provides an output stage circuit, AB class amplifier and electronic equipment, when detecting power supply's voltage and changing, reduce or increase the quiescent current of the quiescent current bias circuit who flows through among the quiescent current control circuit, the quiescent current of the output stage circuit that makes to flow through keeps invariable, when power supply's voltage risees, the quiescent current of the output stage circuit's of enabling to flow through output stage circuit keeps invariable, so, can rise the PSRR of output stage circuit effectively, reduce the consumption of equipment.

Additionally, the utility model discloses an among the implementation scheme, when power supply's voltage risees, the increase of the drain-source voltage of metal oxide semiconductor field effect transistor (MOS) of quiescent current equalizer circuit, the quiescent current of the quiescent current control circuit's of messenger's flowing through quiescent current control circuit reduces, thereby make the quiescent current of the output end circuit of flowing through keep invariable, so, when power supply's voltage risees, can keep the quiescent current of the output end circuit of output stage circuit of flowing through invariable effectively, thereby can rise the PSRR of output end circuit's electric current effectively, the consumption of reduction equipment.

Moreover, the utility model has simple, convenient and easy realization scheme; the method can be applied to various devices with different power supply voltages.

Drawings

FIG. 1 is a schematic diagram of an output stage of a conventional class AB amplifier;

FIG. 2 is a diagram illustrating simulation results using a prior art scheme;

FIG. 3 is a schematic diagram of the output stage circuit structure of the present invention;

FIG. 4 is a schematic diagram of an output stage circuit structure in practical application of the present invention;

fig. 5 is a schematic diagram of a simulation result according to the technical solution of the present invention.

Detailed Description

In general, if the functions implemented by the circuits are divided, the output stage circuit of the conventional class AB amplifier includes: a quiescent current control circuit and an output terminal circuit, as shown in fig. 1; the static current control circuit is configured to control the magnitude of the static current of the output end circuit and realize an AB type working mode. Here, the quiescent current control circuit includes: MP2, MP3, MP4, MN2, MN3, MN4, two first reference current sources I₀And two second reference current sources I₁(ii) a The output terminal circuit includes: MP1 and MN 1; the working mode for realizing the AB class is as follows: in a static state, the static current flowing through the output end circuit is small; when the dynamic-state circuit is in a dynamic state, the circuit can output larger current to a load, and has higher output efficiency and smaller cross-over distortion.

If it is divided from the type of MOS employed, as shown in fig. 1, the output stage circuit of the conventional class AB amplifier may include: composed of four P-channel metal oxide semiconductor field effect transistors (PMOS) including MP1, MP2, MP3 and MP4, a first reference current source I₀And a second reference current source I₁A first circuit of; and is composed ofFour N-channel metal oxide semiconductor field effect transistors (NMOS) comprising MN1, MN2, MN3 and MN4, a first reference current source I₀And a second current source I₁A second circuit of; wherein the first circuit and the second circuit each comprise a quiescent current bias circuit; the quiescent current bias circuit of the first circuit comprises MP2, MP3 and a first reference current source I₀The second quiescent current bias circuit comprises: MN2, MN3 and a first reference current source I₀. Here, the quiescent current bias circuit is configured to bias a quiescent current of the output terminal circuit such that the quiescent current flowing through the output terminal circuit is a mirror image of the quiescent current flowing through itself.

The principle of the magnitude of the quiescent current flowing through the output terminal circuit of the output stage circuit of the conventional class AB amplifier will be described below by taking the first circuit as an example.

As shown in fig. 1, in the output stage circuit of the conventional class AB amplifier, there are: v_gsMP1+V_gsMP4＝V_gsMP2+V_gsMP3(ii) a Wherein, V_gsMP1Representing the gate-source voltage, V, of MP1_gsMP4Representing the gate-source voltage, V, of MP4_gsMP2Representing the gate-source voltage, V, of MP2_gsMP3Represents the gate-source voltage of MP 3; MP1 and MP2 have the same gate finger size (finger size), and MP3 and MP4 have the same finger size, so the quiescent current flowing through MP1 is N times the quiescent current flowing through MP 2; where N denotes a ratio of the number of fingers (finger number) of MP1 to the finger number of MP2, where MP1 and MP2 have the same finger size: MP1 and MP2 are both finger (finger) structures, and the width-to-length ratio of each finger of MP1 and MP2 is the same.

The principle of the second circuit is the same as that of the first circuit, and is not described in detail here.

Therefore, in an ideal situation, the quiescent current flowing through the output-side circuit is N times of the quiescent current flowing through the quiescent current bias circuit, and when the value of N is determined, the quiescent current flowing through the output-side circuit is a fixed multiple of the quiescent current flowing through the quiescent current bias circuit, that is, the magnitude of the quiescent current flowing through the output-side circuit is constant. Here, the static current bias circuit may be a static current bias circuit of the first circuit, or may be a static current bias circuit of the second circuit.

However, as shown in fig. 2, due to the channel length modulation effect, the static current flowing through the output circuit increases as the voltage of the power supply VCC increases, and simulation results show that: in the process that the voltage of the power supply VCC rises from 2.5V to 5.5V, the quiescent current flowing through the output end circuit increases from 418uA to 610 uA; compared with the quiescent current flowing through the output end circuit when the voltage of the power supply VCC is 2.5V, the quiescent current flowing through the output end circuit when the voltage of the power supply VCC is 5.5V is increased by 50%.

The main manifestations of the channel length modulation effect causing the static current flowing through the output end circuit to increase with the voltage rise of the power supply VCC include:

first, in the output stage circuit of the conventional class AB amplifier, since V is_dsMP1+V_dsMN1＝V_VCCTherefore, when the voltage of the power supply VCC changes, V_dsMP1+V_dsMN1Variations will also occur. Wherein, V_dsMP1Represents the drain-source voltage, V, of MP1_dsMN1Represents the drain-source voltage, V, of MN1_VCCRepresenting the voltage of the supply source VCC. Therefore, due to the channel length modulation effect, when the voltage of the power supply VCC changes, the drain-source voltage of the output-side circuit is mismatched along with the change of the voltage of the power supply VCC, so that the ratio of the quiescent current flowing through the output-side circuit to the quiescent current flowing through the quiescent current bias circuit is no longer a fixed value, that is: the quiescent current flowing through the output circuit is no longer constant but varies. Here, the static current bias circuit may be a static current bias circuit of the first circuit, or may be a static current bias circuit of the second circuit.

Second, in the conventional class AB amplifier inputIn the output stage circuit, when the voltage of the power supply VCC rises, the first reference current source I is enabled due to the channel length modulation effect₀Drain-source voltage ofBecomes large, thereby causing the first reference current source I₀The quiescent current of the output circuit is increased, and the quiescent current flowing through the output circuit is obviously increased.

Based on this, the basic idea of the utility model is: when the voltage of the power supply is detected to change, the static current flowing through the static current bias circuit in the static current control circuit is reduced or increased, so that the static current flowing through the output end circuit is kept constant.

The present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.

The utility model provides an output stage circuit, as shown in FIG. 3, include: a power supply 31, a static current balancing circuit 32, a static current control circuit 33, and an output terminal circuit 34; wherein,

a power supply 31 configured to supply power to the quiescent current control circuit 33 and the output-end circuit 34;

a quiescent current balancing circuit 32 configured to reduce or increase a quiescent current flowing through a quiescent current bias circuit in the quiescent current control circuit 32 when detecting a change in voltage of the power supply 31, so that the quiescent current flowing through the output terminal circuit 34 is kept constant;

the quiescent current control circuit 33 is configured to control the quiescent current of the output end circuit 34 and implement a class AB operation mode.

Here, the detection of the change in the voltage of the power supply 31 means: detecting that the voltage of the power supply 31 at the current moment is different from the voltage at the previous moment; in practical application, the detecting that the voltage of the power supply 31 at the current moment is different from the voltage at the previous moment means: in the circuit design, outside the range of allowable variation, namely: outside the error range, it is detected that the voltage of the power supply 31 at the present time is different from the voltage at the previous time.

Accordingly, in practical applications, the keeping of the quiescent current flowing through the output terminal circuit 34 constant means that: in practical applications, the quiescent current flowing through the output terminal circuit 34 varies within a range that allows variation in circuit design.

When the voltage of the power supply 31 is detected to change, the quiescent current flowing through the quiescent current bias circuit in the quiescent current control circuit 32 is reduced or increased, so that the quiescent current flowing through the output terminal circuit 34 is kept constant, specifically:

when the voltage of the power supply 31 is detected to be increased, the quiescent current flowing through the quiescent current bias circuit in the quiescent current control circuit 32 is reduced, so that the quiescent current flowing through the output end circuit 34 is kept constant; when a decrease in the voltage of the power supply 31 is detected, the quiescent current flowing through the quiescent current bias circuit in the quiescent current control circuit 32 is increased, so that the quiescent current flowing through the output terminal circuit 34 is kept constant.

By reducing the quiescent current flowing through the quiescent current bias circuit in the quiescent current control circuit 33, the mismatch between the quiescent current flowing through the output terminal circuit 34 and the quiescent current flowing through the quiescent current bias circuit, which is caused by the variation of the drain-source voltage of the output terminal circuit 34, can be cancelled, so that the quiescent current flowing through the output terminal circuit 34 is kept constant, and the correlation between the quiescent current flowing through the output terminal circuit 34 and the voltage of the power supply 31 is reduced.

The working mode for realizing the AB class is as follows: in a static state, a smaller static current flowing through the output end circuit is smaller; when the dynamic-state circuit is in a dynamic state, the circuit can output larger current to a load, and has higher output efficiency and smaller cross-over distortion.

The static current balancing circuit 32 reduces or increases the static current flowing through the static current bias circuit in the static current control circuit 32, so that the static current flowing through the output terminal circuit 34 is kept constant, specifically: the quiescent current flowing through itself is increased or decreased to keep the quiescent current flowing through the output terminal circuit 34 constant.

Here, the static current balancing circuit 32 reduces the static current flowing through the static current bias circuit in the static current control circuit 32 by increasing the static current flowing through itself; the static current balancing circuit 32 increases the static current flowing through the static current bias circuit in the static current control circuit 32 by reducing the static current flowing through itself.

By increasing or decreasing the quiescent current flowing through the quiescent current balancing circuit 32, the quiescent current flowing through the quiescent current bias circuit in the quiescent current control circuit 33 can be decreased or increased, thereby canceling out the mismatch between the quiescent current flowing through the output terminal circuit 34 and the quiescent current flowing through the quiescent current bias circuit caused by the variation of the drain-source voltage of the output terminal circuit 34, and further keeping the quiescent current flowing through the output terminal circuit 34 constant, that is: in the circuit design, the change of the quiescent current flowing through the output terminal circuit 34 is within the allowable change range, and the dependence of the output terminal circuit quiescent current on the power supply voltage is reduced.

As shown in fig. 4, the quiescent current control circuit 33, when actually applied, may further include: the floating-voltage bias circuit comprises a first static current bias circuit 331, a second static current bias circuit 332 and a floating-voltage bias circuit 333, wherein the first static current bias circuit 331 and the second static current bias circuit 332 form a static current bias circuit; the first static current bias circuit 331 may include: a first PMOS P1, a second PMOS P2, a sixth NMOS N6, a first reference current source I₀And a first reference voltage source V₀The second quiescent current bias circuit 332 may include: a first NMOS N1, a second NMOS N2, a sixth PMOSP6, a second reference current source I₁And a second reference voltage source V₁The floating voltage bias circuit 333 may include: a third PMOS P3, a third NMOS N3, and a third reference current source I₂And a fourth reference current source I₃(ii) a The first static current bias circuit 331 and the second static current bias circuit 332 are configured to bias the static current of the output circuit 34, so that the static current flowing through the output circuit is a mirror image of the static current flowing through itself; a floating voltage bias circuit 333 configured to bias the voltage of the output terminal circuit 34.

The static current balancing circuit 32, as shown in fig. 4, may include: a first static current balancing sub-circuit 321 and a second static current balancing sub-circuit 322; the first static current balancing sub-circuit 321 includes: a fifth PMOS P5, the two static current balancing sub-circuits 322 comprising: fifth NMOS N5. In practical applications, the static current balancing circuit 32 may include only the first static current balancing sub-circuit 321, only the second static current balancing sub-circuit 322, or both the first static current balancing sub-circuit 321 and the second static current balancing sub-circuit 322 in a designed circuit.

As shown in fig. 4, the output-end circuit 34 may include: a fourth PMOS P4 and a fourth NMOSN 4.

The connection relationship of the components of the output stage circuit shown in fig. 4 is:

in the first static current bias circuit 331, the gate and the drain of the first PMOS P1 are connected to the gate of the fifth PMOS P5 and the source of the second PMOS P2 in the first static current balancing sub-circuit 321, the source of the first PMOS P1 is connected to the power supply 31, the gate and the drain of the second PMOS P2 are connected to the gate of the third PMOS P3 and the drain of the sixth NMOS N6 in the floating voltage bias circuit 333, the gate of the sixth NMOS N6 is connected to the first reference voltage source V₀The source of the sixth NMOS N6, the drain of the fifth PMOS P5 in the first static current balancing sub-circuit 321, and the first reference current source I₀Is connected to a first reference current source I₀The other end of the first voltage reference is connected to a ground point VSS, a first reference voltage source V₀The other end of the ground line is connected with a grounding point VSS;

in the first placeIn the two static current bias circuits 332, the gate and the drain of the first NMOS N1 are connected to the gate of the fifth NMOS N5 and the source of the second NMOS N2 in the second static current balancing sub-circuit 322, the source of the first NMOS N1 is connected to the ground VSS, the gate and the drain of the second NMOS N2 are connected to the gate of the third NMOS P3 and the drain of the sixth PMOS P6 in the floating voltage bias circuit 333, and the gate of the sixth PMOS P6 is connected to the second reference voltage source V₁The source of the sixth PMOS P6, the drain of the fifth NMOS N5 in the second static current balancing sub-circuit 322, and the second reference current source I₁Is connected to a second reference current source I₁Is connected to the power supply 31, a second reference voltage source V₀The other end of the power supply is connected with a power supply 31;

in the floating voltage bias circuit 333, the source of the third PMOS P3 and the third reference current source I₂Is connected to a connection point formed by the drain of the third NMOS N3 and the gate of the fourth PMOS P4 in the output terminal circuit 34, the drain of the third NMOS N3 is connected to the fourth reference current source I₃Is connected to a connection point formed by the source of the third NMOS N3 and the gate of the fourth NMOS N4, and a third reference current source I₂Is connected to the power supply 31, a fourth reference current source I₃The other end of the ground line is connected with a grounding point VSS;

in the output circuit 34, the source of the fourth PMOS P4 is connected to the power supply 31, the drain of the fourth PMOS P4 is connected to the drain of the fourth NMOS N4, and the source of the fourth NMOS N4 is connected to the ground VSS;

in the first static current balancing sub-circuit 321, the source of the fifth PMOS P5 is connected to the power supply 31;

in the second static current balancing sub-circuit 322, the source of the fifth NMOS N5 is connected to the ground VSS.

The working principle of the first static current balancing sub-circuit 321 is as follows:

when the voltage of the power supply 31 rises, because

And is

Remains substantially unchanged, therefore, V_dsP5Increase, causing the quiescent current flowing through the fifth PMOS P5 to increase; furthermore, it is possible to provide a liquid crystal display device,

and the fifth PMOS P5 and the first PMOS P1 are current mirrors, so when the voltage of the power supply 31 rises, I_P5Is increased so that I_P5In that

So that the quiescent current flowing through the first PMOS P1 decreases, i.e., the quiescent current flowing through the first quiescent current bias circuit 331 decreases as the voltage of the power supply 31 increases.

As shown in fig. 4, due to V_dsP1＝V_gsP1And V is_dsP4But is related to the voltage of the power supply 31, so that the static current flowing through the first PMOS P1 has a mismatch with the static current flowing through the fourth PMOS P4, and therefore, the effect of the mismatch is cancelled by the action of the fifth PMOS, so that the current of the fourth PMOS P4 is kept constant.

Wherein, V_dsP5Representing the drain-source voltage of the fifth PMOS P5,

representing a first reference voltage source V₀Voltage of V_gsN6Representing the gate-source voltage, V, of the sixth NMOS N6_VCCIndicating the voltage, V, of the power supply 31_gsP1Representing the gate-source voltage, V, of the first PMOS P1_gsP5Representing the gate-source voltage of the fifth PMOS P5,

denotes a first reference current source I₀Current of (I)_P5To representQuiescent current, I, flowing through the fifth PMOS P5_P1Represents the quiescent current flowing through the first PMOS P1, i.e., the quiescent current flowing through the first quiescent current bias circuit 331, V_dsP1Representing the drain-source voltage, V, of the first PMOS P1_dsP4Representing the drain-source voltage of the fourth PMOS P4.

When the voltage of the power supply 31 decreases, the operation principle of the first quiescent current balance sub-circuit 321 is opposite to that when the voltage of the power supply 31 increases, and the description thereof is omitted here.

The operation principle of the second static current balancing sub-circuit 322 is the same as that of the first static current balancing sub-circuit 321, and is not described herein again.

Based on the output stage circuit, the utility model also provides a quiescent current equilibrium method, this method includes: when the voltage of the power supply is detected to change, the static current flowing through the static current bias circuit in the static current control circuit is reduced or increased, so that the static current flowing through the output end circuit is kept constant.

Specifically, a static current balancing circuit is arranged;

when the voltage of the power supply is detected to change, the static current flowing through the static current balancing circuit is increased or decreased, so that the static current flowing through the output end circuit is kept constant.

Based on above-mentioned output stage circuit, the utility model also provides a class AB amplifier, include: an output stage circuit, as shown in fig. 3, the output stage circuit comprising: a power supply 31, a static current balancing circuit 32, a static current control circuit 33, and an output terminal circuit 34; wherein,

As shown in fig. 4, the quiescent current control circuit 33, when actually applied, may further include: first and second quiescent current bias circuits 331 and 332, and floating voltage biasThe circuit 333, the first static current bias circuit 331 and the second static current bias circuit 332 form a static current bias circuit; the first static current bias circuit 331 may include: a first PMOS P1, a second PMOS P2, a sixth NMOS N6, a first reference current source I₀And a first reference voltage source V₀The second quiescent current bias circuit 332 may include: a first NMOS N1, a second NMOS N2, a sixth PMOSP6, a second reference current source I₁And a second reference voltage source V₁The floating voltage bias circuit 333 may include: a third PMOS P3, a third NMOS N3, and a third reference current source I₂And a fourth reference current source I₃(ii) a The first static current bias circuit 331 and the second static current bias circuit 332 are configured to bias the static current of the output circuit 34, so that the static current flowing through the output circuit is a mirror image of the static current flowing through itself; a floating voltage bias circuit 333 configured to bias the voltage of the output terminal circuit 34.

in the first static current bias circuit 331, the gate and the drain of the first PMOS P1, the gate of the fifth PMOS P5 in the first static current balancing sub-circuit 321, and the gate of the second PMOS P2The source of the first PMOS P1 is connected with the power supply 31, the gate and the drain of the second PMOS P2 are connected with the gate of the third PMOS P3 and the drain of the sixth NMOS N6 in the floating voltage bias circuit 333, and the gate of the sixth NMOS N6 is connected with the first reference voltage source V₀The source of the sixth NMOS N6, the drain of the fifth PMOS P5 in the first static current balancing sub-circuit 321, and the first reference current source I₀Is connected to a first reference current source I₀The other end of the first voltage reference is connected to a ground point VSS, a first reference voltage source V₀The other end of the ground line is connected with a grounding point VSS;

in the second static current bias circuit 332, the gate and the drain of the first NMOS N1 are connected to the gate of the fifth NMOS N5 and the source of the second NMOS N2 in the second static current balancing sub-circuit 322, the source of the first NMOS N1 is connected to the ground VSS, the gate and the drain of the second NMOS N2 are connected to the gate of the third NMOS P3 and the drain of the sixth PMOS P6 in the floating voltage bias circuit 333, and the gate of the sixth PMOS P6 is connected to the second reference voltage source V₁The source of the sixth PMOS P6, the drain of the fifth NMOS N5 in the second static current balancing sub-circuit 322, and the second reference current source I₁Is connected to a second reference current source I₁Is connected to the power supply 31, a second reference voltage source V₀The other end of the power supply is connected with a power supply 31;

When the voltage of the power supply 31 rises, the first static current balancing sub-circuit 321 works according to the following principle:

when the voltage of the power supply 31 rises, the voltage of the power supply is controlled byAnd is

and the fifth PMOS P5 and the first PMOS P1 are current mirrors, so when the voltage of the power supply 31 rises, I_P5Is increased so that I_P5In thatSo that the quiescent current flowing through the first PMOS P1 decreases, i.e., the quiescent current flowing through the first quiescent current bias circuit 331 decreases as the voltage of the power supply 31 increases.

Wherein, V_gsP5Representing the gate-source voltage of the fifth PMOS P5,

representing a first reference voltage source V₀Voltage of V_gsN6Representing the gate-source voltage, V, of the sixth NMOS N6_VCCIndicating the voltage, V, of the power supply 31_gsP1Representing the gate-source voltage, V, of the first PMOS P1_gsP5Representing the gate-source voltage of the fifth PMOS P5,denotes a first reference current source I₀Current of (I)_P5Representing the quiescent current, I, flowing through the fifth PMOS P5_P1Represents the quiescent current flowing through the first PMOS P1, i.e., the quiescent current flowing through the first quiescent current bias circuit 331, V_dsP1Representing the drain-source voltage, V, of the first PMOS P1_dsP4Representing the drain-source voltage of the fourth PMOS P4.

Based on above-mentioned class AB amplifier, the utility model also provides an electronic equipment, this electronic equipment includes: mainboard, shell, and AB class amplifier, AB class amplifier includes output stage circuit, as shown in FIG. 3, output stage circuit includes: a power supply 31, a static current balancing circuit 32, a static current control circuit 33, and an output terminal circuit 34; wherein,

As shown in fig. 4, the quiescent current control circuit 33, when actually applied, may further include: first and second quiescent current bias circuits 331 and 331The circuit 332, the floating voltage bias circuit 333, the first static current bias circuit 331 and the second static current bias circuit 332 form a static current bias circuit; the first static current bias circuit 331 may include: a first PMOS P1, a second PMOS P2, a sixth NMOS N6, a first reference current source I₀And a first reference voltage source V₀The second quiescent current bias circuit 332 may include: a first NMOS N1, a second NMOS N2, a sixth PMOSP6, a second reference current source I₁And a second reference voltage source V₁The floating voltage bias circuit 333 may include: a third PMOS P3, a third NMOS N3, and a third reference current source I₂And a fourth reference current source I₃(ii) a The first static current bias circuit 331 and the second static current bias circuit 332 are configured to bias the static current of the output circuit 34, so that the static current flowing through the output circuit is a mirror image of the static current flowing through itself; a floating voltage bias circuit 333 configured to bias the voltage of the output terminal circuit 34.

in the first static current bias circuit 331, the gate and the drain of the first PMOS P1 and the fifth static current balancing sub-circuit 321The grid of the PMOS P5 is connected with the source of the second PMOS P2, the source of the first PMOS P1 is connected with the power supply 31, the grid and the drain of the second PMOS P2 are connected with the grid of the third PMOS P3 and the drain of the sixth NMOS N6 in the floating voltage bias circuit 333, and the grid of the sixth NMOS N6 is connected with the first reference voltage source V₀The source of the sixth NMOS N6, the drain of the fifth PMOS P5 in the first static current balancing sub-circuit 321, and the first reference current source I₀Is connected to a first reference current source I₀The other end of the first voltage reference is connected to a ground point VSS, a first reference voltage source V₀The other end of the ground line is connected with a grounding point VSS;

when the voltage of the power supply 31 rises, because

And is

Wherein, V_dsP5Representing the drain-source voltage of the fifth PMOS P5,

denotes a first reference current source I₀Current of (I)_P5Representing the quiescent current, I, flowing through the fifth PMOS P5_P1Represents the quiescent current flowing through the first PMOS P1, i.e., the quiescent current flowing through the first quiescent current bias circuit 331, V_dsP1Representing the drain-source voltage, V, of the first PMOS P1_dsP4Representing the drain-source voltage of the fourth PMOS P4.

Here, the electronic device may be a mobile phone, an ipad, a notebook computer, or the like.

Fig. 5 is a simulation result diagram obtained by adopting the technical scheme of the utility model, and the simulation result shows: adopt the technical scheme of the utility model, the in-process that power supply's voltage rose to 5.5V from 2.5V, and the quiescent current of the output end circuit of flowing through changes between 315uA to 324uA, and the rate of change is 3%.

Simultaneously, for explaining better and adopting the technical scheme of the utility model, the quiescent current of output Circuit is flowed through and is not changed along with power supply voltage's change, adopts the technical scheme of the utility model six Integrated Circuits (IC) that serial number is 1, 2, 3, 4, 5, 6 have been made to the quiescent current of the output Circuit of flowing through IC has been tested, and the test temperature is 25 ℃, and concrete result is shown as table 1.

TABLE 1

It can be seen from table 1 that, for each IC, in the process that the voltage of the power supply rises from 2.7V to 5.5V, the change of the quiescent current flowing through the output circuit of the IC is only a few uA, which illustrates that the test result has good repeatability, and after adopting the technical scheme of the utility model, the quiescent current flowing through the output circuit of the IC hardly changes along with the change of the voltage of the power supply.

The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention.

Claims

1. An output stage circuit comprising: power supply, quiescent current control circuit and output end circuit, its characterized in that, output stage circuit still includes: and when the voltage of the power supply is detected to change, the quiescent current flowing through the quiescent current bias circuit in the quiescent current control circuit is reduced or increased, so that the quiescent current flowing through the output end circuit is kept constant.

2. The output stage circuit of claim 1, wherein the quiescent current balancing circuit reduces or increases the quiescent current flowing through a quiescent current bias circuit in the quiescent current control circuit to keep the quiescent current flowing through the output stage circuit constant by: and increasing or decreasing the quiescent current flowing through the output end circuit to keep the quiescent current flowing through the output end circuit constant.

3. The output stage circuit of claim 1, wherein the quiescent current control circuit comprises: the circuit comprises a first static current bias circuit, a second static current bias circuit and a floating voltage bias circuit;

the static current balancing circuit includes: a first static current balancing sub-circuit and/or a second static current balancing sub-circuit;

the first quiescent current bias circuit includes: the first PMOS, the second PMOS, the sixth NMOS, a first reference current source and a first reference voltage source; the second quiescent current bias circuit includes: the first NMOS, the second NMOS, the sixth PMOS, a second reference current source and a second reference voltage source; the floating voltage bias circuit includes: a third PMOS, a third NMOS, a third reference current source and a fourth reference current source;

the output terminal circuit includes: a fourth PMOS and a fourth NMOS;

the first static current balancing sub-circuit comprises a fifth PMOS, and the second static current balancing sub-circuit comprises a fifth NMOS.

4. The output stage circuit of claim 3,

in the first static current bias circuit, the gate and the drain of the first PMOS are both connected with the gate of the fifth PMOS in the first static current balancing sub-circuit and the source of the second PMOS, and the source of the first PMOS is connected with the power supply; the grid electrode and the drain electrode of the second PMOS are both connected with the drain electrode of the sixth NMOS and the grid electrode of the third PMOS in the floating voltage bias circuit, the grid electrode of the sixth NMOS is connected with one end of the first reference voltage source, the source electrode of the sixth NMOS is connected with one end of the first reference current source and the drain electrode of the fifth PMOS in the first static current balancing sub-circuit, the other end of the first reference current source is connected with a grounding point, and the other end of the first reference voltage source is connected with the grounding point;

in the second static current bias circuit, the gate and the drain of the first NMOS are both connected to the gate of the fifth NMOS in the second static current balancing sub-circuit and the source of the second NMOS, and the source of the first NMOS is connected to the ground point; the grid electrode and the drain electrode of the second NMOS are both connected with the drain electrode of the sixth PMOS and the grid electrode of the third NMOS in the floating voltage bias circuit, the grid electrode of the sixth PMOS is connected with one end of the second reference voltage source, the source electrode of the sixth PMOS is connected with one end of the second reference current source and the drain electrode of the fifth NMOS in the second static current balancing sub-circuit, the other end of the second reference current source is connected with the power supply, and the other end of the second reference voltage source is connected with the power supply;

in the floating voltage bias circuit, a source of the third PMOS is connected to a connection point formed by one end of the third reference current source, a drain of the third NMOS, and a gate of the fourth PMOS in the output-side circuit, a drain of the third PMOS is connected to a connection point formed by one end of the fourth reference current source, a source of the third NMOS, and a gate of the fourth NMOS in the output-side circuit, another end of the third reference current source is connected to the power supply, and another end of the fourth reference current source is connected to the ground point;

in the output end circuit, the source of the fourth PMOS is connected to the power supply, the drain of the fourth PMOS is connected to the drain of the fourth NMOS, and the source of the fourth NMOS is connected to the ground point;

in the first static current balancing sub-circuit, the source of the fifth PMOS is connected to the power supply;

in the second static current balancing sub-circuit, the source of the fifth NMOS is connected to the ground point.

5. A class AB amplifier comprising: an output stage circuit; output stage circuit includes power supply, quiescent current control circuit and output end circuit, its characterized in that, output stage circuit still includes: and when the voltage of the power supply is detected to change, the quiescent current flowing through the quiescent current bias circuit in the quiescent current control circuit is reduced or increased, so that the quiescent current flowing through the output end circuit is kept constant.

6. The class AB amplifier of claim 5, wherein the quiescent current balancing circuit reduces or increases the quiescent current through a quiescent current bias circuit in the quiescent current control circuit to maintain a constant quiescent current through the output circuit by: and increasing or decreasing the quiescent current flowing through the output end circuit to keep the quiescent current flowing through the output end circuit constant.

7. The class AB amplifier of claim 5, wherein the quiescent current control circuit comprises: the circuit comprises a first static current bias circuit, a second static current bias circuit and a floating voltage bias circuit;

the output terminal circuit includes: a fourth PMOS and a fourth NMOS;

8. The class AB amplifier of claim 7,

9. An electronic device, comprising: mainboard, shell and AB class amplifier, AB class amplifier includes: an output stage circuit; output stage circuit includes power supply, quiescent current control circuit and output end circuit, its characterized in that, output stage circuit still includes: and when the voltage of the power supply is detected to change, the quiescent current flowing through the quiescent current bias circuit in the quiescent current control circuit is reduced, so that the quiescent current flowing through the output end circuit is kept constant.

10. The electronic device of claim 9, wherein the quiescent current balancing circuit reduces or increases the quiescent current flowing through a quiescent current bias circuit in the quiescent current control circuit to keep the quiescent current flowing through the output terminal circuit constant by: and increasing or decreasing the quiescent current flowing through the output end circuit to keep the quiescent current flowing through the output end circuit constant.

11. The electronic device of claim 9, wherein the quiescent current control circuit comprises: the circuit comprises a first static current bias circuit, a second static current bias circuit and a floating voltage bias circuit;

the output terminal circuit includes: a fourth PMOS and a fourth NMOS;

12. The electronic device of claim 11,