CN203480166U - Array substrate and display device - Google Patents
Array substrate and display device Download PDFInfo
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- CN203480166U CN203480166U CN201320603846.5U CN201320603846U CN203480166U CN 203480166 U CN203480166 U CN 203480166U CN 201320603846 U CN201320603846 U CN 201320603846U CN 203480166 U CN203480166 U CN 203480166U
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Abstract
The utility model provides an array substrate and a display device. The array substrate and the display device are used for increasing the aperture ratio of pixels. The array substrate comprises a substrate base plate, scanning lines, data lines and pixel units, wherein the scanning lines and the data lines are arranged on the substrate base plate in a crossed mode, the pixel units are formed through the scanning lines and the data lines in a division mode, and are arranged in a matrix mode, a thin film transistor, a pixel electrode and light-emitting structures are arranged in each pixel unit, the pixel electrodes are arranged above the layer where the thin film transistors are located, the area covered with the pixel electrodes comprises the area above the thin film transistors, the light-emitting structures are arranged above the layer where the thin film transistors are located, the area covered with the light-emitting structures corresponds to the area covered with the pixel electrodes, and the light-emitting structures are used for providing a backlight source.
Description
Technical field
The utility model relates to technical field of liquid crystal display, relates in particular to a kind of array base palte and display device.
Background technology
Thin Film Transistor-LCD (Thin Film Transistor Liquid Crystal Display, TFT-LCD) there is the features such as volume is little, low in energy consumption, radiationless, obtained in recent years developing by leaps and bounds, in current flat panel display market, occupied leading position.
TFT-LCD is comprised of display panels, driving circuit and backlight module, and display panels is the pith of TFT-LCD.Display panels is that surrounding seals by sealed plastic box by inject liquid crystal between array base palte and color membrane substrates, then on array base palte and color membrane substrates, sticks respectively that the process such as the orthogonal polaroid in polarization direction forms.Referring to Fig. 1 and Fig. 2, Fig. 1 is the plane structure chart of array base palte in prior art, and Fig. 2 is the cross-sectional view along the array base palte of A-A1 direction in Fig. 1; From Fig. 1 and Fig. 2, can find out, described array base palte comprises a plurality of pixel cells that matrix is arranged that are, described pixel cell comprises transmission region and non-transmission region, wherein, the transmission region that dotted line EE ' and dotted line CC ' institute delimited area are pixel cell, the non-transmission region that dotted line CC ' and dotted line DD ' institute delimited area are pixel cell.Described non-transmission region is included in sweep trace arranged in a crossed manner on underlay substrate 100 101 and data line 102, and being the thin film transistor (TFT) 10 that matrix form is arranged, described thin film transistor (TFT) 10 comprises: grid 103, gate insulation layer 104, active layer 105, source electrode 106 and drain 107; Described transmission region comprises pixel electrode 108.
Common described active layer 105 adopts amorphous silicon (a-Si) materials to form, the described thin film transistor (TFT) being formed by the amorphous silicon material advantages such as maturation, cost is low, technique is simple, good stability that possess skills; But the described tft characteristics being formed by amorphous silicon material is very low, wherein, the most basic parameter that represents tft characteristics comprises: amplitude under carrier mobility, threshold voltage and threshold.Along with the development of display technique, the thin film transistor (TFT) that employing polysilicon (p-Si) material forms and the thin film transistor (TFT) that adopts metal oxide materials to form have been there is; Wherein, the thin film transistor (TFT) that adopts polycrystalline silicon material to form has that TFT characteristic is high, carrier mobility advantages of higher, but the tft characteristics that described employing polycrystalline silicon material forms is unstable, homogeneity is poor; The thin film transistor (TFT) that described employing oxide material forms has the advantages such as characteristic is higher, homogeneity is good, but manufacturing cost is high, complex manufacturing technology.
Needs along with development trends such as high aperture, high resolving power, at present existing multiple technologies can be used for realizing higher resolution, as low-temperature polysilicon film transistor technology, oxide semiconductor film transistor technology, reduce the refinement technology of gate line, source electrode line and drain line width, but the improvement situation of aperture opening ratio is unsatisfactory, wherein, described aperture opening ratio refers to that peripheral circuit area and the light after TFT regions of removing each pixel pass through the area of part and the ratio between the area of each pixel integral body.Along with Organic Light Emitting Diode technology (Organic Light-Emitting Diode, OLED) development, OLED is used to improve the aperture opening ratio of pixel, but OLED is current driving apparatus, need higher carrier mobility, only have application of cold temperature polysilicon technology driving OLED could obtain higher aperture opening ratio, but, owing to existing homogeneity poor in low temperature polycrystalline silicon, complex process, the problems such as yields is low, make the scheme of application of cold temperature polysilicon technology driving OLED still cannot well solve the problem that aperture opening ratio is low.
Utility model content
The utility model embodiment provides a kind of array base palte and display device, in order to increase the aperture opening ratio of pixel.
The array base palte that the utility model embodiment provides comprises: a plurality of pixel cells that are matrix arrangement, described pixel cell comprises transmission region and non-transmission region, described transmission region comprises pixel electrode, described non-transmission region comprises thin film transistor (TFT), sweep trace and data line, wherein, described pixel electrode is positioned at the top of described thin film transistor (TFT) place layer, and described pixel electrode part or all cover described non-transmission region; Described pixel cell also comprise be arranged on described thin film transistor (TFT) place layer top, with the ray structure that pixel electrode insulation arranges, the overlay area of described ray structure is corresponding with the overlay area of described pixel electrode, for backlight is provided.
In described array base palte, comprise the pixel electrode of the top that is positioned at described thin film transistor (TFT) place layer, and the ray structure that is arranged on layer top, described thin film transistor (TFT) place; Wherein, the overlay area of described pixel electrode comprises the upper area of thin film transistor (TFT), and described ray structure is used for providing backlight.Because the overlay area of described pixel electrode comprises the upper area of thin film transistor (TFT), therefore the overlay area of pixel electrode increases compared with the overlay area of pixel electrode in prior art, simultaneously, because ray structure serves as backlight, therefore, make the corresponding region of pixel electrode that is positioned at thin film transistor (TFT) top have light to pass through, can carry out image demonstration, improved the aperture opening ratio of pixel.
Preferably, described ray structure is connected with public electrode wire, for serving as the public electrode of array base palte, has further simplified manufacture craft, has saved production cost.In addition, in described array base palte, can also set up a public electrode, and pixel electrode produces electric field jointly to drive liquid crystal layer molecule to deflect.
Preferably, described ray structure comprises: be arranged on the negative electrode of pixel electrode top, be arranged on the luminous material layer of negative electrode top, and the anode that is arranged on described luminous material layer top, wherein, described anodic bonding public electrode wire; Or described ray structure comprises: be arranged on the anode of pixel electrode top, be arranged on the luminous material layer of anode top, and the negative electrode that is arranged on described luminous material layer top, wherein, described anodic bonding public electrode wire.Luminous for driving luminous material layer to carry out owing to being provided with two electrodes in described ray structure, eliminated ray structure to having the dependence of the thin film transistor (TFT) of higher carrier mobility, having solved the lower thin film transistor (TFT) of carrier mobility can not be for making the problem of high aperture and high resolution display.
Preferably, described ray structure is positioned at the top of described pixel electrode, and described ray structure is slit-shaped, and described pixel electrode is tabular or slit-shaped; Or described ray structure is positioned at the below of described pixel electrode, described ray structure is slit-shaped or tabular, and described pixel electrode is slit-shaped.Make between described ray structure and pixel electrode, to form horizontal component of electric field, drive the liquid crystal molecule of liquid crystal layer to deflect, and then realize the demonstration of image.
Preferably, the thickness of described gate insulation layer is 6000～8000 dusts, this thickness is about the twice of gate insulation layer thickness in general thin film transistor (TFT), increase the thickness of described gate insulation layer, can effectively reduce the coupling capacitance between the grid of thin film transistor (TFT) and source electrode, drain electrode, and then reduce the power consumption of thin film transistor (TFT).
Preferably, array base palte also comprises the passivation layer being arranged between described thin film transistor (TFT) place layer and pixel electrode, makes to form pixel electrode at the upper area of described thin film transistor (TFT), is not corroded for the protection of thin film transistor (TFT) simultaneously; In addition, in described passivation layer, be also provided with via hole, described pixel electrode is electrically connected to the drain electrode of thin film transistor (TFT) by this via hole.
Preferably, described array base palte also comprises the second passivation layer being arranged between pixel electrode and ray structure, for described pixel electrode and ray structure are isolated.
The utility model embodiment provides a kind of display device, and described display device comprises above-mentioned array base palte.
Accompanying drawing explanation
Fig. 1 is the planar structure schematic diagram of a kind of array base palte of the prior art;
Fig. 2 is the cross-sectional view along the array base palte of A-A1 direction in Fig. 1;
The planar structure schematic diagram of a kind of array base palte that Fig. 3 provides for the utility model embodiment mono-;
Fig. 4 is the cross-sectional view along the array base palte of B-B1 direction in Fig. 3;
The cross-sectional view of ray structure in the array base palte that Fig. 5 provides for embodiment mono-;
The cross-sectional view of a kind of array base palte that Fig. 6 provides for the utility model embodiment bis-;
The cross-sectional view of a kind of array base palte that Fig. 7 provides for the utility model embodiment tri-;
Fig. 8 is the cross-sectional view of ray structure in embodiment tetra-;
Fig. 9 has been the cross-sectional view of the array base palte of fabrication;
Figure 10 has been the cross-sectional view of the array base palte of gate insulation layer making;
Figure 11 has been the cross-sectional view of the array base palte of active layer making;
Figure 12 has been the array base palte cross-sectional view that source electrode and drain electrode are made;
Figure 13 has been the array base palte cross-sectional view that passivation layer is made;
Figure 14 has been the array base palte cross-sectional view that pixel electrode is made;
Figure 15 has been the array base palte cross-sectional view that the second passivation layer is made;
The schematic flow sheet that Figure 16 is the array base palte making embodiment bis-and provide;
The schematic flow sheet of the thin film transistor (TFT) that Figure 17 is the array base palte making embodiment tri-and provide.
Embodiment
The utility model embodiment provides a kind of array base palte and display device, in order to increase the aperture opening ratio of pixel.
Below in conjunction with the accompanying drawing in the utility model embodiment, the technical scheme in the utility model embodiment is clearly and completely described, obviously, described embodiment is only the utility model part embodiment, rather than whole embodiment.Embodiment based in the utility model, those of ordinary skills are not making the every other embodiment obtaining under creative work prerequisite, all belong to the scope of the utility model protection.
The utility model embodiment mono-provides a kind of array base palte, referring to Fig. 3 and Fig. 4, and the planar structure schematic diagram of the array base palte that Fig. 3 provides for the utility model embodiment mono-, Fig. 4 is the cross-sectional view along the array base palte of B-B1 direction in Fig. 3; In conjunction with Fig. 3 and Fig. 4, can find out that described array base palte comprises: underlay substrate 100, sweep trace 101 and data line 102 arranged in a crossed manner on underlay substrate, and be thin film transistor (TFT) 10 and the pixel electrode 108 that matrix is arranged; Wherein, described thin film transistor (TFT) 10 comprises: grid 103, gate insulation layer 104, active layer 105, source electrode 106 and drain 107.Described array base palte also comprises the ray structure 301 that is arranged on described pixel electrode 108 tops, and described ray structure 301 is for providing backlight.
Concrete, described grid 103 arranges with layer with sweep trace 101, is all positioned at the top of described underlay substrate 100, and described sweep trace 101 is for providing sweep signal to described grid 103; And described grid 103 adopts identical making material with described sweep trace 101, and making material used is generally non-transparent metals and the alloys thereof such as chromium (Cr), tungsten (W), titanium (Ti), molybdenum (Mo), aluminium (Al), copper (Cu).
Described gate insulation layer 104 is positioned at the top of described grid 103 and sweep trace 101 place layers, covers the upper area of described grid 103 and sweep trace 101, for described grid 103 and sweep trace 101 and other layer are insulated.Described gate insulation layer adopts monox or silicon nitride material to form, and its thickness is 6000～8000 dusts, is about the twice of gate insulation layer thickness in prior art.Increase the thickness of described gate insulation layer 104, the coupling capacitance that can effectively reduce grid 103 and source electrode 106 and drain between 107, the power consumption of reduction thin film transistor (TFT).
Described active layer 105 is positioned at the top of described gate insulation layer, and described active layer is film layer structure, specifically comprises semiconductor material layer 105a and ohmic contact layer 105b; In the present embodiment, described semiconductor material layer 105a adopts indium gallium zinc oxide or other transition metal oxide layers to form; In addition, described semiconductor material layer 105a can also adopt amorphous silicon material or polycrystalline silicon material to form.Described ohmic contact layer 105b, be arranged on described semiconductor material layer 105a top, with source electrode 106, the 107 corresponding positions that drain, generally adopt the formation of phosphorus doping amorphous silicon material.
Described source electrode 106 and drain electrode 107 arrange with layer with data line 102, are all positioned at the top of described active layer 105 place layers, and adopt identical making material, and making material used is generally nontransparent metal material or its alloy;
Described data line 102 is electrically connected to described source electrode 106;
The relative both sides that described source electrode 106 is positioned at described active layer 105 tops with drain electrode 107.
Described pixel electrode 108, is positioned at the upper area of described data line 102, source electrode 106 and the 107 place layers that drain, and its overlay area comprises the upper area of thin film transistor (TFT), described pixel electrode part or all cover described non-transmission region; The general transparent oxide materials such as tin indium oxide, indium zinc oxide or aluminum zinc oxide that adopt of described pixel electrode 108 are made, and it is shaped as tabular or slit-shaped.
Described ray structure 301, is positioned at the upper area of described pixel electrode 108, and arranges with described pixel electrode 108 insulation, and described ray structure 301 is slit-shaped, for backlight is provided; Meanwhile, described ray structure 301, also for serving as the public electrode of described array base palte, for jointly forming horizontal component of electric field with described pixel electrode 108, drives the liquid crystal molecule of liquid crystal layer to deflect, thereby realize wide-angle, shows.
Referring to Fig. 5, described ray structure 301 comprises: the negative electrode 3011 that is arranged on pixel electrode 108 tops, be arranged on the luminous material layer 3012 of described negative electrode 3011 tops, and the anode 3013 that is arranged on described luminous material layer 3012 tops, described anode 3013 connects the public electrode wire of described array base palte.Described negative electrode 3011 and anode 3013, for offering driving voltage to described ray structure, make described ray structure produce white light.
In addition, described ray structure 301 also comprises:
The first restraining barrier 3016, it is transferred to described negative electrode 3011 for blocking hole between described electron transfer layer 3014 and described luminous material layer 3012;
The second restraining barrier 3017, it is transferred to described anode 3013 for block electrons between described hole transmission layer 3015 and described luminous material layer 3012.
Described luminous material layer 3012 comprises: the orange phosphorescent layer 3012a that is positioned at 3016 tops, described the first restraining barrier, be positioned at the blue fluorescent body 3012b of described orange phosphorescent layer 3012a top, and the green phosphorescent layer 3012c that is positioned at described blue fluorescent body 3012b top.
During the work of described ray structure, from described negative electrode 3011, inject electronics, from described anode 3013 injected holes, electronics imports in luminous material layer 3012 by described electron transfer layer 3014, hole imports in luminous material layer 3012 by described hole transmission layer 3015, electronics and hole are compound in described luminous material layer 3012, form singlet state exciton and triplet exciton, described singlet state exciton and triplet exciton by excited state in the process of ground state transition, its energy discharges in the mode of photon and heat energy, wherein, part photon is used as backlight, for realizing the demonstration of image, provide light, concrete, in blue fluorescent body 3012b, the exciton of singlet state is by excited state during to ground state transition, send blue fluorescence, in orange phosphorescent layer 3012a and green phosphorescent layer 3012c, the exciton of triplet during to excited state transition, sends green phosphorescent and orange phosphorescence by ground state, described blue-fluorescence and green phosphorescent, orange phosphorescence are compound, form white light.
Further; in described array base palte, also comprise passivation layer 302; described passivation layer 302 is arranged on the top of described data line 102, source electrode 106 and the 107 place layers that drain; the upper area of cover film transistor 10; make above described thin film transistor (TFT), to form pixel electrode, for the protection of thin film transistor (TFT) 10, be not corroded simultaneously.
In addition, in described passivation layer 302, be also provided with via hole 303, described via hole 303 is arranged on and the 107 corresponding positions that drain, and described pixel electrode 108 and described drain electrode 107 are electrically connected to by this via hole 303.
Further, described array base palte also comprises the second passivation layer 304, and described the second passivation layer 304 is arranged on the top of described pixel electrode 108 place layers, for described pixel electrode 108 and ray structure 301 are isolated.Described the second passivation layer 304 adopts resin material to form, with respect to monox and silicon nitride material, described resin material has lower relative dielectric coefficient, can effectively reduce the coupling capacitance between described pixel electrode and ray structure, further reduces the power consumption of this array base palte; And use resin material to use monox or silicon nitride material to be easier to form the second passivation layer.
During above-mentioned array base palte work, its driving process is as follows:
On grid 103, apply positive bias, make thin film transistor (TFT) conducting, data-signal passes to the drain electrode 107 of thin film transistor (TFT) from the source electrode 106 of thin film transistor (TFT), and is transferred to pixel electrode 108 by described via hole 303;
After ray structure 301 energisings, be equivalent to the public electrode of this array base palte, pixel electrode 108 couplings with being positioned at its below, produce for driving the electric field of liquid crystal deflecting element, thereby realize wide-angle, show.
The utility model is implemented two a kind of array base palte is provided, referring to Fig. 6, the array base-plate structure that the structure of described array base palte and embodiment mono-provide is basic identical, both are difference, in the array base palte that embodiment bis-provides, described ray structure 301 can arrange the below of described pixel electrode 108, and described ray structure 301 is tabular or slit-shaped, and described pixel electrode 108 is slit-shaped.Concrete: described the second passivation layer 304 is located at the top of described thin film transistor (TFT) place layer, described ray structure 301 is arranged on the top of described the second passivation layer 304, described passivation layer 302 is arranged on the top of described ray structure 301, described pixel electrode 108 is arranged on the top of described passivation layer 302, described pixel electrode 108 is by via hole 303 ' 107 be electrically connected to draining, described via hole 303 ' run through described passivation layer 302 and the second passivation layer 304.
The utility model embodiment tri-provides a kind of array base palte, referring to Fig. 7, as can be seen from Figure 7, the structure of the array base palte shown in this array base palte and Fig. 4 is basic identical, both difference parts are: the array base palte that the array base palte shown in Fig. 4 is bottom grating structure, and the array base palte that the array base palte shown in Fig. 7 is top gate structure is concrete: described active layer 105 is positioned at the top of described underlay substrate 100; Described source electrode 106, drain 107 and data line with layer, arrange, be positioned at the top of described active layer 105; Described gate insulation layer 104 is positioned at the top of described source electrode 106 and drain electrode 107 place layers; Described grid 103 is positioned at the top of described gate insulation layer 104; And 303 of via holes run through passivation layer 302 in the array base palte shown in Fig. 4, and in the array base palte shown in Fig. 6 for making to drain 107 and the via hole 303 that is electrically connected to of pixel electrode 108 ' run through passivation layer 302 and gate insulation layer 104.
Be pointed out that, the array base palte providing for the utility model embodiment tri-, described ray structure 301 also can be arranged on the below of described pixel electrode 108, repeats no more herein.
The utility model embodiment tetra-provides a kind of array base palte, the structure of the array base palte shown in this array base palte and Fig. 4 is basic identical, both difference parts are: in described array base palte, the structure of ray structure is different from the structure of ray structure in the array base palte shown in Fig. 4, concrete, referring to Fig. 8, in the ray structure of described array base palte, hole transmission layer 3015 is arranged on the top of anode 3013, the second restraining barrier 3017 is arranged on the top of hole transmission layer 3015, luminous material layer 3012 is arranged on the top on described the second restraining barrier 3017, one restraining barrier 3016 is arranged on the top of luminous material layer 3012, electron transfer layer 3014 is arranged on the top on the first restraining barrier 3016, negative electrode is arranged on the top of electron transfer layer 3014, wherein, the general tin indium oxide/silver/tin indium oxide multiple film layer structure that adopts of described anode 3013, the general transparent low work function alloy materials such as magnesium silver alloy, lithium-aluminium alloy that adopt of described negative electrode 3011.
In like manner, the array base palte providing for the utility model embodiment tetra-, described ray structure 301 also can be arranged on the below of described pixel electrode 108, repeats no more herein.
The utility model embodiment five provides a kind of array base palte, the structure of the array base palte shown in this array base palte and Fig. 7 is basic identical, both difference parts are: in described array base palte, the structure of ray structure is different from the structure of ray structure in the array base palte shown in Fig. 7, and in this array base palte, the concrete structure of ray structure is referring to Fig. 8; In like manner, in the array base palte that the utility model embodiment five provides, described ray structure 301 also can be arranged on the below of described pixel electrode 108, repeats no more herein.
In the array base palte that above-described embodiment one, embodiment bis-, embodiment tri-, embodiment tetra-and embodiment five provide, the overlay area of described pixel electrode comprises the upper area of thin film transistor (TFT), and described ray structure is used for providing backlight.In this array base palte, because the overlay area of described pixel electrode comprises the upper area of thin film transistor (TFT), therefore the overlay area of pixel electrode increases compared with the overlay area of pixel electrode in prior art, simultaneously, because ray structure serves as backlight, therefore, make the corresponding region of pixel electrode that is positioned at thin film transistor (TFT) top have light to pass through, be conducive to improve the aperture opening ratio of pixel; In addition, described ray structure, also for serving as the public electrode of described array base palte, produces for driving the horizontal component of electric field of liquid crystal molecule with described pixel electrode acting in conjunction, thereby has realized wide-angle demonstration.
The utility model embodiment provides a kind of method for making of array base palte, described method comprises the step that forms data line, sweep trace, pixel electrode and the step that forms thin film transistor (TFT), described pixel electrode is formed on the transparent region of pixel cell, described thin film transistor (TFT) all, sweep trace and data line be formed on the nontransparent region of described pixel region, wherein, described pixel electrode is positioned at the top of described thin film transistor (TFT) place layer, its overlay area comprises the upper area of thin film transistor (TFT), described pixel electrode part or all cover described non-transmission region; Described method also comprises the step that forms ray structure, described ray structure is positioned at the top of described pixel electrode, arrange with described pixel electrode insulation, the overlay area of described ray structure is corresponding with the overlay area of described pixel electrode, for backlight is provided.
The array base palte that the utility model embodiment mono-of take below provides is example, introduces in detail in actual fabrication technique, and the method for making of described array base palte, the method specifically comprises:
The first step, referring to Fig. 9, on described underlay substrate 100, deposit layer of metal film, then by composition PROCESS FOR TREATMENT, formation comprises the figure of sweep trace and grid 103, described in be used to form metallic film material be non-transparent metals and the alloys thereof such as Cr, W, Ti, Ta, Mo, Al, Cu.
Second step, referring to Figure 10, deposited silicon nitride or silicon oxide layer above the described figure that comprises sweep trace and grid 103, form gate insulation layer 104;
This step specifically comprises:
Deposited silicon nitride or silicon oxide layer above the described figure that comprises sweep trace and grid 103, its thickness is 6000～8000 dusts, is about 2 times of gate insulation layer thickness in prior art; On described silicon nitride or silicon oxide layer, apply photoresist; Then through overexposure, the techniques such as development, remove corresponding part silicon nitride or the monox of channel region, make the thickness of gate insulation layer corresponding to conducting channel region identical with the thickness of conducting channel in prior art and gate insulation layer, thereby guaranteed higher ON state current.
The 3rd step, referring to Figure 11, deposited semiconductor material and phosphorus doping amorphous silicon material successively above described gate insulation layer 104, then form by composition technique the figure that comprises active layer 105; Wherein, described semiconductor material can be polysilicon semiconductor material, amorphous silicon semiconductor material or metal oxide semiconductor material.
The 4th step, referring to Figure 12, above the described figure that comprises active layer 105, metallic film is leaked in formation source, then by composition technique, forms and comprises data line, source electrode 106 and 107 the figure of draining.
The 5th step, referring to Figure 13, described comprise data line, source electrode 106 and 107 the figure of draining above deposited silicon nitride or silicon oxide layer, form passivation layer 302, make above thin film transistor (TFT), to form pixel electrode, and be not corroded for the protection of thin film transistor (TFT); And, utilize composition technique to form via hole 303 in this passivation layer 302, described via hole 303 runs through described passivation layer 302, corresponding with the position of drain electrode 107.
The 6th step, referring to Figure 14, above described passivation layer 302, use magnetron sputtering method deposition indium oxide layer tin transparent conductive film, and by composition technique, formation comprises the figure of pixel electrode 108, the overlay area of described pixel electrode 108 comprises the upper area of film crystal, and described pixel electrode part or all cover the non-transmission region of pixel cell; And described pixel electrode 108 is electrically connected to described drain electrode 107 by via hole 303.
The 7th step, referring to Figure 15, spin coating resin above the described figure that comprises pixel electrode 108, forms the second passivation layer 304, for described pixel electrode 108 is isolated with ray structure 301.Described the second passivation layer can also adopt silicon nitride or silica material to make, but described resin material has lower relative dielectric coefficient, can effectively reduce the coupling capacitance between described pixel electrode and ray structure, further reduce the power consumption of this array base palte, and because resin material has mobility, silicon nitride or silica material more easily form the second passivation layer relatively.
The 8th step, referring to Fig. 4, above described the second passivation layer 304, deposit successively the conductive material of high reflectance, luminescent material and transparent conductive material, then by composition technique, form the figure that comprises ray structure 301, described ray structure 301 is for providing backlight, also for serving as the public electrode of array base palte, jointly produce electric field to drive liquid crystal molecule to deflect with described pixel electrode simultaneously, realize image and show; Concrete, the step of described formation ray structure 301 comprises: above described passivation layer, deposition has the conductive material of high reflectance, and forms by composition technique the figure that comprises negative electrode; Depositing light-emitting material above the described figure that comprises negative electrode, and by composition technique, form the figure that comprises luminous material layer; Above the described figure that comprises luminous material layer, form deposit transparent conductive material, and form by composition technique the figure that comprises anode.
Through above-mentioned steps, form that the utility model embodiment mono-is that provide, structure array base palte as shown in Figure 4.
For the utility model, implement the array base palte that two ray structures that provide are arranged on pixel electrode below, its method for making is basic identical with the method for the array base palte that making the utility model embodiment mono-provides, both are difference, referring to Figure 16, the method that the utility model enforcement two array base paltes that provide are provided comprises:
Described comprise data line, source electrode 106 and 107 the figure of draining above spin coating resin, form the second passivation layer 304, for described thin film transistor (TFT) and ray structure 301 are isolated;
Above described the second passivation layer 304, deposit successively the conductive material of high reflectance, luminescent material and transparent conductive material, then by composition technique, form the figure that comprises ray structure 301;
Deposited silicon nitride or silicon oxide layer above the described figure that comprises ray structure 301, form passivation layer 302;
Above described passivation layer 302, use magnetron sputtering method deposition indium oxide layer tin transparent conductive film, and by composition technique, form the figure that comprises pixel electrode 108, the overlay area of described pixel electrode 108 comprises the upper area of film crystal; And described pixel electrode 108 is by via hole 303 ' 107 be electrically connected to draining, described via hole 303 ' run through described passivation layer 302 and the second passivation layer 304.
Through above-mentioned steps, form that the utility model embodiment bis-is that provide, structure array base palte as shown in Figure 6.
Be pointed out that, for ray structure in the utility model, be arranged on the array base palte of pixel electrode below, all to form successively the second passivation layer, ray structure, passivation layer and pixel electrode after forming thin film transistor (TFT), the method for the array base palte that specifically can provide with reference to making embodiment bis-.
The array base palte providing for the utility model embodiment tri-, its method for making is similar with the method for the array base palte that making the utility model embodiment mono-provides, and difference is, referring to Figure 17, when making the array base palte that embodiment tri-provides, the step that forms thin film transistor (TFT) comprises:
Deposition of amorphous silicon semiconductor material layer 105a and phosphorus doping amorphous silicon material layer 105b above described underlay substrate 100, then form by composition technique the figure that comprises active layer 105;
Above the described figure that comprises active layer 105, metallic film is leaked in formation source, then by composition technique, forms and comprises data line, source electrode 106 and 107 the figure of draining;
Described comprise data line, source electrode 106 and 107 the figure of draining above deposited silicon nitride or silica material, form gate insulation layer 104;
Above described gate insulation layer 104, deposit layer of metal film, then by composition PROCESS FOR TREATMENT, formation comprises the figure of sweep trace and grid 103, described in be used to form metallic film material be non-transparent metals and the alloys thereof such as Cr, W, Ti, Ta, Mo, Al, Cu.
The array base palte providing for the utility model embodiment tetra-, its method for making is similar with the method for the array base palte that making the utility model embodiment mono-provides, difference is, when making the array base palte that embodiment tetra-provides, the step that forms ray structure comprises: above described passivation layer, deposition has the conductive material of high reflectance, and forms by composition technique the figure that comprises anode; Depositing light-emitting material above the described figure that comprises anode, and by composition technique, form the figure that comprises luminous material layer; Deposit transparent conductive material above the described figure that comprises luminous material layer, and by composition technique, form the figure that comprises negative electrode.
The array base palte providing for the utility model embodiment five, its method for making is similar with the method for the array base palte that making the utility model embodiment tri-provides, difference is, when making the array base palte that embodiment five provides, the step of described formation ray structure with at making embodiment tetra-, provide array base palte time to form the step of ray structure identical.
Be pointed out that, in the utility model, described composition technique, can only include photoetching process, or, comprise photoetching process and etch step, can also comprise printing, ink-jet etc. other are used to form the technique of predetermined pattern simultaneously; Photoetching process, refers to that utilize photoresist, mask plate, the exposure machine etc. of technological processs such as comprising film forming, exposure, development form the technique of figure.Can be according to the corresponding composition technique of formed structure choice in the utility model.
The utility model embodiment provides a kind of display device, and described display device comprises above-mentioned array base palte.
To sum up, in the array base palte that the utility model embodiment provides, because the overlay area of described pixel electrode comprises the upper area of thin film transistor (TFT), therefore the overlay area of pixel electrode increases compared with the overlay area of pixel electrode in prior art, meanwhile, and because ray structure serves as backlight, therefore, make the corresponding region of pixel electrode that is positioned at thin film transistor (TFT) top have light to pass through, can carry out image demonstration, be conducive to improve the aperture opening ratio of pixel; Meanwhile, owing to being provided with two electrodes in described ray structure, so the driving of this ray structure do not rely on the characteristic with thin film transistor (TFT), and therefore having solved amorphous silicon material can not be for making the problem of high resolving power and high aperture display.
Obviously, those skilled in the art can carry out various changes and modification and not depart from spirit and scope of the present utility model the utility model.Like this, if within of the present utility model these are revised and modification belongs to the scope of the utility model claim and equivalent technologies thereof, the utility model is also intended to comprise these changes and modification interior.
Claims (8)
1. an array base palte, described array base palte comprises a plurality of pixel cells that matrix is arranged that are, described pixel cell comprises transmission region and non-transmission region, described transmission region comprises pixel electrode, described non-transmission region comprises thin film transistor (TFT), sweep trace and data line, it is characterized in that
Described pixel electrode is positioned at the top of described thin film transistor (TFT) place layer, and described pixel electrode part or all cover described non-transmission region;
Described pixel cell also comprise be arranged on described thin film transistor (TFT) place layer top, with the ray structure that pixel electrode insulation arranges, the overlay area of described ray structure is corresponding with the overlay area of described pixel electrode, for backlight is provided.
2. array base palte as claimed in claim 1, is characterized in that, described ray structure is connected with public electrode wire, for serving as the public electrode of array base palte.
3. array base palte as claimed in claim 2, is characterized in that, described ray structure comprises: the negative electrode that is arranged on pixel electrode top, be arranged on the luminous material layer of negative electrode top, and the anode that is arranged on described luminous material layer top, wherein, described anodic bonding public electrode wire;
Or described ray structure comprises: be arranged on the anode of pixel electrode top, be arranged on the luminous material layer of anode top, and the negative electrode that is arranged on described luminous material layer top, wherein, described anodic bonding public electrode wire.
4. array base palte as claimed in claim 2, is characterized in that, described ray structure is positioned at the top of described pixel electrode, and described ray structure is slit-shaped, and described pixel electrode is tabular or slit-shaped;
Or described ray structure is positioned at the below of described pixel electrode, described ray structure is slit-shaped or tabular, and described pixel electrode is slit-shaped.
5. array base palte as claimed in claim 1, is characterized in that, the thickness of described gate insulation layer is 6000～8000 dusts.
6. array base palte as claimed in claim 1, is characterized in that, described array base palte also comprises the passivation layer being arranged between described thin film transistor (TFT) place layer and pixel electrode.
7. the array base palte as described in claim as arbitrary in claim 1～6, is characterized in that, described array base palte also comprises the second passivation layer being arranged between pixel electrode and ray structure.
8. a display device, is characterized in that, described display device comprises the array base palte described in the arbitrary claim of claim 1～7.
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| CN201320603846.5U CN203480166U (en) | 2013-09-25 | 2013-09-25 | Array substrate and display device |
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| CN201320603846.5U CN203480166U (en) | 2013-09-25 | 2013-09-25 | Array substrate and display device |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103489892A (en) * | 2013-09-25 | 2014-01-01 | 北京京东方光电科技有限公司 | Array substrate, preparing method of array substrate and display device of array substrate |
| WO2016179940A1 (en) * | 2015-05-12 | 2016-11-17 | 京东方科技集团股份有限公司 | Oled pixel unit, transparent display apparatus and manufacturing method, and display device |
| CN114628409A (en) * | 2022-03-17 | 2022-06-14 | 京东方科技集团股份有限公司 | Display substrate, preparation method thereof and display panel |
| CN118844130A (en) * | 2023-02-24 | 2024-10-25 | 京东方科技集团股份有限公司 | Array substrate and display device |
-
2013
- 2013-09-25 CN CN201320603846.5U patent/CN203480166U/en not_active Expired - Fee Related
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103489892A (en) * | 2013-09-25 | 2014-01-01 | 北京京东方光电科技有限公司 | Array substrate, preparing method of array substrate and display device of array substrate |
| WO2015043083A1 (en) * | 2013-09-25 | 2015-04-02 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method therefor, and display device |
| CN103489892B (en) * | 2013-09-25 | 2016-04-13 | 北京京东方光电科技有限公司 | A kind of array base palte and preparation method thereof and display unit |
| WO2016179940A1 (en) * | 2015-05-12 | 2016-11-17 | 京东方科技集团股份有限公司 | Oled pixel unit, transparent display apparatus and manufacturing method, and display device |
| US10002847B2 (en) | 2015-05-12 | 2018-06-19 | Boe Technology Group Co., Ltd. | OLED pixel unit, transparent display device, method for fabricating the same, display apparatus |
| CN114628409A (en) * | 2022-03-17 | 2022-06-14 | 京东方科技集团股份有限公司 | Display substrate, preparation method thereof and display panel |
| CN118844130A (en) * | 2023-02-24 | 2024-10-25 | 京东方科技集团股份有限公司 | Array substrate and display device |
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