CN203466192U - Array substrate and display device - Google Patents
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- CN203466192U CN203466192U CN201320598851.1U CN201320598851U CN203466192U CN 203466192 U CN203466192 U CN 203466192U CN 201320598851 U CN201320598851 U CN 201320598851U CN 203466192 U CN203466192 U CN 203466192U
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Abstract
本实用新型属于显示技术领域，具体涉及一种阵列基板以及显示装置。一种阵列基板，包括基板以及设置于所述基板上的薄膜晶体管和驱动电极，所述薄膜晶体管包括栅极、栅绝缘层、有源层、源极和漏极，所述驱动电极包括不同层设置、且在正投影方向上至少部分重叠的狭缝电极和板状电极，所述源极、所述漏极与所述有源层为部分共底面结构，所述薄膜晶体管与所述板状电极之间还设置有树脂层。由于源极、漏极与有源层采用共面结构，且第一保护层与有源层的图形完全重合，省略了刻蚀阻挡层；板状电极设置在树脂层厚度较大的区域且与树脂层在同时形成，结构更紧凑；在制备过程中能节省三次构图工艺，不仅简化了工艺，极大地提高了产能，还节约了成本。
The utility model belongs to the field of display technology, in particular to an array substrate and a display device. An array substrate, including a substrate and a thin film transistor and a driving electrode arranged on the substrate, the thin film transistor includes a gate, a gate insulating layer, an active layer, a source and a drain, and the driving electrode includes different layers The slit electrode and the plate-shaped electrode are arranged and at least partially overlap in the direction of the orthographic projection, the source electrode, the drain electrode and the active layer have a part of the same bottom structure, and the thin film transistor and the plate-shaped electrode A resin layer is also provided between the electrodes. Since the source electrode, the drain electrode and the active layer adopt a coplanar structure, and the patterns of the first protective layer and the active layer are completely overlapped, the etching stopper layer is omitted; The resin layer is formed at the same time, and the structure is more compact; in the preparation process, three patterning processes can be saved, which not only simplifies the process, greatly improves the production capacity, but also saves costs.
Description
Technical field
The utility model belongs to Display Technique field, is specifically related to a kind of array base palte and display unit.
Background technology
Along with scientific and technical development, panel display apparatus has replaced heavy CRT (Cathode Ray Tube, cathode ray tube) display unit to be goed deep in daily life day by day.Plasma display system) and OLED(Organic Light-Emitting Diode liquid crystal indicator), PDP(Plasma Display Panel at present, conventional panel display apparatus comprises LCD(Liquid Crystal Display::: Organic Light Emitting Diode) display unit.
Wherein, LCD and active matrix drive type OLED(Active Matrix Organic Light Emission Display, be called for short AMOLED) in display unit all by being integrated in thin-film transistor (Thin Film Transistor: be called for short TFT) in array base palte as control device, thereby realize image, show.Wherein, thin-film transistor mainly comprises grid, gate insulation layer, active layer, source electrode and drain electrode.
At present, active layer adopts material or metal oxide semiconductor material to form conventionally.Adopt metal oxide semiconductor material as active layer, thin-film transistor has good ON state current, switching characteristic, and mobility is high, good uniformity, do not need to increase compensating circuit, can be used for the fast application of response and larger electric current of needs, as be applied to high frequency, high-resolution, in large-sized LCD and OLED display unit.Meanwhile, the manufacture craft that metal oxide semiconductor material forms active layer is simple, adopts the methods such as sputter, good with existing LCD product line matching, easily transition, does not need to increase extra equipment, has cost advantage.
Along with the demand that people show high pixel (high PPI), also impel array base palte to improve, there is increasing at present the structure of resin bed in array base palte, resin bed is arranged on the top of data wire.Resin bed can reduce the use of integrated capacitance, is therefore conducive to improve the aperture opening ratio of array base palte, and effective pixel area is increased; Also reduced logic power consumption, greatly reduced power consumption, improved the performance of product, make to go a step further before high pixel (high PPI) demonstration simultaneously.
A Typical Representative of high picture display device is a senior super dimension switch technology ADSDS(ADvanced Super Dimension Switch, is called for short ADS) liquid crystal indicator.In ADS type array base palte, generally include pixel electrode layer and the common electrode layer that is positioned at liquid crystal cell the same side, the electric field that pixel electrode layer and public electrode interlayer produce, all liquid crystal molecules in liquid crystal cell can both be deflected, thereby improved liquid crystal operating efficiency and increased visual angle.But, adopt at present metal oxide semiconductor material as active layer and increase the ADS type array base palte of resin bed, in preparation technology, generally need nine composition techniques.Nine times composition technique is respectively: on substrate, deposit grid conductive film, adopt composition technique for the first time to form grid; On grid, deposit gate insulation layer, on gate insulation layer, deposit active layer, adopt composition technique for the second time to form the figure that comprises active layer; Above active layer, form etching barrier layer film, adopt composition technique for the third time to form the figure that comprises etching barrier layer; Sedimentary origin leakage conductance conductive film above etching barrier layer, adopts the 4th composition technique to form the figure that comprises source electrode, drain electrode; Above source electrode, drain electrode, form the first passivation tunic, adopt the 5th composition technique to form the figure of the first passivation layer and the via hole in the first passivation layer; Above the first passivation layer, form resin tunic, adopt the 6th composition technique to form the figure that comprises resin bed; Above resin bed, form the first electrode tunic, adopt the 7th composition technique to form plate electrode; Above plate electrode, form the second passivation tunic, adopt the 8th composition technique to form and comprise the figure of the second passivation layer and the via hole in the second passivation layer; Above the second passivation layer, form the second electrode lay film, adopt the 9th composition technique to form gap electrode.
Visible, increased after resin bed, although improved the aperture opening ratio of array base palte, and reduced to a certain extent power consumption, improved the performance of product, also make the complicated process of preparation of array base palte simultaneously, reduced production capacity and product yield.
Utility model content
Technical problem to be solved in the utility model is for above shortcomings in prior art, and a kind of array base palte and display unit are provided, and this array base-plate structure is compact, preparation method only comprises composition technique six times, simplify technique, improved production capacity, saved cost.
The technical scheme that solution the utility model technical problem adopts is this array base palte, comprise substrate and be arranged at thin-film transistor and the drive electrode on described substrate, described thin-film transistor comprises grid, gate insulation layer, active layer, source electrode and drain electrode, described drive electrode comprises different layers setting and at least part of overlapping gap electrode and plate electrode in orthographic projection direction, wherein, described source electrode, described drain electrode and described active layer are part bottom surface structure altogether, between described thin-film transistor and described plate electrode, are also provided with resin bed.
Preferably, described grid is arranged at described substrate top, described grid top arranges described gate insulation layer, interval, described gate insulation layer top arranges described source electrode and described drain electrode, and described source electrode, described drain electrode partly overlap in orthographic projection direction with described grid respectively, described active layer is arranged in the spacer region that described source electrode and described drain electrode form and extends to respectively the top of described source electrode and the described drain electrode of part, and the bottom surface of described source electrode, described drain electrode and the described active layer of part is all arranged on described gate insulation layer end face.
Preferably, the top of described active layer is provided with the first protective layer, and described the first protective layer and described active layer are completely overlapping in orthographic projection direction; Described resin bed is arranged at the top of described the first protective layer; described plate electrode is arranged at the top of described resin bed; the thickness that described resin bed correspondence the region that is provided with plate electrode is greater than the thickness in other regions; the top of described plate electrode is provided with the second protective layer, and described gap electrode is arranged at the top of described the second protective layer.
Preferably, described plate electrode is public electrode, and described gap electrode is pixel electrode, or described plate electrode is pixel electrode, described gap electrode is public electrode, described array base palte also comprises the public electrode wire arranging with layer with described grid, the region that described resin bed correspondence described drain electrode offers the first via hole, the region of corresponding described public electrode wire offers the second via hole, the region that described the second protective layer correspondence described drain electrode offers the 3rd via hole, the region that described gate insulation layer correspondence described public electrode wire offers the 4th via hole, described pixel electrode is electrically connected to described drain electrode by described the first via hole and described the 3rd via hole, described public electrode is electrically connected to described public electrode wire by described the second via hole and described the 4th via hole.
Preferably, described resin bed adopts organic resin to form, and described organic resin comprises acrylic compounds film-forming resin, phenolic resins class film-forming resin, and polyvinyl film-forming resin or poly-imines film-forming resin, the thickness range of described resin bed is 900-2100nm;
Described active layer adopts metal oxide semiconductor material to form, and described metal oxide semiconductor material comprises indium oxide gallium zinc, indium oxide, zinc oxide or tin indium oxide zinc, and the thickness range of described active layer is 20-60nm.
Preferably, described grid, described public electrode wire adopt molybdenum, molybdenum niobium alloy, aluminium, aluminium neodymium alloy, titanium, chromium or copper to form; Described grid, described public electrode wire are single or multiple lift composite lamainated structure, and the thickness range of described grid, described public electrode wire is 100-500nm;
Described source electrode and described drain electrode adopt indium oxide gallium zinc, indium zinc oxide, tin indium oxide or indium oxide gallium tin to form, and the thickness range of described source electrode and described drain electrode is 100-500nm.
Preferably, described pixel electrode adopts indium oxide gallium zinc, indium zinc oxide, tin indium oxide or indium oxide gallium tin to form, and the thickness range of described pixel electrode is 20-110nm; Described public electrode adopts indium oxide gallium zinc, indium zinc oxide, tin indium oxide or indium oxide gallium tin to form, and the thickness range of described public electrode is 20-60nm.
Preferably; described the first protective layer and described the second protective layer are single or multiple lift composite lamainated structure; adopt Si oxide, silicon nitride, hafnium oxide or aluminum oxide to form; the thickness range of described the first protective layer is 90-210nm, and the thickness range of described the second protective layer is 190-310nm.
A display unit, comprises above-mentioned array base palte.
The beneficial effects of the utility model are: in array base palte of the present utility model, because source electrode, drain electrode and active layer adopt coplanar structure, and the first protective layer overlaps completely with the figure of active layer, omitted etching barrier layer; Plate electrode is arranged on the region that resin layer thickness is larger and forms at the same time more compact structure with resin bed; In preparation process, can save composition technique three times, not only simplify technique, greatly improve production capacity, also save cost.
Accompanying drawing explanation
Figure 1A is the plane graph of array base palte in the utility model embodiment 1;
Figure 1B is the cutaway view of A-A cutting line in corresponding Figure 1A;
Fig. 2 A-2F is the preparation flow figure of array base palte in Figure 1A and Figure 1B;
Wherein:
Fig. 2 A is for forming the cutaway view of the figure that comprises grid;
Fig. 2 B-1, Fig. 2 B-2 are for forming the cutaway view of the figure that comprises gate insulation layer, source electrode and drain electrode;
Wherein:
Fig. 2 B-1 is for forming the cutaway view of gate insulation layer;
Fig. 2 B-2 is for forming the cutaway view of the figure that comprises source electrode and drain electrode;
Fig. 2 C is for forming the cutaway view of the figure that comprises active layer and the first protective layer;
Fig. 2 D-1 to Fig. 2 D-3 is for forming the cutaway view of the figure that comprises resin bed and plate electrode;
Wherein:
Fig. 2 D-1 is for forming the cutaway view of resin tunic and the first conduction tunic;
Fig. 2 D-2 is for to resin tunic and the first schematic diagram of exposing of conduction tunic;
Fig. 2 D-3 is for forming the cutaway view of the figure that comprises resin bed and via hole wherein and plate electrode;
Fig. 2 E is for forming the cutaway view of the figure that comprises the second protective layer;
Fig. 2 F is for forming the cutaway view of the figure that comprises gap electrode;
Fig. 3 is the structural representation of array base palte in the utility model embodiment 2;
Reference numeral: 1-substrate; 2-grid; 3-gate insulation layer; 4-source electrode; 5-drain electrode; 6-active layer; 7-the first protective layer; 8-resin bed; 80-resin material tunic; 9-plate electrode; 90-the first conduction tunic; 10-the second protective layer; 11-gap electrode; 12-public electrode wire; 131-the first via hole; 132-the second via hole; 133-the 3rd via hole; 134-the 4th via hole; 14-is communicated with electrode; 15-grid line; 16-data wire.
Embodiment
For making those skilled in the art understand better the technical solution of the utility model, below in conjunction with the drawings and specific embodiments, the utility model array base palte and display unit are described in further detail.
A kind of array base palte, comprise substrate and be arranged at thin-film transistor and the drive electrode on described substrate, described thin-film transistor comprises grid, gate insulation layer, active layer, source electrode and drain electrode, described drive electrode comprises different layers setting and at least part of overlapping gap electrode and plate electrode in orthographic projection direction, wherein, described source electrode, described drain electrode and described active layer are part bottom surface structure altogether, between described thin-film transistor and described plate electrode, are also provided with resin bed.
A display unit, comprises above-mentioned array base palte.
Embodiment 1:
A kind of array base palte, comprise substrate and be arranged at thin-film transistor and the drive electrode on substrate, thin-film transistor comprises grid, gate insulation layer, active layer, source electrode and drain electrode, drive electrode comprises different layers setting and at least part of overlapping gap electrode and plate electrode in orthographic projection direction, wherein, source electrode, drain electrode and active layer are part bottom surface structure altogether, between thin-film transistor and plate electrode, are provided with resin bed.
As shown in FIG. 1A and 1B, grid 2 is placed in substrate 1 top, grid 2 tops arrange gate insulation layer 3, gate insulation layer 3 intervals, top arrange source electrode 4 and drain electrode 5, and source electrode 4, draining 5 partly overlaps in orthographic projection direction with grid 2 respectively, active layer is established 6 and is placed in the spacer regions that source electrode 4 and drain electrode 5 form and extends to respectively drain 5 top of source electrode 4 and part, make source electrode 4, drain 5 and the bottom surface of part active layer 6 be all arranged on gate insulation layer 3 end faces.Wherein, the whole layer of gate insulation layer 3 is arranged at the top of grid 2; Meanwhile, for ease of thin-film transistor (for example: drain electrode) and drive electrode (for example: being connected pixel electrode), preferably active layer 6 only part cover the top of drain electrode 5, the part that makes to expose drains and 5 is convenient to be electrically connected to pixel electrode; And active layer 6 can partly cover or cover completely the top of source electrode 4.
The top of active layer 6 is provided with the first protective layer 7; the first protective layer 7 is completely overlapping in orthographic projection direction with active layer 6; the first protective layer 7 makes active layer 6 not be subject to the impact of the resin bed of follow-up setting; be convenient to again the first protective layer 7 and active layer 6 and form in same composition technique, and be convenient to the formation of the via hole of the follow-up connection for thin-film transistor and drive electrode.
Resin bed 8 is arranged at the top of the first protective layer 7; plate electrode 9 is arranged at the top of resin bed 8; the thickness that resin bed 8 correspondences the region that is provided with plate electrode 9 is greater than the thickness in other regions; the top of plate electrode 9 is provided with the second protective layer 10, and gap electrode 11 is arranged at the top of the second protective layer 10.
As shown in FIG. 1A and 1B, array base palte also comprises the public electrode wire 12 arranging with layer with grid 2.In the present embodiment, plate electrode 9 is public electrode, the region that resin bed 8 correspondences public electrode wire 12 offers the second via hole 132(because wherein having embedded connection electrode 14, therefore in Figure 1A, specifically do not identify), the region that gate insulation layer 3 correspondences public electrode wire 12 offers the 4th via hole (because wherein having embedded connection electrode 14, therefore in Figure 1A, specifically do not identify), public electrode is electrically connected to public electrode wire 12 by the second via hole 132 and the 4th via hole 134; Gap electrode 11 is pixel electrode; the region that resin bed 8 correspondences drain electrode 5 offers the first via hole 131(because wherein having embedded pixel electrode; therefore in Figure 1A, specifically do not identify); the region that the second protective layer 10 correspondences drain electrode 5 offers the 3rd via hole (because wherein having embedded pixel electrode; therefore in Figure 1A, specifically do not identify), pixel electrode is electrically connected to drain electrode 5 by the first via hole 131 and the 3rd via hole 133.
The array base palte of said structure can reduce the integrated capacitance between data wire 16 and public electrode effectively, improves the stability of array base palte.
Accordingly, the preparation method of above-mentioned array base palte, be included in the step that forms thin-film transistor and drive electrode on substrate, thin-film transistor comprises grid, gate insulation layer, active layer, source electrode and drain electrode, drive electrode is included at least part of overlapping gap electrode and plate electrode in orthographic projection direction, wherein, source electrode, drain electrode and active layer adopt twice composition technique forming section to be total to bottom surface structure, between thin-film transistor and plate electrode, be also formed with resin bed, resin bed and plate electrode adopt a composition technique to form.
Before concrete elaboration, it should be understood that in the utility model, composition technique, can only include photoetching process, or comprises photoetching process and etch step, and can also comprise printing, ink-jet etc. other are used to form the technique of predetermined pattern simultaneously; Photoetching process, refers to that utilize photoresist, mask plate, the exposure machine etc. of technical processs such as comprising film forming, exposure, development form the technique of figure.Can be according to the corresponding composition technique of formed structure choice in the utility model.
Concrete, the method specifically comprises the steps:
Step S1: adopt composition technique one time, form the figure that comprises grid on substrate.
As shown in Figure 2 A, on substrate 1, form gate electrode metal film, adopt a composition technique to form the figure that comprises grid 2.Wherein, adopt the method for deposition, sputter (comprising magnetron sputtering) or thermal evaporation on substrate 1, to form gate electrode metal film.
Further, when formation comprises the figure of grid 2, be also formed with public electrode wire 12 and grid line 15(please refer to Figure 1A, not shown in Fig. 2 A), public electrode wire 12 is waited until in subsequent technique and is formed after public electrode, is electrically connected to public electrode; Grid line 15 is electrically connected to grid 2, no longer describes in detail here.
Preferably, at least one formation that grid 2, public electrode wire 12, grid line 15 adopt in molybdenum (Mo), molybdenum niobium alloy (MoNb), aluminium (Al), aluminium neodymium alloy (AlNd), titanium (Ti), chromium (Cr) or copper (Cu); Grid 2, public electrode wire 12 and grid line 15 are single or multiple lift composite lamainated structure, and the thickness range of described grid 2, described public electrode wire 12 and grid line 15 is 100-500nm, more preferably 200-400nm.
Step S2: form gate insulation layer on the described substrate of completing steps S1, adopt composition technique one time, form the figure that comprises source electrode and drain electrode above gate insulation layer, source electrode arranges with drain electrode interval.
As shown in Fig. 2 B-1, in this step, on the substrate 1 of completing steps S1, form gate insulation layer film, above grid 2, form gate insulation layer 3.Then, as shown in Fig. 2 B-2, adopt the methods such as deposition, sputter (comprising magnetron sputtering) or thermal evaporation above gate insulation layer 3, to form source-drain electrode metallic film, adopt a composition technique to form the figure that comprises source electrode 4 and drain electrode 5 simultaneously, source electrode 4 arranges with drain electrode 5 intervals.
Wherein, using plasma strengthens chemical vapour deposition technique (Plasma Enhanced Chemical Vapor Deposition: be called for short PECVD) and forms gate insulation layer 3, at least one formation that gate insulation layer 3 adopts in Si oxide (SiOx), silicon nitride (SiNx), hafnium oxide (HfOx), silicon nitrogen oxide (SiON) or aluminum oxide (AlOx).Gate insulation layer 3 is single or multiple lift composite lamainated structure, and the thickness range of gate insulation layer 3 is 200-500nm, more preferably 300-400nm.
Here it should be understood that, because the general transparent material (Si oxide, silicon nitride, hafnium oxide, silicon nitrogen oxide, aluminum oxide) that adopts of gate insulation layer 3 forms, to the observation of plane graph, can not cause obstruction, therefore in the floor map of Figure 1A, omit the signal (the first protective layer, the second protective layer are same therewith) of gate insulation layer 3; Meanwhile, for ease of the position relationship between each layer of structure and each layer in understanding array base palte, each in plane Figure 1A layer is set to have certain transparency.
Step S3: on the substrate of completing steps S2; adopt one time composition technique; formation comprises the figure of active layer and the first protective layer; active layer is arranged in the spacer region that source electrode and drain electrode form and extends to respectively the top that source electrode and part drain; the bottom surface of source electrode, drain electrode and part active layer forming section coplanar structure on gate insulation layer end face, the first protective layer and active layer are completely overlapping in orthographic projection direction.
As shown in Figure 2 C; in this step; on the substrate of completing steps S2, adopt the methods such as deposition, sputter (comprising magnetron sputtering) or thermal evaporation to form active layer film, then using plasma strengthens chemical vapour deposition technique and on active layer film, forms the first protective layer film.In the present embodiment, active layer 6 and the first protective layer 7 are in source electrode 4, the formation after 5 that drains, and active layer 6 adopts wet etchings to form, and the first protective layer 7 adopts dry etchings to form, and active layer 6 is identical with the figure of the first protective layer 7.The structure of array base palte compared to existing technology, the setting that can omit etching barrier layer, has also correspondingly reduced the composition technique that forms the figure that comprises etching barrier layer.
Wherein, active layer 6 adopts metal oxide semiconductor material to form, and metal oxide semiconductor material comprises indium oxide gallium zinc (IGZO), indium oxide (In
2o
3), at least one in zinc oxide (ZnO) or tin indium oxide zinc (ITZO), the thickness range of active layer 6 is 20-60nm, more preferably 30-50nm.Here it should be understood that metal oxide semiconductor material comprises by the material that comprises the elements such as indium (In), gallium (Ga), zinc (Zn), oxygen (O), tin (Sn) makes, and wherein must comprise two or more element of oxygen element and other.
The first protective layer 7 is single or multiple lift composite lamainated structure, adopts at least one formation in Si oxide, silicon nitride, hafnium oxide or aluminum oxide, and the thickness range of the first protective layer 7 is 90-210nm, more preferably 100-200nm.
Step S4: on the substrate of completing steps S3, adopt composition technique one time, form the figure comprise resin bed and plate electrode, the thickness that resin bed correspondence the region that is provided with plate electrode is greater than the thickness in other regions.
In the present embodiment, plate electrode is public electrode.This step S4 specifically comprises:
Step S41: form resin material tunic on the substrate of completing steps S3, and form the first conduction tunic on resin material tunic.
As shown in Fig. 2 D-1, adopt (the comprising spin coating) method of coating at the upper formation resin material tunic 80 of the first protective layer 7, then adopt the method for deposition, sputter (comprising magnetron sputtering) or thermal evaporation to form the first conduction tunic 90.
Wherein, resin material tunic 80 adopts organic resin to form, wherein, organic resin comprises acrylic compounds film-forming resin, phenolic resins class film-forming resin, polyvinyl film-forming resin or poly-imines film-forming resin, the thickness range of resin material tunic 80 is 1000-2100nm, more preferably 1000-2000nm; The first conduction tunic 90 is used to form public electrode, at least one formation that the first conduction tunic 90 adopts in the transparent conductive materials such as indium oxide gallium zinc (IGZO), indium zinc oxide (IZO), tin indium oxide (ITO) or indium oxide gallium tin (InGaSnO), the thickness range of the public electrode forming is 20-60nm, more preferably 30-50nm.
Step S42: adopt gray mask plate or half-tone mask plate, resin material tunic 80 is exposed, the subregion that resin material tunic 80 drain electrode in correspondence is that resin material is removed district completely, corresponding the region that forms plate electrode is the complete reserved area of resin material, and other regions are resin material part reserved area.
Further, district is also removed completely for resin material in the subregion that resin material tunic 80 public electrode wire in correspondence.As shown in Fig. 2 D-2, in this step, by gray mask plate or half-tone mask plate, control the light transmission amount in exposure process, thereby control resin material tunic 80 degree of being exposed in zones of different, and then obtain the resin bed 8 of satisfactory different-thickness.
In Fig. 2 D-2, NP represents the complete reserved area of resin material, and HP represents resin material part reserved area, and WP represents that resin material removes district completely.The region that drain electrode 5 region and corresponding public electrode wire 12 in resin bed 8 correspondences is that resin material is removed district completely, so that be formed for pixel electrode and 5 via holes that are connected that drain, with the via hole that is formed for public electrode and is connected with public electrode wire 12.
Step S43: the substrate of completing steps S42 is developed, form the figure that comprises resin bed and plate electrode simultaneously.
As shown in Fig. 2 D-2 and 2D-3, in this step, the different situations that in corresponding step S42, resin material tunic 80 is removed or is retained, the resin material of respective regions is removed or is retained, thereby forms the figure that comprises resin bed 8.And then, due to be used to form the first conductive layer first conduction tunic 90 in transparent conductive material be attached to resin material tunic 80 tops, and the very thin thickness (for example 40nm) of the first conduction tunic 90, when resin material tunic 80 is removed, transparent conductive material attached thereto is also removed simultaneously, therefore, the plate electrode 9 finally being formed by the first conduction tunic 90 can form without etching technics, and the shape of plate electrode 9 is identical with the shape in the resin bed 8 larger regions of thickness.
, in step S4, by composition technique, resin bed 8 correspondences the thick 50-100nm of thickness in other regions of Thickness Ratio except the first via hole that form plate electrode 9, so that can effectively remove part the first conduction tunic 90 in the preparation technology of array base palte, form plate electrode, can guarantee the thickness between source electrode and drain electrode and plate electrode again, obtain good aperture opening ratio, at the first conduction tunic 90 that does not form the region of plate electrode 9, along with the removal of resin material tunic 80, be removed, also therefore formed the thickness difference of resin bed 8 in zones of different.Further, the region that drain electrode 5 in resin bed 8 correspondences is formed with the first via hole 131, and the region that the while public electrode wire 12 in correspondence is formed with the second via hole 132.
Step S5: on the substrate of completing steps S4, adopt composition technique one time, form the figure that comprises the second protective layer.
As shown in Figure 2 E, in this step, on the substrate of completing steps S4, using plasma strengthens chemical vapour deposition technique and on resin bed 8, forms the second protective layer film; Then, adopt composition technique one time, form the figure that comprises the second protective layer 10.
At least one formation that the second protective layer 10 adopts in Si oxide, silicon nitride, hafnium oxide or aluminum oxide.The second protective layer 10 is single or multiple lift composite lamainated structure, and the thickness range of the second protective layer 10 is 190-310nm, more preferably 200-300nm.
In this step, the second protective layer 10 in correspondence that drain electrode 5 region offers the 3rd via hole 133, the three via holes 133 and the first via hole 131 is overlapping at least partly in orthographic projection direction, preferably completely overlapping; Meanwhile, the second protective layer film correspondence public electrode and is removed near the part of public electrode wire 12 1 sides, to expose part public electrode, so that being electrically connected to of follow-up public electrode and public electrode wire 12.
In this step, also simultaneously in gate insulation layer 3 region of corresponding public electrode wire 12 formed the 4th via hole 134, the second via holes 132 and the 4th via hole 134 overlapping at least partly in orthographic projection direction, preferably completely overlapping.
Step S6: on the substrate of completing steps S5, adopt composition technique one time, form the figure that comprises gap electrode.
In the present embodiment, gap electrode 11 is pixel electrode.In this step, adopt the method for deposition, sputter (comprising magnetron sputtering) or thermal evaporation to form electrically conducting transparent tunic.
As shown in Figure 2 F, in this step, formed the pixel electrode that slit-shaped distributes, pixel electrode is electrically connected to drain electrode 5 by the first via hole 131 and the 3rd via hole 133; Meanwhile, after completing, in the second via hole 132 and the 4th via hole 134, formed connection electrode 14 in this step, be communicated with electrode 14 and make the public electrode forming at step S4 be able to link together with public electrode wire 12 by being communicated with electrode 14.
In the present embodiment, at least one formation that pixel electrode and connection electrode 14 adopt in the transparent conductive materials such as indium oxide gallium zinc (IGZO), indium zinc oxide (IZO), tin indium oxide (ITO) or indium oxide gallium tin (InGaSnO), the thickness range of pixel electrode is 20-110nm, more preferably 30-100nm.
In the present embodiment, owing to forming the active layer of thin-film transistor, adopted metal oxide semiconductor material, electron mobility between source electrode and drain electrode is increased, therefore can obtain the electron mobility between good source electrode and drain electrode, improved the switching characteristic of thin-film transistor.And, owing to being provided with resin bed between thin-film transistor and plate electrode, therefore can greatly reduce integrated capacitance (for example, the integrated capacitance between data wire and public electrode), thereby reduce logic power consumption, greatly reduced product overall power; Meanwhile, resin bed also helps the aperture opening ratio that improves array base palte, and effective pixel area is increased, and has improved the performance of product.Meanwhile, in the preparation technology of corresponding array base palte, resin bed and plate electrode utilize a composition technique (only using mask plate one time) to complete, not only simplified technique, greatly improve production capacity, also saved cost, and be conducive to the raising of product yield.
Embodiment 2:
In the present embodiment, the setting of the plate electrode in array base palte and gap electrode is different from embodiment 1.
As shown in Figure 3, in the present embodiment, gap electrode 11 is public electrode, the region that resin bed 8 correspondences public electrode wire 12 offers the second via hole, the region that gate insulation layer 3 correspondences public electrode wire 12 offers the 4th via hole, and public electrode is electrically connected to public electrode wire 12 by the second via hole and the 4th via hole; Plate electrode 9 is pixel electrode, and the region that resin bed 8 correspondences drain electrode 5 offers the first via hole, and the region that the second protective layer 10 correspondences drain electrode 5 offers the 3rd via hole, and pixel electrode is electrically connected to drain electrode 5 by the first via hole and the 3rd via hole.
Accordingly, the preparation method of above-mentioned array base palte specifically comprises the steps:
Step S1: adopt composition technique one time, form the figure that comprises grid on substrate.
Identical with embodiment 1, in this step, also form the figure that comprises public electrode wire 12 simultaneously.
Step S2: form gate insulation layer on the substrate of completing steps S1, adopt composition technique one time, form the figure that comprises source electrode and drain electrode above gate insulation layer, source electrode arranges with drain electrode interval.
Step S3: on the substrate of completing steps S2; adopt one time composition technique; formation comprises the figure of active layer and the first protective layer; active layer is arranged in the spacer region that source electrode and drain electrode form and extends to respectively the top that source electrode and part drain; the bottom surface of source electrode, drain electrode and part active layer forming section coplanar structure on gate insulation layer end face, the first protective layer and active layer are completely overlapping in orthographic projection direction.
Step S4: on the substrate of completing steps S3, adopt composition technique one time, form the figure comprise resin bed and plate electrode, the thickness that resin bed correspondence the region that is provided with plate electrode is greater than the thickness in other regions.
In this step, the region that resin bed drain electrode in correspondence offers the first via hole, and the region that public electrode wire in correspondence offers the second via hole.
Step S5: on the substrate of completing steps S4, adopt composition technique one time, form the figure that comprises the second protective layer.
In this step, also in the second protective layer correspondence, the region draining simultaneously and offer the 3rd via hole, the region that public electrode wire in correspondence offers the 4th via hole.
Step S6: on the described substrate of completing steps S5, adopt composition technique one time, form the figure that comprises gap electrode.
In this step, pixel electrode is electrically connected to drain electrode by the first via hole and the 3rd via hole, and public electrode is electrically connected to public electrode wire by the second via hole and the 4th via hole.
In the present embodiment, other structures of array base palte and other steps in array base palte preparation technology are identical with embodiment 1, repeat no more here.
In array base palte in embodiment 1,2, adopt compared to existing technology metal oxide semiconductor material as active layer and increase the array base palte of resin bed, owing to having adopted source electrode, drain electrode and active layer for being partly total to bottom surface structure, and the first protective layer overlaps completely with active layer area, therefore the setting that can omit etching barrier layer, and active layer and the first protective layer can, by form with a composition technique simultaneously, reduce composition technique twice; And resin bed and plate electrode are by form (plate electrode forms in to the exposure of resin bed, developing process) with a composition technique simultaneously simultaneously, do not need plate electrode to implement separately composition technique, reduced again composition technique one time.Therefore, in the present embodiment, adopt metal oxide semiconductor material as active layer and increase the array base palte of resin bed, compared to existing technology, adopt metal oxide semiconductor material as active layer and increase the array base palte of resin bed, more compact structure, be specially adapted to high pixel, the product of high aperture, low-power consumption; Meanwhile, this array base palte has reduced three composition techniques (only needing the preparation that six times composition technique can complete whole array base palte) in preparation technology, has not only simplified technique, has greatly improved production capacity, has saved cost, is conducive to the raising of product yield.
Embodiment 3:
The present embodiment provides a kind of display unit, and this display unit comprises array base palte arbitrary in embodiment 1 or 2.
Wherein, this display unit can be: any product or parts with Presentation Function such as liquid crystal panel, Electronic Paper, mobile phone, panel computer, television set, display, notebook computer, DPF, navigator.
Here it should be understood that, in the present embodiment in the array base palte of display unit, comprise different layers setting, and at least part of overlapping gap electrode and plate electrode in orthographic projection direction, also be ADSDS(ADvanced Super Dimension Switch, a senior super dimension switch technology) pattern, the operation principle of the display unit of this pattern is: the electric field producing by electric field that in same plane, gap electrode edge produces and gap electrode layer and plate electrode interlayer forms multi-dimensional electric field, make between the interior gap electrode of liquid crystal cell, directly over electrode, all aligned liquid-crystal molecules can both produce rotation, thereby improved liquid crystal molecule operating efficiency and increased light transmission efficiency.A senior super dimension switch technology can improve the picture quality of LCD product, has high-resolution, high permeability, low-power consumption, wide visual angle, high aperture, low aberration, without advantages such as water of compaction ripples (push Mura).
Be understandable that, above execution mode is only used to principle of the present utility model is described and the illustrative embodiments that adopts, yet the utility model is not limited to this.For those skilled in the art, in the situation that not departing from spirit of the present utility model and essence, can make various modification and improvement, these modification and improvement are also considered as protection range of the present utility model.
Claims (9)
1. an array base palte, comprise substrate and be arranged at thin-film transistor and the drive electrode on described substrate, described thin-film transistor comprises grid, gate insulation layer, active layer, source electrode and drain electrode, described drive electrode comprises different layers setting and at least part of overlapping gap electrode and plate electrode in orthographic projection direction, it is characterized in that, described source electrode, described drain electrode and described active layer are part bottom surface structure altogether, between described thin-film transistor and described plate electrode, are also provided with resin bed.
2. array base palte according to claim 1, it is characterized in that, described grid is arranged at described substrate top, described grid top arranges described gate insulation layer, interval, described gate insulation layer top arranges described source electrode and described drain electrode, and described source electrode, described drain electrode partly overlaps in orthographic projection direction with described grid respectively, described active layer is arranged in the spacer region of described source electrode and described drain electrode formation, and extend to respectively the top of described source electrode and the described drain electrode of part, make described source electrode, the bottom surface of described drain electrode and the described active layer of part is all arranged on described gate insulation layer end face.
3. array base palte according to claim 2, is characterized in that, the top of described active layer is provided with the first protective layer, and described the first protective layer and described active layer are completely overlapping in orthographic projection direction; Described resin bed is arranged at the top of described the first protective layer; described plate electrode is arranged at the top of described resin bed; the thickness that described resin bed correspondence the region that is provided with plate electrode is greater than the thickness in other regions; the top of described plate electrode is provided with the second protective layer, and described gap electrode is arranged at the top of described the second protective layer.
4. array base palte according to claim 3, is characterized in that, described plate electrode is public electrode, and described gap electrode is pixel electrode, or described plate electrode is pixel electrode, described gap electrode is public electrode, described array base palte also comprises the public electrode wire arranging with layer with described grid, the region that described resin bed correspondence described drain electrode offers the first via hole, the region of corresponding described public electrode wire offers the second via hole, the region that described the second protective layer correspondence described drain electrode offers the 3rd via hole, the region that described gate insulation layer correspondence described public electrode wire offers the 4th via hole, described pixel electrode is electrically connected to described drain electrode by described the first via hole and described the 3rd via hole, described public electrode is electrically connected to described public electrode wire by described the second via hole and described the 4th via hole.
5. array base palte according to claim 4, it is characterized in that, described resin bed adopts organic resin to form, described organic resin comprises acrylic compounds film-forming resin, phenolic resins class film-forming resin, polyvinyl film-forming resin or poly-imines film-forming resin, the thickness range of described resin bed is 900-2100nm;
Described active layer adopts metal oxide semiconductor material to form, and described metal oxide semiconductor material comprises indium oxide gallium zinc, indium oxide, zinc oxide or tin indium oxide zinc, and the thickness range of described active layer is 20-60nm.
6. array base palte according to claim 5, is characterized in that, described grid, described public electrode wire adopt molybdenum, molybdenum niobium alloy, aluminium, aluminium neodymium alloy, titanium, chromium or copper to form; Described grid, described public electrode wire are single or multiple lift composite lamainated structure, and the thickness range of described grid, described public electrode wire is 100-500nm;
Described source electrode and described drain electrode adopt indium oxide gallium zinc, indium zinc oxide, tin indium oxide or indium oxide gallium tin to form, and the thickness range of described source electrode and described drain electrode is 100-500nm.
7. array base palte according to claim 6, is characterized in that, described pixel electrode adopts indium oxide gallium zinc, indium zinc oxide, tin indium oxide or indium oxide gallium tin to form, and the thickness range of described pixel electrode is 20-110nm; Described public electrode adopts indium oxide gallium zinc, indium zinc oxide, tin indium oxide or indium oxide gallium tin to form, and the thickness range of described public electrode is 20-60nm.
8. array base palte according to claim 7; it is characterized in that; described the first protective layer and described the second protective layer are single or multiple lift composite lamainated structure; adopt Si oxide, silicon nitride, hafnium oxide or aluminum oxide to form; the thickness range of described the first protective layer is 90-210nm, and the thickness range of described the second protective layer is 190-310nm.
9. a display unit, is characterized in that, comprises the array base palte described in claim 1-8 any one.
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| CN201320598851.1U CN203466192U (en) | 2013-09-26 | 2013-09-26 | Array substrate and display device |
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| CN201320598851.1U CN203466192U (en) | 2013-09-26 | 2013-09-26 | Array substrate and display device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103489826A (en) * | 2013-09-26 | 2014-01-01 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method and display device |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103489826A (en) * | 2013-09-26 | 2014-01-01 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method and display device |
| WO2015043268A1 (en) * | 2013-09-26 | 2015-04-02 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method therefor, and display apparatus |
| CN103489826B (en) * | 2013-09-26 | 2015-08-05 | 京东方科技集团股份有限公司 | Array base palte, preparation method and display unit |
| US9373649B2 (en) | 2013-09-26 | 2016-06-21 | Boe Technology Group Co., Ltd. | Array substrate and method for manufacturing the same, and display device |
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