CN203456468U - Insulated gate bipolar transistor - Google Patents

Abstract

Disclosed in the utility model is an insulated gate bipolar transistor (IGBT) comprising an emitter, a main semiconductor body, and at least one groove. The main semiconductor body includes a first base region having a first conductive type, a source region having a second conductive type different from the first conductive type, and an anti-latch up region (P+) formed in the first base region. The source region and the first base region form a first pn node. And the anti-latch up region (P+) has at least one first portion that is arranged below the source region and is contacted with the source region; the anti-latch up region has the first conductive type; and the doping concentration is larger than that of the first base region. The at least one groove being filled with a gate electrode includes a first groove portion with a first width and a second groove portion with a second width, wherein the second width is different from the first width. According to the technical scheme, a latch-up effect can be prevented from occurring at an IGBT.

Description

Insulated Gate Bipolar Transistor

technical field

The utility model relates to a semiconductor device, in particular to an insulated gate bipolar transistor.

Background technique

Insulated Gate Bipolar Transistor (IGBT: Insulated Gate Bipolar Transistor) is a combination of Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET: Metal-Oxide-Semiconductor Field-Effect Transistor) and Bipolar Transistor (BJT: Bipolar Junction Transistor) The semiconductor device has the advantages of these two devices. It not only has the advantages of small driving power and fast switching speed of MOSFET, but also has the advantages of low saturation voltage drop and large current carrying capacity of BJT. Therefore, in recent years, IGBTs have been widely used in fields requiring power conversion such as AC motors, frequency converters, switching power supplies, lighting circuits, and traction drives.

FIG. 1 shows an example of a conventional IGBT. As shown in FIG. 1 , the IGBT100 is shown to have a trench gate field stop structure, which includes a p-type collector region 11, an n-type field stop region 12, an n-type drift region 13, a p-type base Region 14 and n+ type source region 15 , and gate 16 and gate oxide layer 17 formed in n − type drift region 13 , p type base region 14 and n+ type source region 15 .

Further, in the IGBT 100 shown in FIG. 1 , the gate 16 includes an upper gate 161 with a uniform cross-sectional width and a lower gate 162 with a cross-sectional width larger than that of the upper gate 161 . This structure can be called a partially narrow mesa (PNM: Partially Narrow Mesa) structure. In the paper "Low Loss IGBT with Partially Narrow Mesa Structure (PNM-IGBT)" published by Masakiyo Sumitomo and others at the 24th International Conference on Power Semiconductor Devices and Power Integrated Circuits (ISPSD: International Symposium on Power Semiconductor Devices and IC) in 2012 and An IGBT having a similar structure is described in Patent No. US7800187B2. By forming a local narrow mesa structure (the base region between two adjacent trench gates is narrowed) as shown in the dashed box in Figure 1, the mesa can be reduced without reducing the metal-semiconductor contact area width (the width of the base region between two adjacent trench gates), so that the saturation voltage of the IGBT100 is significantly reduced, and a good trade-off can also be obtained between the on-state voltage and the turn-off loss.

However, in the IGBT 100 shown in FIG. 1 , the narrowing of the mesa region increases the current density in this region. During the turn-off transition of the IGBT100, most or almost all of the current in this region is carried by holes, and the high hole current density will flow to the next P contact region, causing the current to flow through the p-type base region 14 located in the n+-type source A lateral voltage drop (lateral voltage drop) occurs in the part below the region 15. This voltage drop makes the parasitic thyristor of IGBT100 (with a PNPN structure composed of p-type collector region 11, n-type field stop region 12/n-type drift region 13, p-type base region 14 and n+ type source region 15) The NPN tube is turned on, which is more likely to happen especially during over-current-turn-off. As a result, a latch-up effect occurs on the IGBT100, the control capability of the equivalent MOSFET therein is reduced or even invalid, and the IGBT100 will eventually be damaged due to overheating.

The above-mentioned latch-up phenomenon may occur for an IGBT with a local narrow mesa structure, not only that, but also for a normal IGBT.

The second problem is: In PNM-IGBT, a high density of trenches is usually achieved. Therefore, each region of the PNM-IGBT has a large channel width and high channel conductivity. This means that during short-circuit operation, extremely high current densities flow through the device, accompanied by high collector-emitter voltages. This will cause the device to fail within a few microseconds.

The third problem is that the ends of the mesa structures will have corners or trenches that are rounded in some way. Due to geometrical reasons (it would be more effective if the gate was around the corner), due to different doping levels of the channel region (boron segregates into the gate oxide during oxidation, or on a different crystallographic plane) High temperature annealing is different in the plane), or due to different properties of the gate oxide, such as thickness or interface charge (these also depend on the individual crystal planes), in this region (mesa end region), the MOS channel threshold voltage will be different Higher (usually lower) voltages at the long sides of the mesa. This can lead to higher current densities or even long-term degradation and instability of the threshold voltage at the end of the mesa.

PNM-IGBTs are described in US6521538B2 and US7800187B2. However, no solution to the above technical problems has been proposed in the prior art. The structure shown in US7800187B2 has the following drawbacks: the contact with the n+ region and the spaced P-body region occupy a large area, which counteracts the basic idea of the PNM-IGBT, which is to achieve a very narrow mesa area , thus achieving a high carrier concentration in the n-base region in the on-state.

Utility model content

In view of the above problems, it is desirable to provide an IGBT device capable of avoiding at least one of the above disadvantages.

According to one aspect of the present invention, there is provided an insulated gate bipolar transistor, comprising: an emitter; and a semiconductor body, wherein the semiconductor body includes: a first base region having a first conductivity type; a source region having a second conductivity type different from the first conductivity type, and forming a first pn junction with the first base region; an anti-latch-up region, formed in the first base region, having at least one a first portion below and in contact with the source region, the anti-latch-up region having the first conductivity type and having a doping concentration greater than that of the first base region; and at least one trench, Wherein, the at least one trench is filled with a gate electrode, wherein the at least one trench has: a first trench portion having a first width; and a second trench portion having a second width; the first trench portion having a second width; The second width is different from the first width.

Preferably, a portion of the first base region is located laterally between the second portion of the anti-latch-up region and the at least one trench.

Preferably, a portion of the first base region is located laterally between the first portion of the anti-latch-up region and the at least one trench.

Preferably, the distance between the anti-latch-up region and the trench is 100nm-800nm.

Preferably, at least a part of the anti-latch-up region is in contact with an insulating portion of the at least one first trench, the insulating portion insulating the gate electrode from at least the source region and the first base region.

Preferably, the source region includes a first source region and a second source region, wherein the second portion of the anti-latch-up region and a portion of the surface of the first base region on the side of the emitter are located at the Between the surface of the first source region on the side of the emitter and the surface of the second source region.

Preferably, the width of the source region along the first direction is 0.5 μm-3 μm.

Preferably, the anti-latch-up region is formed with a groove, wherein the groove is filled with a portion of the emitter such that the emitter contacts the source region and the anti-latch-up region.

Preferably, the depth of the groove is at least equal to the depth of a pn junction between the first portion of the anti-latch-up region and the source region.

Preferably, said groove extends in the same direction as said at least one groove extends.

Preferably, a dielectric layer is located between said emitter and said semiconductor body;

The emitter includes: a first emitter portion overlying the dielectric layer; and a second emitter portion extending through the dielectric layer from the first emitter portion to the recess middle.

Preferably, the source region includes a first source region and a second source region respectively located on two sides of the second emitter portion.

Preferably, the second trench portion is disposed below the first trench portion along a vertical direction of the IGBT, wherein, in a lateral direction of the IGBT, the The second width is greater than the first width.

Preferably, the first width of the first groove portion is a uniform width along the first groove portion.

Preferably, the at least one trench includes an insulating portion insulating the gate electrode from at least the source region and the first base region.

Preferably, a pair of the gate trench and the source region define a mesa structure, and certain positions at the ends of the mesa structure have corner structures, chamfer structures or arc structures.

Preferably, the multiple positions of the anti-latch-up region extend to predetermined positions of the gate trench structure at predetermined intervals.

Preferably, the gate further includes: a gate trench connecting portion, which is perpendicular to the extending direction of the at least one gate trench and connects the two gate trenches.

Preferably, a predetermined portion of the anti-latch-up region extends to the connecting portion of the gate trench; or a predetermined portion of the anti-latch-up region extends to the connecting portion between the at least one trench and the gate trench formed corners.

Preferably, the insulated gate bipolar transistor is a trench gate field stop type insulated gate bipolar transistor.

Preferably, the insulated gate bipolar transistor further includes: a drift region having a second conductivity type different from the first conductivity type and located on the side opposite to the emitter side of the first base region , and form a second pn junction with the first base region; a collector region having the first conductivity type and located on a side of the second base region opposite to the side of the first base region; and a collector electrode in contact with the collector region.

Preferably, said at least one trench extends in said drift region.

Preferably, the IGBT further includes: a dielectric layer located between the emitter and the first base region; the emitter includes: a first emitter portion located at the above a dielectric layer; and a second emitter portion extending through the dielectric layer from the first emitter portion to the source region and forming a contact region with the source region.

Preferably, a contact region is provided between the emitter and the source region.

Preferably, the contact region contains selenium or sulfur atoms.

Preferably, the contact area is a barrier layer.

Preferably, the blocking layer includes at least one of Ti, Tiw, TiN, TaN.

Through the technical scheme of the utility model, the latch-up (Latchup) effect in the IGBT is effectively prevented; and the current density flowing through the device during short-circuit operation is reduced, and the life of the device is prolonged; the threshold voltage of the MOS channel is reduced or eliminated unstable.

Description of drawings

In the drawings, like reference characters in different views generally identify the same parts. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention. In the following description, various embodiments of the present utility model are described according to the following drawings, in the drawings:

FIG. 1 is a perspective view showing an example of a conventional IGBT;

2A is a cross-sectional view illustrating an IGBT according to an embodiment of the present invention;

FIG. 2B is a perspective view showing an IGBT according to an embodiment of the present invention.

Fig. 3 is a perspective view showing an IGBT according to a modified example of the present invention;

Fig. 4 is a perspective view showing an IGBT according to a modified example of the present invention;

5A, 5B and 5C are cross-sectional views illustrating IGBTs according to several other modified examples of the present invention; and

FIG. 6 is a cross-sectional view showing an IGBT according to another modified example of the present invention.

Detailed ways

The following detailed description refers to the accompanying drawings, which illustrate by way of illustration specific details and embodiments in which the invention may be practiced.

The word "on" may be used herein with reference to forming a material "on" a side or surface to mean that the material may be formed "directly" on said side or surface, e.g., in direct contact with it; Means that the material is formed "indirectly" on the side or surface with one or more additional layers between the side or surface and the material. Because components of an embodiment may be disposed in a variety of different orientations, directional terms are used for purposes of illustration only and are by no means limiting.

One of the cores of the invention is to prevent latch-up in the IGBT by using the region p+ (anti-latch-up region) below the source region.

In the embodiment of the present invention, a region p+ is inserted under the n+ source region, in order to reduce the resistance of the p region under the source region. Holes are thus able to flow through this high conductivity region to the emitter contact without causing an excessive voltage drop to forward bias the source-body-pn junction, thereby preventing latch-up.

Preferred embodiment:

1) In a preferred embodiment, the region p+ is contacted simultaneously with the n+ source region through a trench contact.

2) In the second preferred embodiment, the region P+ reaches the trench at some position at the end of the mesa. This can be a corner or at the very end of the countertop. At these locations, the p-doping under the source is so high that no MOS channel can form at gate voltages within the nominal range. Therefore, the above-mentioned problem of reduced or unstable MOS threshold voltage is solved.

3) In a third preferred embodiment, the regions P+ reach more or less regularly spaced locations along most of the mesa of the trench. This results in a considerable reduction of the channel width as well as the current flowing in short-circuit mode. Depending on the remaining active channel width, longer short durations can be achieved.

Describe in detail below with reference to accompanying drawing:

FIG. 2A is a cross-sectional view illustrating an IGBT according to an embodiment of the present invention. Referring to FIG. 2A, the IGBT200 is shown as having a trench gate field stop type structure, which includes a sequentially stacked collector electrode C, a p-type collector region 21, an n-type field stop region 22, and an n-type drift region 23; body, wherein the semiconductor body includes: a p-type base region 24 and an n+ type source region 25, and a gate 26 and a gate oxide formed in the n-type drift region 23, the p-type base region 24 and the n+ type source region 25 layer 27 , wherein the n+ type source region 25 forms a first pn junction with the first base region 24 . In addition, a dielectric layer (interlayer dielectric) 28 is formed on the upper surfaces of the p-type base region 24 , n+-type source region 25 , and gate 26 . Wherein, the n-type drift region 23 is located on the side opposite to the emitter side of the first base region 24 and forms a second pn junction with the first base region 24 .

The IGBT200 also includes at least one trench, wherein the at least one trench is filled with the gate electrode 26, wherein the at least one trench has: a first trench portion 261 (for convenience of illustration, filled in the first trench The first gate portion in the groove portion 261 is also indicated by the reference numeral 261 ), has a first width; and the second trench portion 262 (for the convenience of illustration, the second gate portion filled in the second trench portion section is also represented by reference numeral 262). The second trench portion 262 is disposed below the first trench portion 261 along the vertical direction of the IGBT 200 , wherein, in the lateral direction of the IGBT 200 , The second width is greater than the first width. The at least one trench extends in the drift region 23 .

The first width of the first groove portion 261 is a uniform width along the first groove portion.

The at least one trench includes an insulating portion 27 insulating the gate electrode 26 from at least the source region 25 and the first base region 24 .

IGBT 200 also has emitter 29 including first emitter portion 291 and second emitter portion 292 . The first emitter portion 291 is formed on the dielectric layer 28, in other words, the dielectric layer 28 is located between the emitter 29 and the semiconductor body. The second emitter portion 292 extends downwardly from the lower surface of the first emitter portion 291 through the dielectric layer 28 to be in contact with the n+ type source region 25 .

The collector region 21 has the first conductivity type and is located on the opposite side of the second base region (drift region 23 ) to the side of the first base region 24 ; the collector C is connected to the collector region 21 touch.

In this embodiment, a contact region P+ (anti-latch-up region) is also provided, formed in the p-type base region 24, at least a part of the contact region P+ is located under the source region 25 and connected to the source region 25 contact, the contact region P+ is P+ doped, and the doping concentration is greater than the doping concentration of the first base region 24 . At least a portion of the anti-latch-up region P+ is in contact with the insulating portion 27 of the at least one first trench.

Wherein, the anti-latch-up region P+ is in contact with the emitter 29 . The anti-latch-up region P+ has a second portion laterally adjacent to the source region 25 . A portion of the first base region is located laterally between the second portion of the anti-latch-up region P+ and the at least one trench.

Preferably, the distance between the anti-latch-up region P+ and the gate trench is 100nm-800nm.

At least a part of the anti-latch-up region P+ is in contact with the insulating portion 27 of the trench, and the insulating portion 27 insulates the gate electrode 26 from at least the source region 25 and the first base region 24 .

The source region 25 includes a first source region and a second source region, wherein the second part of the anti-latch-up region P+ and a part of the surface of the first base region 24 on the side of the emitter are located at the Between the surface of the first source region on the side of the emitter 29 and the surface of the second source region.

A pair of the gate trenches and the source region 25 defines a mesa structure, and certain positions at the ends of the mesa structure have corner structures, chamfer structures or arc structures. By providing the contact region P+, the resistance of the p region under the source region 25 can be reduced. Therefore, holes can flow through this high conductivity region to the emitter contact region (contact) without causing an excessive voltage drop in this region to forward bias the source-body region-pn junction, thereby preventing up the latch.

FIG. 2B is a perspective view showing an IGBT according to an embodiment of the present invention.

In FIG. 2B , for ease of observation, the dielectric layer between the emitter and the upper surface of the semiconductor is omitted.

In this embodiment, the source region 25 may include n sub-source regions, which are arranged on the first base region 24 along the first direction (ie, the direction perpendicular to the paper in the figure) at predetermined intervals, where n is an integer greater than or equal to 2.

The contact region P+ can be produced in different ways. If a planar contact to the semiconductor surface is used, the contact regions P+ can be produced in the first direction alternating with the source regions 25 . At locations where there is no source region 25, the region P+ domain can reach the semiconductor surface.

That is, in addition to the aforementioned, a part of the contact region P+ is located under the source region 25 and is in contact with the source region 25, and the contact region P+ may further include a second part, which is in contact with the source region 25. The n sub-source regions are arranged alternately.

The width of the sub-source region in the first direction must be kept small enough (for example, 0.5 μm-3 μm) to minimize the path of current under the sub-source region that may cause latch-up, thereby preventing latch-up from occurring.

Figure 2B shows that the source region 25 includes two sub-source regions, which are respectively arranged at the front and rear of the semiconductor surface, and the second part of the contact region P+ is arranged between the two sub-source regions; the second part of the contact region P+ The upper surfaces of the two parts are flush with the upper surface of the source region 25 , but of course they can also be set to be not flush.

Wherein, the gate 26 is formed in the gate trench, which includes: a first gate portion 261 having a uniform width; and a second gate portion 262 located below the first gate portion 261 and having a width greater than the The width of the uniform width described above.

A pair of gate trenches and the source region 25 define a mesa structure, and certain positions at the ends of the mesa structure have corner structures, chamfer structures or arc structures.

Fig. 3 is a perspective view showing an IGBT according to a modified example of the present invention;

Another possibility for the contact region P+ is to use a groove contact to connect the contact region to the emitter metal.

Such an embodiment is shown in FIG. 3 . Compared with the embodiment shown in FIG. 2A and FIG. 2B , the main difference of this embodiment is that a groove G1 is formed on the upper surface of the contact region P+, wherein the groove G1 is filled with the emitter A portion of the pole 39, so that the emitter is in contact with the source region 35 and the anti-latch-up region P+. The extending direction of the groove G1 may be the same as the extending direction of the trench of the gate 36 , that is, the direction perpendicular to the paper in the figure. A lower portion of the second emitter portion 392 passes through the n+ type source region 35 and extends to the bottom of the groove G1. Since the emitter 39 forms a groove contact with the contact region P+, it bypasses the pn junction between the base region 34 and the n+ source region 35, thereby partially short-circuiting the p-type collector region 31, n-type A PNPN structure formed by the field stop region 32, the n-type drift region 33, the p-type base region 34, and the n+-type source region 35, that is, the n-type drift region 33, the p-type base region 34, and the n+-type source region The parasitic npn transistor formed by 35 acts as a short circuit between the p-type base region 34 and the n+ type source region 35 . Therefore, during the over-current cut-off period of the IGBT 300 , the length of the p-type base region 34 under the n+-type source region 35 is limited to the distance between the trench and the groove contact, thereby reducing the ohmic voltage drop during the turn-off period. Therefore, the latch-up of the IGBT300 during the cut-off period is avoided, and the normal operation of the IGBT300 is guaranteed.

Preferably, the depth of the groove G1 is at least equal to the depth of the pn junction formed between the first part of the contact region P+ and the n+ type source region 35 . In this case, a contiguous n+ source region can be used. As shown in FIG. 3 , the source region 25 includes a first source region and a second source region, which are respectively located on two sides of the second emitter portion 392 . Each of the first source region and the second source region is continuous, which is different from being arranged at predetermined intervals as shown in FIG. 2A and FIG. 2B .

The groove G1 extends in the same direction as that of the at least one groove. Wherein, the bottom of the groove G1 may be 0.2 to 1.5 μm away from the upper surface of the semiconductor formed by the p-type base region 34 and the n+-type source region 35 .

Thereby, it can be ensured that the base region and the emitter of the parasitic npn transistor in IGBT 300 are effectively short-circuited.

4 is a cross-sectional view illustrating an IGBT according to a modified example of the present invention; and

In the embodiment shown in FIG. 4 , IGBT 400 is sectioned from the upper surface of source region 45 . The difference from the previous embodiments is that the gate 26 of the IGBT400 further includes: a third gate portion 44 with a uniform width, perpendicular to the first gate portion 461, a second gate portion 462, and Two first gate portions 461 and 462 opposite to each other are connected.

The third gate portion 463 , also referred to as a trench connection portion, is perpendicular to the extending direction of the at least one gate trench and connects the two gate trenches.

A predetermined portion of the anti-latch-up region P+ extends to the gate trench connection portion 463; or a predetermined portion of the anti-latch-up region P+ extends to the connection portion between the at least one trench and the gate trench 463 formed by the corner.

5A, 5B and 5C are cross-sectional views illustrating IGBTs according to several other modified examples of the present invention;

5A, 5B and 5C illustrate embodiments of region P+ contact trenches. The three embodiments shown are sectioned horizontally along the depth below the n+ source region (and below the contact groove).

According to some embodiments of the present invention, the contact region P+ extends to a predetermined position of the gate trench at the end of the mesa structure. Wherein, the distance between the edge of the contact region P+ and the gate trench must be relatively small, for example, 100nm-800nm. This also refers to certain parts of the contact region P+ that are not located at the ends of the mesa structures.

Multiple parts of the anti-latch-up region P+ extend to predetermined positions of the gate trench structure at predetermined intervals.

Specifically, as shown in FIG. 5A, the predetermined parts of the contact region P+ (the upper left corner 581 and the upper right corner 582 extend to the trenches of the first and second gate parts 461, 462 and the third The corner formed by the trench of the gate portion 463. The corner can be 90° to 135° or other angles, and can also be a rounded corner.

As shown in FIG. 5B , the predetermined portion of the contact region P+ extends to the entire end 583 of one side of the mesa structure, that is, the trench of the third gate portion;

At these locations, the p-doping under the source is so high that no MOS channel can form at gate voltages within the nominal range. Therefore, the above-mentioned problem of reduced or unstable MOS threshold voltage is solved.

As shown in FIG. 5C , the region P+ reaches more or less regularly spaced locations along most of the mesa of the trench, in particular, the contact region P+ has a plurality of locations 585, 586 extending at predetermined intervals close to the at the trench of the first gate.

The technical solution shown in FIG. 5C can lead to a reduction in the channel width and a considerable reduction in the current flowing in the short-circuit mode. Depending on the remaining active channel width, longer short durations can be achieved.

FIG. 6 is a cross-sectional view showing an IGBT according to another modified example of the present invention.

A further embodiment of the invention prevents latch-up by a different method. Here, by reducing the doping level to, for example, 1*1019 cm-3 or even preferably below 1*1018 cm-3, the emission efficiency of the n+ source region is reduced. Since the latch-up occurs only when the sum of the gains of the npn transistor (n source/p body/n drift region) and the pnp transistor (p emitter/n drift region/p body region) reaches 1, reduce the npn The gain of the junction transistor prevents latch-up. Since the contact resistance with only a moderately highly doped n-source will be high, without further measures, this embodiment should be combined with an additional contact area at the interface between the contact metal and the n-source. This additional contact region has a low contact resistance and may be a region implanted with, for example, selenium or sulfur ions. In particular, the implantation of selenium atoms results in lower doping concentrations for ohmic contacts, since at the end of the ion-implantation range, the selenium atoms separate and partially form electrically inactive clusters with energy levels deep in the bandgap. The usual implant dose is 3*1013 selenium atoms per cm3 and 3*1014 selenium atoms per cm3. The ion implantation energy should be in the range between 20 and 150 KeV or preferably between 30 and 70 KeV.

Alternatively, high-dose implantation of normally non-doped elements (such as argon or silicon) can achieve ohmic contact regions with strong damage and a high concentration of deep levels; preferably, the subsequent annealing temperature should be below 950°C or Better yet, below 350°C, or better yet, below 300°C.

Furthermore, a lateral variation of the n-type doping level in the source region can be provided; for example, a higher doping level in this region (where p-type concentration is high), and a lower doping level in this region (where, low concentration of p-type). In this way, a homogenous reduction in emitter efficiency can be achieved.

The IGBT 600 shown in FIG. 6 is formed by the above method, and the difference from the IGBT 200 shown in FIG. 2A is that an additional contact region 61 is formed under the second portion 692 of the emitter 69 .

As shown in FIG. 6, the emitter 69 is located above the source region 65; the dielectric layer 68 is located between the emitter 69 and the first base region 64; the emitter 69 includes: a first An emitter portion 691 is located on the dielectric layer 68 ; and a second emitter portion 692 passes through the dielectric layer 68 . Electrical contact to said source region 65 is made via an additional contact region 61 . The contact region 61 is arranged between the emitter and the source region 65 .

The contact region 61 contains selenium or sulfur atoms. The contact region 61 is a barrier layer. The blocking layer includes at least one of Ti, TiW, TiN, TaN.

Through the technical solution shown in FIG. 6 , the formation of latches can also be effectively prevented.

Although the IGBT device with a local narrow mesa structure has been described above as an example, the technology of the present invention is not limited thereto. For example, it can also be applied to an IGBT with a common trench gate structure. An IGBT device with a field stop structure is described as an example, but the technology of the present invention is not limited thereto, for example, it can also be applied to an IGBT device with a planar gate structure. In IGBT devices with other structures than the above-mentioned IGBT devices, the technology of the present invention can also be used to effectively avoid the latch-up effect.

The utility model has been specifically shown and described according to specific embodiments above, but those skilled in the art should understand that as long as it does not depart from the gist and scope of the utility model defined by the appended claims, its form and details can be modified. Various changes. Therefore, the scope of the present invention is as described in the appended claims, and therefore, various changes may be made as long as they are within the meaning and range of equivalency of the claims.

Claims (29)

1. an insulated gate bipolar transistor (200,300,400,600), is characterized in that, comprising:

Emitter (29,39); And

Semiconductor body, wherein said semiconductor body comprises:

The first base (24,34,44), has the first conduction type;

Source region (25,35,45), has the second conduction type that is different from described the first conduction type, and forms a pn knot with described the first base (24,34);

Anti-breech lock district (P+), be formed on described the first base (24,34,44), in, there is at least one and be positioned at described source region (25,35,45) under and with described source region (25,35,45) contact first, described anti-breech lock district (P+) has described the first conduction type, and doping content is greater than the doping content of described the first base (34); And

Grid, is formed in gate trench, and wherein, described gate trench is filled with gate electrode, and wherein, described gate trench has: the first groove (261), has the first width; And second groove (262), there is the second width; Described the second width is different from described the first width.

2. insulated gate bipolar transistor according to claim 1 (200,300,400,600), is characterized in that, described anti-breech lock district (P+) and described emitter (29,292,39,392) contact.

3. insulated gate bipolar transistor according to claim 1 (200,300,400,600), is characterized in that, described anti-breech lock district (P+) has and source region (25,35,45) laterally adjacent second.

4. insulated gate bipolar transistor according to claim 3 (200,300,400,600), is characterized in that, a part of horizontal direction of described the first base is positioned between the second portion and described gate trench in described anti-breech lock district (P+).

5. according to the insulated gate bipolar transistor (200 described in any one in claim 1 to 4,300,400,600), it is characterized in that, a part of horizontal direction of described the first base is positioned between the first and described gate trench in described anti-breech lock district (P+).

6. insulated gate bipolar transistor according to claim 5 (200,300,400), is characterized in that, the distance between described anti-breech lock district (P+) and described gate trench is 100nm-800nm.

7. according to the insulated gate bipolar transistor described in any one in claim 1 to 4 (300), it is characterized in that, the at least a portion in described anti-breech lock district (P+) contacts with the insulation division (27) of described gate trench, described insulation division (27) at least insulate described gate electrode (26) with described source region (25) and described the first base (24,34).

8. according to the insulated gate bipolar transistor described in any one in claim 1 to 4 (300), it is characterized in that, described source region (25,35,45) comprise the first source region and the second source region, wherein, the surperficial part in described emitter side of the second portion in described anti-breech lock district (P+) and described the first base (24,34) is between the surface and the surface in described the second source region in described first source region of described emitter side.

9. according to the insulated gate bipolar transistor described in any one in claim 1 to 4 (200), it is characterized in that, described source region (25,35,45) are 0.5 μ m-3 μ m along the width of described first direction.

10. according to the insulated gate bipolar transistor described in any one in claim 1 to 4 (300), it is characterized in that,

Described anti-breech lock district (P+) is formed with groove (G1, G2), and wherein, described groove (G1, G2) is filled with a part for described emitter (29,39), and described emitter and described source region (25,35,45) are contacted with described anti-breech lock district (P+).

11. insulated gate bipolar transistors according to claim 10 (300), is characterized in that,

The degree of depth of described groove (G1, G2) at least equals the first in described anti-breech lock district (P+) and the degree of depth of the knot of the pn between described source region (25,35,45).

12. insulated gate bipolar transistors according to claim 10 (200,300), is characterized in that, described groove (G1, G2) extends in the identical direction of the bearing of trend with described gate trench.

13. insulated gate bipolar transistors according to claim 10 (300), is characterized in that,

Dielectric layer (28) is positioned between described emitter (29,39) and described semiconductor body;

Described emitter (29,39) comprising:

The first emitter part (291,391), is positioned on described dielectric layer (28); And

The second emitter part (292,392), through described dielectric layer (28), extends in described groove (G1, G2) from described the first emitter part (291,391).

14. insulated gate bipolar transistors according to claim 13 (300), is characterized in that,

Described source region (25,35,45) comprises the first source region and the second source region, lays respectively at the both sides of described the second emitter part (292,392).

15. according to the insulated gate bipolar transistor (200 described in any one in claim 1-4,300), it is characterized in that, described the second groove (262) is arranged under described the first groove (261) along the vertical direction of described insulated gate bipolar transistor (300), wherein, horizontal direction in described insulated gate bipolar transistor (300), described the second width is greater than described the first width.

16. according to the insulated gate bipolar transistor described in any one in claim 1 to 4 (200,300), it is characterized in that, the first width of described the first groove (261) is the even width along described the first groove.

17. according to the insulated gate bipolar transistor described in any one in claim 1 to 4 (200,300), it is characterized in that,

Described gate trench comprises insulation division (27), and described gate electrode (26) is at least insulated with described source region (25) and described the first base (24,34).

18. according to the insulated gate bipolar transistor described in any one in claim 1 to 4 (200,300,400), it is characterized in that,

A pair of described gate trench and described source region (25,35,45) limit a mesa structure, and some position of the end of described mesa structure has corner structure, chamfering structure or arc structure.

19. according to the insulated gate bipolar transistor (200,300) described in any one in claim 1-4, it is characterized in that,

A plurality of positions in described anti-breech lock district (P+) extend to the precalculated position of the structure of described gate trench with predetermined space.

20. insulated gate bipolar transistors according to claim 18 (400), is characterized in that,

Described grid (46) also comprises: gate trench connecting portion (463), perpendicular to the bearing of trend of described gate trench, and connects two described gate trenchs.

21. insulated gate bipolar transistors according to claim 20 (400), is characterized in that,

The predetermined position (583,584) in described anti-breech lock district (P+) extends to described gate trench connecting portion (463); Or

The predetermined position in described anti-breech lock district (P+) (581,582,586) extends to described gate trench and the formed corner of described gate trench connecting portion (463).

22. according to the insulated gate bipolar transistor described in any one in aforementioned claim 1-4 (200,300,400), it is characterized in that,

Described insulated gate bipolar transistor (200,300) is trench gate field termination type insulated gate bipolar transistor.

23. according to the insulated gate bipolar transistor described in any one in claim 1-4 (200,300,400), it is characterized in that, also comprise:

Drift region (23,33,43), has the second conduction type that is different from described the first conduction type, and is positioned at a side contrary with emitter side of described the first base (24,34,44), and forms the 2nd pn knot with described the first base (24,34);

Collector region (21,31,41), has described the first conduction type, and is positioned at a side contrary with described the first base (24,34,44) side of described drift region (23,33,43); And

Collector electrode (C), contacts with described collector region (21,31,41).

24. insulated gate bipolar transistors according to claim 23 (200,300,400), is characterized in that:

Described gate trench extends in described drift region (23).

25. according to the insulated gate bipolar transistor described in any one in claim 1 to 4 (600), characterized by further comprising:

Dielectric layer (68), is positioned between described emitter (69) and described the first base (64);

Described emitter (69) comprising:

The first emitter part (691), is positioned on described dielectric layer (68); And

The second emitter part (692), through described dielectric layer (68), extends to described source region (65) from described the first emitter part (691), and forms contact zone (61) with described source region (65).

26. according to the insulated gate bipolar transistor described in any one in claim 1 to 4 (600), it is characterized in that:

Between described emitter and described source region (65), be provided with contact zone (61).

27. insulated gate bipolar transistors according to claim 25 (600), is characterized in that:

Described contact zone (61) comprises selenium or sulphur atom.

28. insulated gate bipolar transistors according to claim 25 (600), is characterized in that:

Described contact zone (61) is barrier layer.

29. insulated gate bipolar transistors according to claim 28 (600), is characterized in that:

Institute barrier layer comprises at least one in Ti, TiW, TiN, TaN.

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