CN203435089U - DSP and FPGA-based real-time detection apparatus for agronomic parameter of fruit tree - Google Patents
DSP and FPGA-based real-time detection apparatus for agronomic parameter of fruit tree Download PDFInfo
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Abstract
本实用新型公开了一种基于DSP与FPGA的果树农学参数实时检测装置,包括FPGA协处理器,DSP芯片,其特征在于:FPGA协处理器与DSP芯片连接,FPGA协处理器及DSP芯片均连接到电源电路上;在FPGA协处理器上连接有视频采集模块,复位电路,验证电路及储存模块;在DSP芯片上连接有JETG电路,复位电路,储存模块及显示模块,显示模块与验证电路连接。本实用新型DSP与FPGA相结合的结构,保证了检测结果的实时性与准确性,在不破坏农作物现有生长状况的情况下实时地得到作物的基本农学参数,达到了智能化高精度的在线实时检测的目的,为实时变量喷雾提供了重要的依据,且适合我国的小地块小规模作业,具有较大实践应用价值。
The utility model discloses a real-time detection device for fruit tree agronomic parameters based on DSP and FPGA, which comprises an FPGA coprocessor and a DSP chip, and is characterized in that the FPGA coprocessor is connected with the DSP chip, and both the FPGA coprocessor and the DSP chip are connected. to the power supply circuit; the FPGA coprocessor is connected with a video acquisition module, reset circuit, verification circuit and storage module; the DSP chip is connected with a JETG circuit, reset circuit, storage module and display module, and the display module is connected with the verification circuit . The structure of the combination of DSP and FPGA in the utility model ensures the real-time and accuracy of the detection results, obtains the basic agronomic parameters of the crops in real time without destroying the existing growth conditions of the crops, and achieves intelligent high-precision online The purpose of real-time detection provides an important basis for real-time variable spraying, and it is suitable for small-scale operations in small plots in my country, and has great practical application value.
Description
技术领域 technical field
本实用新型涉及电子控制技术领域,尤其是一种基于DSP与FPGA的果树农学参数实时检测装置。 The utility model relates to the technical field of electronic control, in particular to a real-time detection device for fruit tree agronomic parameters based on DSP and FPGA. the
背景技术Background technique
图像处理技术检测农学参数的一般方法:利用扫描仪、数码相机等图像采集系统对作物图像进行采集,然后用数字图像处理的算法得出所求农学参数的在数字图像中的表示,或者提取出和农学参数相关的几何和色彩特征,于所测农学参数的真实值进行回归得到预测模型。 The general method of image processing technology to detect agronomic parameters: use image acquisition systems such as scanners and digital cameras to collect crop images, and then use digital image processing algorithms to obtain the representation of agronomic parameters in digital images, or extract and The geometric and color features related to the agronomic parameters are regressed on the real values of the measured agronomic parameters to obtain a prediction model.
发明内容 Contents of the invention
本实用新型的目的是:提供一种基于DSP与FPGA的果树农学参数实时检测装置,它实现了高频图像信号的精确采集,又可以保证运算处理的实时性与准确性,达到了智能化高精度的在线实时检测的目的。 The purpose of this utility model is to provide a real-time detection device for fruit tree agronomic parameters based on DSP and FPGA, which realizes the accurate collection of high-frequency image signals, and can ensure the real-time and accuracy of calculation and processing, and achieves high intelligence. The purpose of online real-time detection of precision. the
本实用新型是这样实现的:基于DSP与FPGA的果树农学参数实时检测装置,包括FPGA协处理器,DSP芯片,其特征在于:FPGA协处理器与DSP芯片连接,FPGA协处理器及DSP芯片均连接到电源电路上;在FPGA协处理器上连接有视频采集模块,复位电路,验证电路及储存模块;在DSP芯片上连接有JETG电路,复位电路,储存模块及显示模块,显示模块与验证电路连接。 The utility model is achieved in that the real-time detection device of fruit tree agronomic parameters based on DSP and FPGA comprises an FPGA coprocessor and a DSP chip, and is characterized in that: the FPGA coprocessor is connected with the DSP chip, and both the FPGA coprocessor and the DSP chip are connected. Connected to the power circuit; connected to the FPGA coprocessor is a video acquisition module, reset circuit, verification circuit and storage module; connected to the DSP chip is a JETG circuit, reset circuit, storage module and display module, display module and verification circuit connect. the
所述的视频采集模块包括CCD摄像头,CCD摄像头通过A/D转换芯片与视频处理芯片连接,在A/D转换芯片上连接有初始化模块,视频处理芯片与FPGA协处理器连接。 The video acquisition module includes a CCD camera, the CCD camera is connected with the video processing chip through the A/D conversion chip, the A/D conversion chip is connected with an initialization module, and the video processing chip is connected with the FPGA coprocessor. the
所述的复位电路带有时钟电路。时钟电路为整个系统提供统一的工作时序。 The reset circuit has a clock circuit. The clock circuit provides a unified working sequence for the whole system. the
所述的储存模块包括SDRAM储存模块及FLASH模块。 The storage module includes SDRAM storage module and FLASH module. the
电源电路是为系统提供所需要的3.3V、1.8V的内核电压,以1.2V参考电压而设计的。 The power supply circuit is designed to provide the required 3.3V and 1.8V core voltages for the system, and is designed with a 1.2V reference voltage. the
复位电路使系统初始上电的时候处于一个稳定可靠的初始状态。 The reset circuit keeps the system in a stable and reliable initial state when it is initially powered on. the
FPGA协处理器是图像采集的核心部分,主要完成系统采集来的视频数据的格式转换和帧存以及图像的输出控制功能。 The FPGA coprocessor is the core part of image acquisition, and mainly completes the format conversion, frame storage and image output control functions of the video data collected by the system. the
存储模块包括SDRAM模块及FLASH模块,SDRAM作为视频数据的缓存,FLASH存储DSP算法得到的检测结果。 The storage module includes SDRAM module and FLASH module, SDRAM is used as the cache of video data, and FLASH stores the detection result obtained by DSP algorithm. the
验证电路用了ADV7123将数字图像数据转换为模拟数据并用其驱动VGA显示器显示图像,以演示图像采集的效果。 The verification circuit uses ADV7123 to convert the digital image data into analog data and uses it to drive the VGA monitor to display the image, so as to demonstrate the effect of image acquisition. the
初始化模块主要功能是通过I2C总线对A/D转换芯片的寄存器进行配置,从而把CCD摄像头采集的PAL制式的视频数据解码为YUV4:2:2数据。 The main function of the initialization module is to configure the registers of the A/D conversion chip through the I 2 C bus, so as to decode the PAL video data collected by the CCD camera into YUV4:2:2 data.
视频处理模块的功能是对A/D转换芯片送来的YUV数据进行处理;利用SDRAM控制器的帧存储功能和异步FIFO存储器的协助下将相邻的三帧图像数据存储到SDRAM的固定地址。 The function of the video processing module is to process the YUV data sent by the A/D conversion chip; use the frame storage function of the SDRAM controller and the assistance of the asynchronous FIFO memory to store the adjacent three frames of image data to the fixed address of the SDRAM. the
显示模块用于产生驱动VGA的时序,把ADV7123输出的模拟图像打入VGA显示器进行显示。 The display module is used to generate timing for driving VGA, and put the analog image output by ADV7123 into the VGA display for display. the
由于采用了上述技术方案,与现有技术相比,本实用新型DSP与FPGA相结合的结构,利用FPGA协处理器具有强大的现场可编程能力,具有做时序的调整和图像处理的硬件算法的优势;DSP控制器是哈弗结构体系的嵌入式处理器,具有相互独立的数据总线和地址总线,独立的硬件乘法器,因此非常适合做数字信号处理;把两者结合起来,能够快速地完成图像信号的采集。而且DSP控制器可以快速的执行图像处理算法,保证了检测结果的实时性与准确性,在不破坏农作物现有生长状况的情况下实时地得到作物的基本农学参数,达到了智能化高精度的在线实时检测的目的,为实时变量喷雾提供了重要的依据,且适合我国的小地块小规模作业,具有较大实践应用价值。 Owing to having adopted above-mentioned technical scheme, compared with prior art, the structure that the utility model DSP combines with FPGA utilizes FPGA coprocessor to have powerful on-the-spot programmable ability, has the hardware algorithm that does timing adjustment and image processing Advantages; the DSP controller is an embedded processor of the Haval structure system, with independent data bus and address bus, and independent hardware multiplier, so it is very suitable for digital signal processing; combining the two can quickly complete the image signal collection. Moreover, the DSP controller can quickly execute the image processing algorithm to ensure the real-time and accuracy of the detection results, and obtain the basic agronomic parameters of the crops in real time without destroying the existing growth conditions of the crops, achieving intelligent and high-precision The purpose of online real-time detection provides an important basis for real-time variable spraying, and is suitable for small-scale operations in small plots in my country, and has great practical application value. the
附图说明 Description of drawings
附图1为本实用新型的结构示意图;
Accompanying
附图2为本实用新型的视频采集模块的结构示意图;
Accompanying
附图3为本实用新型的工作原理图。
Accompanying
具体实施方式 Detailed ways
本实用新型的实施例:基于DSP与FPGA的果树农学参数实时检测装置,包括FPGA协处理器1,DSP芯片2,其特征在于:FPGA协处理器1与DSP芯片2连接,FPGA协处理器1及DSP芯片2均连接到电源电路5上;在FPGA协处理器3上连接有视频采集模块3,复位电路4,验证电路6及储存模块7;在DSP芯片4上连接有JETG电路8,复位电路4,储存模块7及显示模块9,显示模块9与验证电路6连接;所述的视频采集模块3包括CCD摄像头3-1,CCD摄像头3-1通过A/D转换芯片3-2与视频处理芯片3-3连接,在A/D转换芯片3-2上连接有初始化模块3-4,视频处理芯片3-3与FPGA协处理器1连接;所述的复位电路4带有时钟电路。所述的储存模块7包括SDRAM储存模块及FLASH模块。
Embodiment of the present utility model: the fruit tree agronomy parameter real-time detection device based on DSP and FPGA, comprises
初始化模块3-4通过I2C总线对解码芯片的寄存器进行配置并初始化,CCD摄像头3-1采集到的原始图像数据格式为PAL制式,经过A/D转换芯片3-2采用saa7113芯片进行A/D转换处理后,生成每秒30帧的图像数据,该数据是分辨率为720×240 的YCbCr(4:2:2)格式的8位图像数据。A/D转换芯片3-2输出到FPGA协处理器1的信号有像素时钟,行、场参考信号,图像数据。FPGA协处理器1在输入的行、场参考都有效时,在输入象素时钟的同步下,接收图像数据进入接收缓存到线缓存模块;由SDRAM时钟控制将一帧数据读入SDRAM中; SDRAM占用容量过半时,从SDRAM 中读取一帧数据至输出缓存;输出缓存为异步FIFO,完成跨时钟传送数据的工作;DSP芯片2通过XINTF接口读取SDRAM存储器的固定地址。由DSP芯片2读取一帧数据,并在DSP芯片2中做生物量密度等农学参数的计算,送LCD显示,存入寄存器待用。验证工作由YUV转RGB模块和VGA控制模块完成。VGA接口在显示器上显示。图像处理过程中采取用三帧同步的处理方法,提高图像的处理速度来满足实时性的要求。
The initialization module 3-4 configures and initializes the registers of the decoding chip through the I 2 C bus. The original image data format collected by the CCD camera 3-1 is the PAL system, and the A/D conversion chip 3-2 adopts the saa7113 chip for A After the /D conversion process, image data at 30 frames per second is generated, which is 8-bit image data in YCbCr (4:2:2) format with a resolution of 720×240. The signals output from the A/D conversion chip 3-2 to the
选用美光公司的SDRAM存储器MT48LC16M16A2P-6A芯片,用来缓存SAA7113芯片输出的图像数据。 Micron's SDRAM memory MT48LC16M16A2P-6A chip is selected to cache the image data output by the SAA7113 chip. the
FLASH芯片选用SST39VF800;系统采集的数据通过ADV7123解码后由VGA接口输出结果。 The FLASH chip selects SST39VF800; the data collected by the system is decoded by ADV7123 and output by the VGA interface.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9411613B1 (en) | 2015-04-22 | 2016-08-09 | Ryft Systems, Inc. | Systems and methods for managing execution of specialized processors |
| US9411528B1 (en) | 2015-04-22 | 2016-08-09 | Ryft Systems, Inc. | Storage management systems and methods |
| US9542244B2 (en) | 2015-04-22 | 2017-01-10 | Ryft Systems, Inc. | Systems and methods for performing primitive tasks using specialized processors |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US9411613B1 (en) | 2015-04-22 | 2016-08-09 | Ryft Systems, Inc. | Systems and methods for managing execution of specialized processors |
| US9411528B1 (en) | 2015-04-22 | 2016-08-09 | Ryft Systems, Inc. | Storage management systems and methods |
| US9542244B2 (en) | 2015-04-22 | 2017-01-10 | Ryft Systems, Inc. | Systems and methods for performing primitive tasks using specialized processors |
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