CN203367268U - Semiconductor chip packaging module and packaging structure thereof - Google Patents
Semiconductor chip packaging module and packaging structure thereof Download PDFInfo
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- CN203367268U CN203367268U CN201320485888.3U CN201320485888U CN203367268U CN 203367268 U CN203367268 U CN 203367268U CN 201320485888 U CN201320485888 U CN 201320485888U CN 203367268 U CN203367268 U CN 203367268U
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- electrical connector
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Abstract
本实用新型揭示了一种半导体芯片封装模组及封装结构，其中，所述封装结构包括：半导体芯片，所述芯片一表面设有第一电连接件和与所述第一电连接件相应的功能区；基板，其包括上表面及与上表面相背的下表面；金属凸块，电性连接所述第一电连接件和所述基板下表面的导电层；第二电连接件，电性连接所述基板下表面的导电层，其厚度大于所述半导体芯片和所述金属凸块的厚度之和。与现有技术相比，本实用新型可在不对基板做任何改动的情况下，有效减小封装体积，满足市场对电子产品的尺寸的轻、小、薄化需求。
The utility model discloses a semiconductor chip packaging module and a packaging structure, wherein the packaging structure includes: a semiconductor chip, a surface of the chip is provided with a first electrical connector and a corresponding first electrical connector Functional area; substrate, which includes an upper surface and a lower surface opposite to the upper surface; metal bumps, electrically connecting the first electrical connector and the conductive layer on the lower surface of the substrate; the second electrical connector, electrically The conductive layer permanently connected to the lower surface of the substrate has a thickness greater than the sum of the thicknesses of the semiconductor chip and the metal bump. Compared with the prior art, the utility model can effectively reduce the packaging volume without making any changes to the substrate, and meet the market demand for light, small and thin electronic products.
Description
Technical field
The utility model belongs to field of semiconductor manufacture, relates in particular to a kind of semiconductor die package module and encapsulating structure thereof.
Background technology
Along with developing rapidly of electronic industry, market more and more is tending towards light, little, thinning to the dimensional requirement of electronic product; Correspondingly, the semiconductor die package in electronic product is had higher requirement.
In currently available technology, normally adopt Bonding (Wire Bonding) mode to be encapsulated (as shown in Figure 1) to semiconductor chip, existing wafer level packaging structure comprises: chip 10, substrate 20, wherein, chip 10 is bonded in the upper surface of substrate 20, and be electrically connected by gold thread 30 and substrate 20, substrate 20 lower surfaces are provided with tin ball 40.
Summary of the invention
The purpose of this utility model is to provide a kind of semiconductor die package module and encapsulating structure thereof that reduces encapsulation volume.
Wherein, the semiconductor chip package of the utility model one execution mode comprises: semiconductor chip, described chip one surface be provided with the first electrical connector and with described the first corresponding functional areas of electrical connector;
Substrate, it comprises that upper surface reaches the lower surface opposing with upper surface;
Described encapsulating structure also comprises:
Metal coupling, be electrically connected the conductive layer of described the first electrical connector and described base lower surface;
The second electrical connector, be electrically connected the conductive layer of described base lower surface, and its thickness is greater than the thickness sum of described semiconductor chip and described metal coupling.
As further improvement of the utility model, described substrate is provided with through hole, and the position of described through hole is corresponding with described functional areas.
As further improvement of the utility model, the difference of the thickness sum of the thickness of described the second electrical connector and described semiconductor chip and described metal coupling is more than or equal to 100 microns.
As further improvement of the utility model, the material of described metal coupling is gold.
Correspondingly, the semiconductor packages module of the utility model one execution mode, comprise semiconductor chip-packaging structure, the lens and the support that coordinate with described semiconductor chip package, and described semiconductor chip package comprises:
Semiconductor chip, described chip one surface be provided with the first electrical connector and with described the first corresponding functional areas of electrical connector;
Substrate, it comprises that upper surface reaches the lower surface opposing with upper surface, and described substrate is provided with through hole, and the position of described through hole is corresponding with described functional areas; Described encapsulating structure also comprises:
Metal coupling, be electrically connected the conductive layer of described the first electrical connector and described base lower surface;
The second electrical connector, be electrically connected the conductive layer of described base lower surface, and its thickness is greater than the thickness sum of described semiconductor chip and described metal coupling.
As further improvement of the utility model, the focal length of described lens equal lens centre to the thickness of the distance of upper surface of base plate, substrate, base lower surface to the center, functional areas apart from sum.
As further improvement of the utility model, the difference of the thickness sum of the thickness of described the second electrical connector and described semiconductor chip and described metal coupling is more than or equal to 100 microns.
Compared with prior art, the utility model can, by comparatively simple technique, effectively reduce encapsulation volume, light, little, the thinning demand of satisfying the market to the size of electronic product.
The accompanying drawing explanation
Fig. 1 is the encapsulating structure generalized section of semiconductor chip in background technology.
Fig. 2 is semiconductor chip package generalized section in the utility model one execution mode.
Fig. 3 is semiconductor packages modular structure generalized section in the utility model one execution mode.
Fig. 4 is semiconductor module method for packing flow chart of steps in the utility model one execution mode.
Embodiment
Below with reference to embodiment shown in the drawings, the utility model is described in detail.But these execution modes do not limit the utility model, the conversion on the structure that those of ordinary skill in the art makes according to these execution modes, method or function all is included in protection range of the present utility model.
As shown in Figure 2, in the utility model one execution mode, described semiconductor chip package comprises semiconductor chip 10, substrate 20, metal coupling 30, and the second electrical connector 40.
Wherein, described chip 10 1 surfaces are provided with at least one first electrical connector 101, for example: weld pad; And with described the first corresponding functional areas 102 of electrical connector 101, for example: the image sensing district.Described the first electrical connector 101 and described functional areas 102 are electrically connected.Preferably, in the present embodiment, the surface that is provided with the first electrical connector 101 and functional areas 102 is referred to as the upper surface of chip 10, and opposing surface is referred to as the lower surface of chip 10 with it.
Described substrate 20, its material can be the materials such as silicon, glass, pottery.Described substrate 20 has upper surface and reaches the lower surface opposing with upper surface.Preferably, the lower surface of described substrate 20 is provided with conductive layer 201.
Described at least one second electrical connector 40, for example: soldered ball is arranged at lower surface one side of described substrate 20.Described the second electrical connector 40 is electrically connected described conductive layer 201.
Described metal coupling 30, its material can be the conducting metals such as gold.The first electrical connector 101 on the described semiconductor chip 10 of this metal coupling 30 electric connection and the conductive layer 201 of described substrate 20 lower surfaces, make the electric connection with described the second electrical connector 40 by described metal coupling 30 realizations of described the first electrical connector 101.
Preferably, in present embodiment, described the second electrical connector 40 roughly is spherical shape.The thickness of described the second electrical connector 40 is greater than the thickness sum of described semiconductor chip 10 and described metal coupling 30.Wherein, the thickness of described the second electrical connector 40 refers to the distance from the lower surface of substrate 20 to the horizontal plane at the second electrical connector 40 lower extreme point places.Described semiconductor chip 10 thickness refer to the distance from the upper surface of semiconductor chip 10 to the lower surface of semiconductor chip 10.The thickness of described metal coupling 30 refer to electric connection point from described metal coupling 30 and substrate 20 to described metal coupling 30 distance with the electric connection point of the upper surface of semiconductor chip 10.Described lower extreme point refers to that lower surface from described substrate 20 is apart from maximum point.So, the lower surface of this semiconductor chip 10 is less than the distance of the lower extreme point of described the second electrical connector 40 to the upper surface of substrate 20 to the distance of the upper surface of substrate 20, thereby has reduced the integral thickness of whole semiconductor chip package.
Preferably, the difference of the thickness sum of the thickness of described the second electrical connector 40 and described semiconductor chip 10 and described metal coupling 30 is more than or equal to 100 microns.To facilitate the second electrical connector 40 to be electrically connected with other devices again, as pcb board.
It is worth mentioning that, shown in ginseng Fig. 3, when described semiconductor chip 10 is the image sensing chip, also can be provided with through hole 202 on described substrate 20, the position of this through hole 202 is corresponding with the position of the functional areas of described semiconductor chip 10, with the upper surface from described substrate 20, exposes the image sensing district described semiconductor chip 10.During the opaque materials such as especially described substrate 20 employing silicon or pottery.
As shown in Figure 3, in the utility model one execution mode, described semiconductor packages module comprises semiconductor chip-packaging structure, the lens 50 that coordinate with described semiconductor chip package and support 60, the focal length of described lens equal lens centre to the thickness of the distance of upper surface of base plate, substrate, base lower surface to the center, functional areas apart from sum.Wherein said semiconductor chip package is the image sensing chip-packaging structure, and encapsulating structure is as previously mentioned particularly for it.
As shown in Figure 4, in the utility model one execution mode, the method for packing of semiconductor module is comprised of following steps:
S1, provide a substrate 20, its material can be the materials such as silicon, glass, pottery.Described substrate 20 has upper surface and reaches the lower surface opposing with upper surface, forms some through holes 202 on described substrate, and forms conductive layer 201 at described base lower surface.
The semiconductor chip is provided, and in the present embodiment, this semiconductor chip can be the wafer form of arbitrary dimension.Described chip 10 1 surfaces are provided with some the first electrical connectors 101, for example: weld pad; And with described the first corresponding some functional areas 102 of electrical connector 101, for example: the image sensing district.Described the first electrical connector 101 and described functional areas 102 are electrically connected.Preferably, in the present embodiment, the surface that is provided with the first electrical connector 101 and functional areas 102 is referred to as the upper surface of chip 10, and opposing surface is referred to as the lower surface of chip 10 with it.
S2, provide metal coupling 30, its material to can be gold to wait conducting metal.The chip 10 that surface is provided with to some the first electrical connectors 101 is electrically connected by metal coupling 30 and the conductive layer 201 of described substrate 20 lower surfaces, described some functional areas are corresponding with described some lead to the hole site, with the upper surface from described substrate 20, expose the image sensing district described semiconductor chip 10.During the opaque materials such as especially described substrate 20 employing silicon or pottery.
S3, at the upper surface of described substrate, form some supports, and with some lens of some support assorteds;
S4, some the second electrical connectors 40 that are electrically connected at described substrate 20 lower surfaces formation and conductive layer 201, for example: soldered ball.Described the first electrical connector 101 is the electric connection with described the second electrical connector 40 by described metal coupling 30 realizations.
Preferably, in present embodiment, described the second electrical connector 40 roughly is spherical shape.The thickness of described the second electrical connector 40 is greater than the thickness sum of described semiconductor chip 10 and described metal coupling 30.Wherein, the thickness of described the second electrical connector 40 refers to the distance from the lower surface of substrate 20 to the horizontal plane at the second electrical connector 40 lower extreme point places.Described semiconductor chip 10 thickness refer to the distance from the upper surface of semiconductor chip 10 to the lower surface of semiconductor chip 10.The thickness of described metal coupling 30 refer to electric connection point from described metal coupling 30 and substrate 20 to described metal coupling 30 distance with the electric connection point of the upper surface of semiconductor chip 10.Described lower extreme point refers to that lower surface from described substrate 20 is apart from maximum point.So, in the situation that substrate 20 is not done to any change, the lower surface that makes this semiconductor chip 10 is less than the distance of the lower extreme point of described the second electrical connector 40 to the upper surface of substrate 20 to the distance of the upper surface of substrate 20.By comparatively simple technique, effectively reduced encapsulation volume.Especially, in present embodiment, because described semiconductor chip 10 is arranged at the lower surface of described substrate, the focal length of described lens equal lens centre to the thickness of the distance of upper surface of base plate, substrate, base lower surface to the center, functional areas apart from sum, therefore its can be directly at the upper surface formation support of described substrate 20, and without after the formation of the upper surface at substrate distance piece, form again support on distance piece, effectively reduce packaging cost, simplified packaging technology, promoted packaging efficiency.
Preferably, the difference of the thickness sum of the thickness of described the second electrical connector 40 and described semiconductor chip 10 and described metal coupling 30 is more than or equal to 100 microns.To facilitate the second electrical connector 40 to be electrically connected with other devices again, as pcb board.
Be to be understood that, although this specification is described according to execution mode, but not each execution mode only comprises an independently technical scheme, this narrating mode of specification is only for clarity sake, those skilled in the art should make specification as a whole, technical scheme in each execution mode also can be through appropriate combination, other execution modes that formation it will be appreciated by those skilled in the art that, for example, can first form the second electrical connector, then form the foreseeable adjustment that the those skilled in the art such as support and lens do under spirit of the present utility model.
Above listed a series of detailed description is only illustrating for feasibility execution mode of the present utility model; they are not in order to limit protection range of the present utility model, all disengaging within equivalent execution mode that the utility model skill spirit does or change all should be included in protection range of the present utility model.
Claims (7)
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| Application Number | Priority Date | Filing Date | Title |
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| CN201320485888.3U CN203367268U (en) | 2013-08-09 | 2013-08-09 | Semiconductor chip packaging module and packaging structure thereof |
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| CN201320485888.3U CN203367268U (en) | 2013-08-09 | 2013-08-09 | Semiconductor chip packaging module and packaging structure thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103400817A (en) * | 2013-08-09 | 2013-11-20 | 苏州晶方半导体科技股份有限公司 | Semi-conductor chip packaging module, packaging structure and packaging method of semi-conductor chip packaging module |
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- 2013-08-09 CN CN201320485888.3U patent/CN203367268U/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103400817A (en) * | 2013-08-09 | 2013-11-20 | 苏州晶方半导体科技股份有限公司 | Semi-conductor chip packaging module, packaging structure and packaging method of semi-conductor chip packaging module |
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| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20131225 |