CN203337971U - Array substrate and display device - Google Patents

Abstract

The utility model provides an array substrate and a display device, and belongs to the technical field of liquid crystal display. The array substrate and the display device can solve the problems that an existing oxide film transistor array substrate is complex in manufacturing technology and manufacturing cost is high. The array substrate comprises a plurality of pixel units, each pixel unit comprises a film transistor area and a display area, film transistors are arranged in the film transistor areas, the film transistors comprise grids, grid insulating layers and active areas, the film transistor areas and the display areas further comprise transparent conductive layers, in the film transistor areas, the transparent conductive layers form the sources of the film transistors and the drains of the film transistors, and in the display areas, the transparent conductive layers form pixel electrodes. The display device comprises the array substrate.

Description

Array substrate and display device

technical field

The utility model belongs to the field of display technology, in particular to an array substrate and a display device.

Background technique

In recent years, display technology has developed rapidly, such as the development of thin film transistor technology from the original a-Si (amorphous silicon) thin film transistor to the current LTPS (low temperature polysilicon) thin film transistor, MILC (metal induced lateral crystallization) thin film transistor, Oxide (oxide) thin film transistors, etc. The light-emitting technology has also developed from the original LCD (liquid crystal display) and PDP (plasma display) to the current OLED (organic light-emitting diode) and so on.

At present, oxide thin-film transistors are attracting more and more attention due to their many advantages. Thin film transistors using oxide semiconductors as active layers have high mobility, good uniformity, transparency, and better switching characteristics, and can be applied to applications that require fast response and large current, such as high frequency, high resolution, and large size displays and organic light-emitting displays.

However, the manufacturing process of the oxide thin film transistor array substrate in the prior art is relatively complicated, and generally requires six photolithography processes. Figure 1 shows a typical structure diagram of the existing oxide thin film transistor array substrate. The oxide thin film transistor The array substrate includes a substrate 1 , a gate 2 , a gate insulating layer 3 , an oxide active layer 4 , an etch stop region 5 , a drain 602 , a source 601 , a passivation layer 7 and a pixel electrode 8 . The oxide thin film transistor array substrate with this structure needs to be formed through six photolithography processes, including the gate 2, the oxide active layer 4, the etch barrier region 5, the source 601 and the drain 602, and the passivation layer 7 via holes. and the pattern of the pixel electrode 8 . It can be seen that the fabrication process of the oxide thin film transistor array substrate with this structure is complicated and the fabrication cost is relatively high.

Utility model content

The technical problems to be solved by the utility model include, aiming at the problems of complex manufacturing process and high manufacturing cost of the existing oxide thin film transistor array substrate, to provide an array substrate with simple manufacturing process and low manufacturing cost.

The technical solution adopted to solve the technical problem of the utility model is an array substrate, including a plurality of pixel units, each pixel unit includes a thin film transistor area and a display area, the thin film transistor area is provided with a thin film transistor, and the thin film transistor includes : gate, gate insulating layer, active region, the thin film transistor region and display region also include a transparent conductive layer, the transparent conductive layer constitutes the source and drain of the thin film transistor in the thin film transistor region, and forms a thin film transistor in the display region pixel electrodes.

Preferably, the array substrate further includes: a source transition layer on the source electrode and a source connection layer on the source transition layer.

Further preferably, the patterns of the source electrode, the source transition layer and the source connection layer are the same.

Further preferably, the material of the source transition layer is heavily doped amorphous silicon; the source connection layer is one or more of molybdenum, molybdenum-niobium alloy, aluminum, aluminum neodymium alloy, titanium, copper Formed single-layer or multi-layer composite laminates.

Preferably, the array substrate further includes a passivation layer, and the passivation layer covers the thin film transistor region.

Preferably, the material of the active region is metal oxide semiconductor.

Preferably, the array substrate further includes an etching stopper region disposed on the active region.

The array substrate of the present invention includes a thin film transistor area and a display area, and the thin film transistor area and the display area also include a transparent conductive layer, because the source electrode, the drain electrode and the pixel electrode of the array substrate of the present invention are all made of the same transparent layer. The conductive layer is produced, so its manufacturing process is simple and the manufacturing cost is low.

The technical problem to be solved by the utility model also includes providing a display device with a simple manufacturing process and low manufacturing cost in view of the problems of complex manufacturing process and high manufacturing cost of the existing display device including an oxide thin film transistor array substrate.

The technical solution adopted to solve the technical problems of the utility model is a display device, which includes:

Any one of the above-mentioned array substrates.

The array substrate of the display device of the present invention includes a thin film transistor area and a display area, and the thin film transistor area and the display area also include a transparent conductive layer, because the source electrode, the drain electrode and the pixel electrode of the array substrate of the present invention are all made of the same layer transparent conductive layer, so its manufacturing process is simple and the manufacturing cost is low.

Description of drawings

FIG. 1 is a schematic structural view of an existing oxide thin film transistor array substrate;

2 is a schematic structural view of the array substrate of Embodiment 1 of the present invention;

3 is a schematic diagram of the structure of the array substrate according to Embodiment 2 of the present invention to form a pattern including a transparent conductive layer film, a transition layer film and a metal layer film;

4 is a schematic structural view of the array substrate in Embodiment 2 of the present invention after forming a source connection layer;

5 is a schematic structural view of the array substrate in Embodiment 2 of the present invention after forming a source transition layer;

6 is a cross-sectional view along the direction A-A in FIG. 7 after the source and drain electrodes are formed on the array substrate of Embodiment 2 of the present invention;

7 is a top view of the array substrate according to Embodiment 2 of the present invention after the source and drain are formed;

8 is a schematic structural view of the array substrate of Embodiment 2 of the present invention after forming a passivation layer;

9 is a schematic structural view of the array substrate in Example 2 of the present invention after removing the passivation layer in the display area;

FIG. 10 is a schematic structural view of the array substrate in Example 2 of the present invention after removing the transition layer film in the display area;

Wherein reference numerals are: 1. substrate; 2. gate; 3. gate insulating layer; 4. active layer; 401. active region; 5. etching stopper region; 601. source; 602. drain 7. Passivation layer; 8. Pixel electrode; 9. Source transition layer; 10. Source connection layer; Q1, thin film transistor region; Q2, display region.

Detailed ways

In order to enable those skilled in the art to better understand the technical solution of the utility model, the utility model will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

Example 1:

As shown in Figure 2, this embodiment provides an array substrate, the array substrate includes a thin film transistor area Q1 and a display area Q2, the thin film transistor area Q1 is provided with a thin film transistor, and the thin film transistor includes: a gate 2, a gate insulating layer 3 and active layer 4 , wherein the part of the active layer 4 corresponding to the gate 2 is the active region 401 . Wherein, the gate 2 is located on the substrate 1 , the gate insulating layer 3 covers the gate 2 , and the active layer 4 is located on the gate insulating layer 3 .

Preferably, the material of the active region 401 (of course, the material of the active layer 4 ) is metal oxide semiconductor. For example, its material may be indium gallium zinc oxide, indium zinc oxide or indium gallium tin oxide, preferably indium gallium zinc oxide or indium zinc oxide; the thickness of the active layer 4 is preferably between 10 nm and 100 nm. It should be noted that, as shown in FIG. 2, from the perspective of simplifying the manufacturing process, the active layer 4 is also present in the display area Q2, that is, the active layer 4 can extend to the display area Q2. Obviously, the The active layer 4 should be transparent, and metal oxide materials and semiconductors are all transparent materials, so they are preferred.

The thin film transistor region Q1 and the display region Q2 also include a transparent conductive layer (such as an indium tin oxide layer), and the transparent conductive layer forms the source 601 and the drain 602 of the thin film transistor in the thin film transistor region Q1, and forms the source electrode 601 and the drain electrode 602 of the thin film transistor in the display region Q2. pixel electrode 8 . That is to say, the source electrode 601, the drain electrode 602 and the pixel electrode 8 are all produced by the same transparent conductive layer.

In the prior art, the source 601 and the drain 602 of the thin film transistor are produced by a layer of source-drain metal, and the pixel electrode 8 is produced by a layer of transparent conductive layer. Usually, the pixel electrode 8 is formed by a passivation layer on the source-drain metal. 7 The via hole is electrically connected to the drain 602, and in the array substrate of the present invention, the source 601, the drain 602 and the pixel electrode 8 are produced by the same layer of transparent conductive layer, as shown in Figure 2, the drain 602 and The pixel electrodes 8 are directly connected, so the manufacturing process is simple and the manufacturing cost is low.

Preferably, the array substrate further includes a source connection layer 10 .

It should be noted that the source connection layer 10 is used for electrical connection with the data line (not shown in the figure). In the prior art, the source electrode 601 is directly connected with the data line. The array provided in this embodiment The substrate is preferably electrically connected to the data line through the source connection layer 10, because the source electrode 601 in this embodiment is made of a transparent conductive layer, and the data line is usually made of a metal material, so the connection between the two Poor electrical conductivity will cause large distortion of the data signal during transmission to the pixel electrode 8 . Therefore, the array substrate provided in this embodiment preferably further includes a source connection layer 10 . The material of the source connection layer 10 is preferably a single-layer or multi-layer composite laminate formed of one or more materials of molybdenum, molybdenum-niobium alloy, aluminum, aluminum-neodymium alloy, titanium, and copper.

Preferably, the array substrate provided in this embodiment further includes a source transition layer 9 .

It should be noted that the function of the source transition layer 9 is to electrically connect the source connection layer 10 to the source electrode 601, because the material of the source connection layer 10 is metal or alloy, and the source electrode 601 is made of a transparent conductive layer. The connection layer 10 is connected to the source electrode 601, and the source transition layer 9 is not provided, there will still be poor contact between the source connection layer 10 and the source electrode 601, resulting in that when the source connection layer 10 is connected to the data line, the data signal cannot be accurately transmitted to the pixel electrode 8, thereby affecting the accuracy and stability of the voltage of the pixel electrode 8, and further affecting the display effect of the liquid crystal display device. Therefore, on the array substrate provided in this embodiment, a source transition layer 9 is also provided between the source electrode 601 and the source connection layer 10 . The material of the source transition layer 9 is heavily doped amorphous silicon (N+a-Si), which can ensure its good electrical conductivity, which also ensures that the data signal can be accurately transmitted to the pixel electrode 8 .

Further preferably, the pattern of the source transition layer 9 is the same as that of the source connection layer 10 .

As shown in Figure 2, the patterns of the source connection layer 10, the source transition layer 9 and the source electrode 601 are the same, which is mainly for the simplicity of the manufacturing process (that is, these structures can be produced in one patterning process). 1. The patterns of the source transition layer 9 and the source electrode 601 can be different, and are specifically set according to specific needs.

It should be further explained that, in FIG. 2 , there are also two layers above the drain 602 , namely: the transition layer film formed on the same layer as the source transition layer 9 and the metal layer film formed on the same layer as the source connection layer 10 . The existence of these two layers has no influence on the performance of the thin film transistor, so they can be retained from the perspective of simplifying the process, and of course they can be removed in a certain way.

The array substrate provided in this embodiment further preferably includes: a passivation layer 7 covering the region between the thin film transistor region Q1 and the pixel unit. The function of this passivation layer is to protect structures such as thin film transistors. As shown in FIG. The electrode 8 needs to form an electric field with the common electrode, and the passivation layer 7 cannot be arranged on it.

Preferably, the array substrate further includes an etch barrier region 5 disposed on the active region 401. It is not difficult to understand that the function of the etch barrier region 5 is to ensure that when the transparent conductive layer film is etched , the active region 401 is not etched.

It should be noted that the thin-film transistors of the array substrate provided in this embodiment are described by taking the bottom-gate type as an example. In fact, the technical solutions mentioned in the present invention are also applicable to the thin-film transistors including the top-gate structure. As for the array substrate, as long as the source electrode 601, the drain electrode 602 and the pixel electrode 8 are produced by the same transparent conductive layer film.

It should be noted that the array substrate provided in this embodiment is an example in which the common electrode is not included (that is, the common electrode is provided on the color filter substrate), but if the common electrode is also provided on the array substrate (that is, the IPS mode Or an array substrate in ADS mode) is also feasible, as long as the source electrode 601, the drain electrode 602 and the pixel electrode 8 are produced by the same layer of transparent conductive layer film. In addition, the data line is not shown in the figure, but the data line only needs to be connected to the source connection layer 10 (through holes can be used, or direct connection can be used, etc.).

The array substrate of the present utility model includes a thin film transistor region Q1 and a display region Q2, and the thin film transistor region Q1 and display region Q2 also include a transparent conductive layer, because the source electrode 601, the drain electrode 602 and the pixel electrode of the array substrate of the present utility model 8 are all produced by the same layer of transparent conductive layer film, so the manufacturing process is simple and the manufacturing cost is low.

Example 2:

This embodiment provides a method for fabricating an array substrate, the array substrate comprising: a gate 2, a gate insulating layer 3, a source 601, a drain 602, a pixel electrode 8 and an active region 401, as shown in Figures 3 to 10 As shown, it specifically includes the following steps:

S01, forming a pattern including the gate 2 on the substrate 1 through a patterning process. The patterning process generally includes processes such as photoresist coating, exposure, development, etching, and photoresist stripping. Wherein, the material of the gate 2 is formed by one or more materials selected from molybdenum (Mo), molybdenum-niobium alloy (MoNb), aluminum (Al), aluminum-neodymium alloy (AlNd), titanium (Ti), and copper (Cu). single-layer or multi-layer composite laminates. It is preferably a single-layer or multi-layer composite film composed of molybdenum (Mo), aluminum (Al) or an alloy containing molybdenum (Mo) and aluminum (Al); the preferred thickness is 100nm-3000nm.

S02, forming a pattern including a gate insulating layer 3 on the substrate 1 after the above steps are completed. The gate insulating layer 3 is made of silicon oxide (SiOx), silicon nitride (SiNx), hafnium oxide (HfOx), silicon oxynitride (SiON), aluminum oxide (AlOx), etc. A multi-layer composite film composed of one or two components. The gate insulating layer 3 is preferably formed by plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD).

The above two steps can be specifically set according to different needs. For example, steps such as forming gate lines (for example, synchronously forming with the gate 2 ) can also be included, which is not limited in the present invention.

S03 , forming a pattern including the active region 401 and the etch stop region 5 on the substrate 1 after the above steps are completed through a patterning process.

Preferably, the S03 step specifically includes the following:

S031, sequentially forming an active layer film and an etching barrier film, and at the same time, forming a photoresist layer above the etching barrier film, the formation of the film usually includes various methods such as deposition, coating, sputtering, etc., wherein, The part of the active layer film corresponding to the gate 2 forms an active region 401, and the part of the etching barrier film corresponding to the active region 401 forms an etching barrier region 5;

Wherein, the active layer film is a metal oxide semiconductor film, such as indium gallium zinc oxide, indium zinc oxide, indium gallium tin oxide, and the like.

The etch stop film can be made of silicon oxide (SiOx), silicon nitride (SiNx), hafnium oxide (HfOx), (aluminum oxide) AlOx, or a multilayer stack of two or three of these film composition. The etch stop film has a low hydrogen content.

S032, exposing and developing the photoresist layer, while retaining the photoresist layer corresponding to the etching barrier area;

S033, removing the etch barrier film that is not covered by the photoresist to form a pattern including the etch barrier region 5;

It should be noted that in this step, the active layer 4 of the display area Q2 is reserved to simplify the process, but in fact the active layer 4 of the display area Q2 has no practical function and can be removed.

Remove the remaining photoresist layer.

S04, forming a transparent conductive layer film, and using the transparent conductive layer film to form a pattern including a source electrode 601 and a drain electrode 602 through a patterning process.

As shown in Figures 3 to 7, the preferred specific steps of S04 include the following:

S041, sequentially forming a pattern comprising a transparent conductive layer film, a transition layer film and a metal layer film;

Among them, the transparent conductive layer film is preferably made of ITO (indium tin oxide) material, and the amorphous ITO (indium tin oxide) film is prepared by sputtering film formation, and then crystallized by annealing. The thickness of the transparent conductive layer film is preferably 20 to 150 nm.

，优选为

。The transition layer film is preferably made of heavily doped amorphous silicon (N+a-Si). The specific process can use plasma enhanced chemical vapor deposition technology to form the transition layer film. The deposition temperature is below 350°C. The thickness of the film layer is

, preferably

.

The metal layer thin film is preferably a single layer or a single layer formed by one or more of molybdenum (Mo), molybdenum-niobium alloy (MoNb), aluminum (Al), aluminum-neodymium alloy (AlNd), Ti, Cr, Cu Multi-layer composite laminate. It is preferably a single-layer or multi-layer composite film composed of Mo, Al or an alloy containing Mo and Al; its thickness is preferably 100 nm to 3000 nm.

S042. Remove the metal layer film, transition layer film, and transparent conductive layer film corresponding to the active area through a patterning process, as well as the metal layer film, transition layer film, transparent conductive layer film, and active layer in the area between each pixel unit thin film, forming a pattern including the source connection layer 10, the source transition layer 9, the source electrode 601 and the drain electrode 602.

It should be noted that, as shown in FIGS. 4 to 6, the process of removing the metal layer film, the transition layer film, the transparent conductive layer film and the active layer film in the area between the active region 401 and each pixel unit is performed synchronously. However, because there is an etching stopper region 5 above the active region 401, when the active layer 4 is removed synchronously, only the active layer thin film in the area between the pixel units is really removed, and the active layer thin film in the active region is not is etched.

The metal layer film, transition layer film and transparent conductive layer film corresponding to the active region are removed, and the metal layer film, transition layer film, transparent conductive layer film and active layer film in the area between each pixel unit are preferably Methods include:

S0421. As shown in FIG. 4, perform wet etching on the metal layer film, thereby forming a pattern including the source connection layer 10, but at this time, only the metal layer film in the area between the active region and each pixel unit is removed, and the metal layer film is removed. The metal layer film in the display area Q2 is preserved;

S0422. As shown in FIG. 5, perform dry etching on the transition layer film, remove the transition layer film in the area between the active region and each pixel unit, similarly, keep the transition layer film in other areas (because it is covered Under the etched metal layer film, it will not be etched);

S0423. As shown in FIG. 6, perform wet etching on the transparent conductive layer thin film in the active region and the transparent conductive layer thin film and the active layer thin film in the region between each pixel unit, that is, in the thin film transistor region Q1, the The transparent conductive layer film is disconnected at the active area, and simultaneously forms a disconnected source electrode 601 and drain electrode 602 (the drain electrode 602 is connected to the pixel electrode 8); the transparent conductive layer film and the active region between each pixel unit Layers of film are removed at the same time, that is, there are no redundant layers between adjacent pixel units.

Specifically, as shown in FIG. 7 , the array substrate includes a plurality of pixel units, and each pixel unit includes a thin film transistor area Q1 and a display area Q2 . It should be noted that, in order to clearly show the structure, only the source electrode 601, the drain electrode 602, the gate electrode 2, the pixel electrode 8 and the etch stop layer 5 are drawn in FIG. For layers such as the transition layer 9 and the source connection layer 10 , those skilled in the art should understand and know the structures and positions of other layers. It can be seen that after step S04, the transparent conductive layer film is disconnected at the active region, exposing the etching stopper region 5, and the source electrode 601 is formed (in fact, there are source transition layer 9 and source connection layer 10 above the source electrode 601 , not shown) and the drain 602 (marked in the figure to show that the drain 602 is directly connected to the pixel electrode 8, but in fact the drain 602 is covered with the remaining transition layer film and metal layer film) . At the same time, as shown in FIG. 7 , the metal layer film, the transition layer film, the transparent conductive layer film and the active layer film in the regions between the pixels are also removed, so that there is no redundant layer between adjacent pixels.

S05. Form a pattern including the pixel electrode 8 by using a transparent conductive layer film through a patterning process.

As shown in Figures 8 to 10, the S05 step preferably specifically includes the following:

S051, as shown in FIG. 8, form a passivation layer 7, and coat a photoresist layer on the passivation layer 7;

Among them, the passivation layer 7 is preferably made of silicon oxide (SiOx), silicon nitride (SiNx), hafnium oxide (HfOx), silicon oxynitride (SiON), aluminum oxide (AlOx ) or a multilayer laminated film composed of two or more of them, the passivation layer 7 can be made by plasma enhanced chemical vapor deposition technology, which is characterized by a low hydrogen content in the film layer and a good surface properties.

S052, exposing and developing the photoresist layer, wherein there is no remaining photoresist layer in the display area Q2;

S053. As shown in FIG. 9 , remove the passivation layer 7 in the display area Q2 that is not blocked by the photoresist layer by dry etching;

As shown in FIG. 10 , remove the metal layer thin film in the display area Q2 that is not covered by the photoresist layer by wet etching;

Remove the transition layer film in the display area Q2 without photoresist shielding by dry etching, expose the transparent conductive layer film to form a pattern including the pixel electrode 8, that is, form the array substrate shown in FIG. 2; that is, in this step ( S05) In the process of forming the pattern including the pixel electrode 8, the transparent conductive layer film is not actually etched, but the passivation layer 7, the metal layer film, and the transition layer film in the display area Q2 are removed, so that the display The thin film of the transparent conductive layer in the region Q2 is exposed to form a pattern including the pixel electrode 8;

S054 , removing the remaining photoresist layer.

It should be noted that since the transition layer film can be removed by dry etching, the transparent conductive layer film located in the display area Q2 will not be adversely affected during the step of removing the transition layer film. This is because for the transparent conductive layer film, if the layer on it needs to be removed by wet etching, part of the transparent conductive layer film will also be removed, and the dry etching method cannot remove the transparent conductive layer film.

It needs to be further explained that it is also feasible if there is no transition layer film and metal layer film in the display area Q2, that is, the transition layer film and metal layer film on the transparent electrode layer have been removed before the step S05 (step S04) , or neither the thin film transistor region Q1 nor the display region Q2 of the array substrate in this embodiment includes transition layer films and metal layer films (in this case, the electrical connection performance between the data line and the source electrode 601 is not good, but it is also feasible) , that is, the passivation layer 7 is above the transparent conductive layer of the display area Q2, and the passivation layer 7 can be directly removed by dry etching, or the pixel electrode 8 can also be formed.

Although the method for fabricating the array substrate provided in this embodiment adds the source transition layer 9 and the source connection layer 10, because these two layers are produced in one patterning process with the source electrode 601 and the drain electrode 602, no further addition is required. At the same time, since the source electrode 601, the drain electrode 602 and the pixel electrode 8 on the array substrate of this embodiment are formed by the same layer of transparent conductive layer film, there is no need to pass through the passivation layer 7 to make the pixel electrode 8 and the The drain 602 is connected, and in the prior art, the gate 2, the oxide active layer 4, the etch barrier region 5, the source 601 and the drain 602, the passivation layer 7 via holes and the The fabrication method of the oxide thin film transistor array substrate for the pixel electrode 8 is simplified to only 4 steps of photolithography, so the fabrication process is simple and the fabrication cost is low.

Example 3:

This embodiment provides a display device, which includes the array substrate described in Embodiment 1. The display device may be any product or component with a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.

The display device of this embodiment has the array substrate in Embodiment 1, so its manufacturing process is simple and its manufacturing cost is low.

Certainly, the display device of this embodiment may also include other conventional structures, such as a power supply unit, a display driving unit, and the like.

It can be understood that, the above embodiments are only exemplary embodiments adopted to illustrate the principles of the present invention, but the present invention is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present utility model, and these variations and improvements are also regarded as the protection scope of the present utility model.

Claims (8)

1. an array base palte, comprise a plurality of pixel cells, and each pixel cell comprises thin film transistor region and viewing area, and described thin film transistor region is provided with thin film transistor (TFT), and described thin film transistor (TFT) comprises: grid, gate insulator, active area, it is characterized in that,

Described thin film transistor region and viewing area also comprise transparency conducting layer, and described transparency conducting layer forms source electrode and the drain electrode of thin film transistor (TFT) at thin film transistor region, form pixel electrode in viewing area.

2. array base palte according to claim 1, is characterized in that, also comprises: be positioned at the source transition bed on described source electrode and be positioned at the source articulamentum on the transition bed of described source.

3. array base palte according to claim 2, is characterized in that, described source electrode, source transition bed, source articulamentum pattern are identical.

4. array base palte according to claim 2, is characterized in that, the material of described source transition bed is heavily doped amorphous silicon; Described source articulamentum is the single or multiple lift composite laminate that one or more materials in molybdenum, molybdenum niobium alloy, aluminium, aluminium neodymium alloy, titanium, copper form.

5. array base palte according to claim 1, is characterized in that, also comprises passivation layer, and described passivation layer covers described thin film transistor region.

6. array base palte according to claim 1, is characterized in that, the material of described active area is metal-oxide semiconductor (MOS).

7. array base palte according to claim 1, is characterized in that, also comprises the etch stop region of being located on described active area.

8. a display device, is characterized in that, comprises the array base palte of any one in claim 1～7.

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