CN203276789U - System for removing spread spectrum of LVDS (Low Voltage differential Signaling) - Google Patents

Abstract

Disclosed is a system for removing spread spectrum of LVDS signals, including an input LVDS signal acquisition module, a first phase-locked loop, a clock detection module, a FIFO buffer, a control processor, a second phase-locked loop and output LVDS signal synthesis module, wherein the control processor receives the effective data information about the synchronization signal sent by the clock detection module and the detection results about the frequency and jitter range of the clock signal, so as to control the FIFO buffer to transmit data and calculate the required reduction The recovered clock signal, and send the control signal with the calculation result to the second phase-locked loop, so that it can adjust the corresponding frequency of the local clock signal without spread spectrum characteristics to form a stable recovered clock signal; finally through The output LVDS signal synthesizing module synthesizes the data signal, the synchronous signal and the recovered clock signal sent by the second phase-locked loop into an LVDS signal without spectrum spreading for output. The utility model can remove the spreading frequency of the LVDS signal, so that the common DVI signal acquisition card can be used for the acquisition and test of the LVDS signal.

Description

System for removing spread spectrum of LVDS signals

technical field

The utility model relates to the field of electronic equipment, in particular to a system for removing the frequency spread of LVDS signals. the

Background technique

In the field of electronic equipment, those skilled in the art know that when an electronic system works at a single frequency, because the energy at this frequency is very high, it will generate a strong electromagnetic wave at this frequency. Pulse interference (Electromagnetic Interference, referred to as EMI). This electromagnetic interference can affect other electronic equipment or the human body. At present, electronic products, especially consumer electronic equipment, have very strict EMI quantification regulations to reduce EMI. At present, the basic method for reducing EMI is to reduce the energy of a specific frequency by spreading the spectrum of the clock or signal. For example, for an LVDS signal transmission system, the LVDS signal is transmitted after being spread by a clock or signal. the

But for the LVDS signal receiving system, since the clock and the frequency of the entire digital signal are broadened, the circuit must go through a large additional overhead to meet the system requirements, such as a larger storage system and stricter timing requirements. Moreover, for some systems, the signal jitter is required to be small while reducing EMI, which requires that the front-end spread spectrum signal be removed from the spread spectrum in a specific system or at least be compatible with the signal and clock after the spread spectrum. the

In existing solutions, tolerance to bandwidth changes after spectrum spreading is achieved mainly by increasing storage capacity. This method only solves the integrity of data reception, and cannot solve the problem of high requirements on clock and signal jitter in some systems, that is to say, the existing method cannot fundamentally remove the spread spectrum of LVDS signals. characteristic. Moreover, since the prior art cannot effectively remove the spread spectrum of the LVDS signal, the signal acquisition cards on the market cannot correctly collect the LVDS signal with spread spectrum. the

Utility model content

Aspects of the utility model provide a system for removing the frequency spread of LVDS signals, which can remove the frequency spread of LVDS signals, so that ordinary DVI signal acquisition cards can be used for the acquisition and testing of LVDS signals. the

One aspect of the present utility model provides a kind of system for removing the frequency spread of LVDS signal, comprising:

Input LVDS signal acquisition module, be used for collecting the LVDS signal of band spread spectrum of input, and the LVDS signal that gathers is separated into clock signal, synchronous signal and data signal; Wherein, described clock signal is pixel clock signal, and described data The signal is an RGB data signal, and the synchronization signal at least includes an effective display data strobe signal;

The first phase-locked loop is used to receive and FM-lock the clock signal separated by the LVDS signal acquisition module;

The clock detection module is used to receive the synchronous signal separated by the LVDS signal acquisition module to extract valid data information, and is used to detect the frequency and jitter range of the clock signal locked by the first phase-locked loop;

The control processor is configured to receive valid data information about the synchronization signal sent by the clock detection module and detection results about the frequency and jitter range of the clock signal, and control the FIFO buffer based on the valid data information and the jitter range of the clock signal Transmit data, and calculate the recovered clock signal to be restored based on the frequency and jitter range of the clock signal and according to the principle of frame synchronization, and send the control signal with the calculation result to the second phase-locked loop;

The FIFO buffer is connected to the LVDS signal acquisition module and the control processor respectively, and is used to transmit the data signal separated by the LVDS signal acquisition module under the control of the control processor;

The second phase-locked loop is used to receive and lock the local clock signal without spread spectrum characteristics generated by the crystal oscillator, and perform frequency adjustment according to the control signal sent by the control processor to form a stable recovered clock signal;

The output LVDS signal synthesis module is used to synthesize the data signal, the synchronization signal and the recovered clock signal sent by the second phase-locked loop into an LVDS signal without spread spectrum for output. the

The system for removing the frequency spread of LVDS signals disclosed by the utility model can effectively remove the frequency spread of LVDS signals, so that ordinary DVI acquisition cards can also acquire images, so that ordinary DVI signal acquisition cards can be used for LVDS signals collection and testing. the

Description of drawings

FIG. 1 is a schematic structural diagram of a system for removing spread spectrum of LVDS signals in an embodiment of the present invention. the

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. example. Based on the embodiments of the present utility model, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the scope of protection of the present utility model. the

The embodiment of the utility model also provides a system for removing the frequency spread of LVDS signals, which can effectively remove the frequency spread of LVDS signals, so that ordinary DVI acquisition cards can also collect images, so that ordinary DVI signal acquisition cards can It is used for the collection and testing of LVDS signals. the

Referring to Fig. 1, it is a kind of system that is used to remove the frequency spread of LVDS signal that the utility model embodiment provides; Described system that is used to remove the frequency spread of LVDS signal includes input LVDS signal acquisition module 11, the first phase-locked loop 12. Clock detection module 13, control processor 14, FIFO buffer 15, second phase-locked loop 16 and output LVDS signal synthesis module 17, wherein:

The input LVDS signal acquisition module 11 is used to acquire the input LVDS signal with spread spectrum, and separate the acquired LVDS signal into a clock signal DCLK1, a synchronization signal and a data signal. Wherein, the synchronous signal includes a horizontal synchronous signal HSync, a vertical synchronous signal Vsync, and an effective display data strobe signal DE in the LVDS signal. The clock signal DCLK1 is a pixel clock signal, which is a reference for transmitting and reading data signals. Wherein, since the input LVDS signal is an LVDS signal with spread spectrum, the frequency of the clock signal DCLK1 changes periodically, that is, it is unstable. The data signal is an RGB data signal. Because the effective display data strobe signal DE contains line and field timing information, it has the function of a composite line and field synchronous signal; while the line synchronous signal HS and the field synchronous signal VS belong to separate synchronous signals. Therefore, the use of synchronization signals can be divided into two types: (1) do not use HS, VS signals, only use DE signals (called only DE synchronization signal mode); (2) use HS, VS, DE signals as synchronization signals at the same time ( Called HS/VS/DE sync signal mode). In this embodiment, under the control of the synchronization type selection signal, only the DE synchronization signal mode or the HS/VS/DE synchronization signal mode can be selected to be used, that is, the synchronization signal input to the LVDS signal acquisition module 11 can only include valid display data The strobe signal DE or simultaneously includes three signals of HS, VS, and DE signals. the

The first phase-locked loop 12 is used to receive and FM lock the clock signal DCLK1 separated by the LVDS signal acquisition module 11; the first phase-locked loop 12 processes the received clock signal DCLK1, and extracts a certain clock signal therefrom. The phase information of the clock, so that the frequency of the output signal is strictly synchronized with the frequency of the input signal, and the output signal and the input signal have a certain phase difference. the

The clock detection module 13 is configured to receive the synchronous signal separated by the LVDS signal acquisition module 11 to extract valid data information, and to detect the frequency and jitter range of the locked clock signal DCLK1. Among them, the clock detection module 13 extracts the valid data part from the received synchronous signal (that is, the effective display data strobe signal DE, and can also extract the horizontal synchronous signal HS and the field synchronous signal VS according to the synchronous signal mode adopted) for use in to reconstruct the signal. The purpose of detecting the frequency and jitter range of the locked clock signal DCLK1 is to regenerate a stable clock signal, so that the regenerated stable clock signal can match the data signal in the input LVDS signal, that is, to find and calculate Appropriate recovered clock signal DCLK2 means appropriate buffer size. Since the PLL (here specifically refers to the second phase-locked loop 16 ) cannot generate any clock frequency, a relatively close frequency needs to be calculated. At the same time, the jitter range of the clock signal DCLK1 is detected to solve the problem of asynchronous input and output by using the FIFO buffer and periodically inserting blank content. the

The control processor 14 is used to receive the effective data information about the synchronization signal sent by the clock detection module 13 and the detection result about the frequency and the jitter range of the clock signal DCLK1, and based on the effective data information and the clock signal DCLK1 jitter range Control the detection result FIFO buffer to transmit data; and based on the frequency and jitter range of the clock signal DCLK1, calculate the required restored clock signal according to the principle of frame synchronization, and send the control signal with the calculation result to the second PLL16. the

The FIFO buffer 15 is connected to the LVDS signal acquisition module 11 and the control processor 14 respectively, and is used to transmit the data signal separated by the LVDS signal acquisition module 11 under the control of the control processor 14 . Among them, the FIFO buffer 15 is a first-in-first-out buffer, which buffers input valid data and eliminates the phenomenon of asynchronous input and output data caused by changes in input data speed. Specifically, the FIFO buffer 15 controls the FIFO input according to the effective data information sent by the control processor 14 (such as the effective display data strobe signal DE) to collect effective data signals; The output data of the strobe signal DE must maintain a certain amount of buffered data during the whole process, so that the problem of asynchrony caused by the inconsistency of the input and output clocks can be solved. the

The second phase-locked loop 16 is used to receive and lock the local clock signal without spread spectrum characteristics generated by the crystal oscillator 161, and form a stable recovered clock signal DCLK2 according to the control signal sent by the control processor 14, specifically , the local clock signal without the spread spectrum feature is generated by the crystal oscillator 161, and the generated local clock signal without the spread spectrum feature is sent to the second phase-locked loop 16; the second phase-locked loop 16 receives the without spread spectrum After the characteristic local clock signal, under the guidance of the control signal of the clock signal that needs to be restored based on the frequency of the clock signal DCLK1 sent by the control processor 14, the corresponding local clock signal without spread spectrum characteristics is performed. Frequency adjustment processing, so as to obtain the required stable recovery clock signal DCLK2. the

Output LVDS signal synthesizing module 17, be used for the data signal that FIFO buffer 15 transmits, the synchronous signal that control processor 14 sends and the recovery clock signal DCLK2 that the second phase-locked loop 16 sends synthesize and remove the LVDS signal of spread spectrum and output, When compositing, keep the input field frequency equal to the input field frequency by inserting blank pixels. The above is a preferred embodiment of the present utility model, it should be pointed out that for those of ordinary skill in the art, without departing from the principle of the present utility model, some improvements and modifications can also be made, these improvements and modifications It is also regarded as the protection scope of the present utility model. the

Claims (1)

1. A system for removing spread spectrum of LVDS signals, comprising: Input the LVDS signal acquisition module (11), used to acquire the input LVDS signal with spread spectrum, and separate the acquired LVDS signal into a clock signal, a synchronization signal and a data signal; wherein, the clock signal is a pixel clock signal, The data signal is an RGB data signal, and the synchronization signal at least includes an effective display data strobe signal; The first phase-locked loop (12) is used to receive and FM lock the clock signal separated by the LVDS signal acquisition module (11); A clock detection module (13), configured to receive the synchronization signal separated by the LVDS signal acquisition module (11) to extract valid data information, and to detect the frequency of the clock signal locked by the first phase-locked loop (12) and jitter range; A control processor (14), configured to receive valid data information about the synchronization signal sent by the clock detection module (13) and detection results about the frequency and jitter range of the clock signal, and based on the valid data information and the clock signal The jitter range controls the FIFO buffer to transmit data, and calculates the recovered clock signal that needs to be restored based on the frequency and jitter range of the clock signal and the principle of frame synchronization, and sends the control signal with the calculation result to the second phase lock ring(16); The FIFO buffer (15) is respectively connected to the LVDS signal acquisition module (11) and the control processor (14), and is used to transmit the LVDS signal acquisition module ( 11) Separated data signal; The second phase-locked loop (16) is used to receive and lock the local clock signal without spread spectrum characteristics generated by the crystal oscillator, and adjust the frequency according to the control signal sent by the control processor (15) to form a stable recovery clock signal; The output LVDS signal synthesis module (17) is used for synthesizing the data signal, the synchronization signal and the recovered clock signal sent by the second phase-locked loop (16) into an LVDS signal without spread spectrum for output. the

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