CN203149556U - Programmable blade server structure - Google Patents
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- CN203149556U CN203149556U CN 201320068852 CN201320068852U CN203149556U CN 203149556 U CN203149556 U CN 203149556U CN 201320068852 CN201320068852 CN 201320068852 CN 201320068852 U CN201320068852 U CN 201320068852U CN 203149556 U CN203149556 U CN 203149556U
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- 230000003287 optical effect Effects 0.000 claims description 4
- 230000002093 peripheral effect Effects 0.000 abstract description 4
- 238000004891 communication Methods 0.000 description 11
- 230000006870 function Effects 0.000 description 10
- 238000010586 diagram Methods 0.000 description 7
- 238000013507 mapping Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 101100004179 Schizophyllum commune BAR2 gene Proteins 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000000977 initiatory effect Effects 0.000 description 2
- 230000008520 organization Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000008859 change Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000013307 optical fiber Substances 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000011664 signaling Effects 0.000 description 1
- WDQKVWDSAIJUTF-GPENDAJRSA-N via protocol Chemical compound ClCCNP1(=O)OCCCN1CCCl.O([C@H]1C[C@@](O)(CC=2C(O)=C3C(=O)C=4C=CC=C(C=4C(=O)C3=C(O)C=21)OC)C(=O)CO)[C@H]1C[C@H](N)[C@H](O)[C@H](C)O1.C([C@H](C[C@]1(C(=O)OC)C=2C(=C3C([C@]45[C@H]([C@@]([C@H](OC(C)=O)[C@]6(CC)C=CCN([C@H]56)CC4)(O)C(=O)OC)N3C=O)=CC=2)OC)C[C@@](C2)(O)CC)N2CCC2=C1NC1=CC=CC=C21 WDQKVWDSAIJUTF-GPENDAJRSA-N 0.000 description 1
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Abstract
The utility model provides a programmable blade server structure. The programmable blade server structure comprises a back plate and a plurality of processor blades inserted into peripheral PCIE inserting slots of the back plate, and is characterized in that each receiving-transmitting channel of each PCIE inserting slot is connected with a high-speed receiver of a field programmable gata array (FPGA), wherein a main endpoint channel is connected to a cvp configuration function specified channel, intellectual property (IP) cores of the plurality of PCIE endpoints in the FPGA are respectively connected with corresponding device endpoints according to corresponding PCIE inserting slots, the device endpoints are connected with a programmable logic module, and the programmable logic module is connected with a PCIEIO interface. The programmable blade server structure has unparalleled expansibility and flexibility compared with existing blade service structures.
Description
Technical field
The utility model belongs to the blade server field, specifically is a kind of blade server structure able to programme.
Background technology
Present blade server substantially all be based on the fixed logic chip design, manufacture and design finish after, its hardware logic function remains unchanged, its backboard only has exchanges data or signalling channel function.The exchange of agreement in the present existing blade server can not arbitrarily change in addition, and extendability and dirigibility are limited.And the network interface of conventional blades server, SAN optical-fibre communications, Infiniband communication and FC interface, all need corresponding interface card be arranged at server blade, the switch of outside need respective protocol, system complex, the cost height, reliability is not high.
The utility model content
In order to solve the problems of the technologies described above, the utility model provides a kind of blade server structure able to programme.
A kind of blade server structure able to programme, comprise that backboard and several are inserted in the processor blade on the backboard PCIE slot, it is characterized in that the transceiver channel of each PCIE slot connects the high-speed transceiver of FPGA, wherein main end points passage is connected to the passage of the cvp configuration feature appointment of FPGA, be connected with the corresponding equipment end points respectively by corresponding PCIE slot by several PCIE end points IP kernels in the FPGA, the equipment end points is connected with programmed logical module, and programmed logical module is connected with PCIE IO interface.
Described a kind of blade server structure able to programme is characterized in that primary processor blade in the described processor blade is provided with the front panel network interface for remote update.
Described a kind of blade server structure able to programme is characterized in that described PCIE IO interface is connected with Ethernet SFP optical interface by the high speed transceiver channel, and described equipment end points connects the ethernet mac in the FPGA, and ethernet mac connects PCS, and PCS connects PMA.
Described a kind of blade server structure able to programme is characterized in that described equipment end points connects the ethernet mac in the FPGA, and ethernet mac is connected with the Ethernet protocol exchange logic, and the Ethernet protocol exchange logic is realized the agreement exchange by fpga logic.
Described a kind of blade server structure able to programme is characterized in that described equipment end points connects the SATA MAC in the FPGA, and SATA MAC connects PCS, and PCS connects PMA, and described PCIE IO interface is connected with the SATA interface by the high speed transceiver channel.
Described a kind of blade server structure able to programme is characterized in that between the described processor blade that the read and write access of the BAR register by the equipment end points realizes FIFO high speed interconnected communication.
Described a kind of blade server structure able to programme, it is characterized in that each processor blade distributes a DMA address, wherein control module is read and write in the location mapping controllably of the endpoint device of primary processor blade, by interrupting the control module initiation to the interruption of other processors.
Blade server structure able to programme of the present invention, in backboard, use the Altera Stratix V of company (or Arria V or Cyclone V) FPGA as the backboard acp chip, used three grades of dirigibility innovations to handle, first dirigibility is handled: specifically made up 1, FPGA dynamic recognition cvp function, 2, FPGA PCIE collocation channel is designed to the main channel structure, 3, the programmability of FPGA PCIE endpoint device, 4, the main blade of band network connection and configuration FPGA function, connect and support various different peripherals, the following peripheral hardware that needs dynamically updates in the structure of the present invention in the time of can be by primary processor blade network implementation, the hardware logic of this structural support telecommunication network software definition is upgraded, this structure is adapted in the customizable server of hardware use.It is to link FPGA behind backboard PCIE slot that second dirigibility of structure handled, the PCIE apparatus logic is realized in FPGA, utilize the programmability of FPGA apparatus logic, as long as being provided, the FPGA protocol process module behind the programming in logic just can realize using any digital exchange agreement that needs, do not limit a certain certain protocol, it is that output interface is partly connected the IO blade by identical PCIE slot that the 3rd dirigibility of structure handled, make output interface adapt to various different demands, so this structure have the incomparable PCIe device extension of current blade server architecture and processing protocol dirigibility.This structure can also utilize the logic intercommunication of FPGA device that high-speed data function of exchange, high-performance between the server blade computing function of trooping is provided simultaneously.Extension connecting equipment is realized in FPGA in this structure, and the agreement exchange between the server inner blade realizes in FPGA equally, has saved interface card and switch and has dropped into, and has reduced system cost and complicacy.The logic connection has replaced the physics of External cable to patch and has connected minimizing in the chip, has improved system reliability.The connected mode of this structure is in the identical FPGA PCIE peripheral hardware of different server blade, makes that the pipeline data communication between the server blade no longer needs complicated agreement, can effectively improve the efficient of data communication.This structure allows the equipment of different Pcie domain spaces be in the same fpga logic chip, and the high-speed communication between the blade main frame can be provided.Realize the opaque bridge logic function of Pcie-Pcie in the structural support FPGA, internal memory is visited mutually between the support blade server.
Description of drawings
Fig. 1 is the physical arrangement figure of blade server able to programme of the present utility model;
Fig. 2 is the fpga logic structural drawing of blade server able to programme of the present utility model;
Fig. 3 is the primary processor blade structure of blade server able to programme of the present utility model;
Fig. 4 is the interior expansion of the FPGA gigabit/10,000,000,000 SFP optical interface Ethernet logical organization synoptic diagram of blade server able to programme of the present utility model;
Fig. 5 is the gigabit/10,000,000,000 SFP optical interface IO blade synoptic diagram of blade server able to programme of the present utility model;
Fig. 6 is the Ethernet protocol exchange synoptic diagram of blade server able to programme of the present utility model;
Fig. 7 is the interior expansion of the FPGA SATA stored logic synoptic diagram of blade server able to programme of the present utility model;
Fig. 8 is the SATA storage IO blade synoptic diagram of blade server able to programme of the present utility model;
Fig. 9 is FIFO communication synoptic diagram between the FPGA inner treater blade apparatus of blade server able to programme of the present utility model;
Figure 10 is the high-performance of the blade server able to programme of the present utility model computing function synoptic diagram of trooping;
Among the figure, 1-backboard; 2-FPGA; 3-main channel; 4-PCIE interface; 5-primary processor blade; 6-processor blade; 7-equipment blade; 8-IO blade; 9-storage blade; 10-processor blade A; 11-processor blade B; 12-main end points; 13-EP; The mapping of 14-address and read-write steering logic; 15-programmed logical module; 16-PCIE IO interface; 17-memory bar; 18-CPU; 19-BIOS;
20-RJ45; 21-root complex; 22-network; 23-hard disk; 24-processor blade C; 25 ethernet macs; 26-PCS; 27-PMA; 28-SFP interface; 29-SATA MAC; 30-SATA interface hard disk; 31-SATA interface; 32-EP A; 33-EP B; 34-EP C; 35-FIFO A-〉B; 36-FIFO B-〉A; 37-from processor blade A; 38-from processor blade B; 39-DMA address; 40-interruption control module; 41-Ethernet logic exchange agreement.
Embodiment
Below in conjunction with accompanying drawing the utility model is elaborated.
Fig. 1 is shown in Figure 2 to be respectively physical arrangement figure and the fpga logic structural drawing of blade server able to programme of the present utility model, processor blade is inserted into backboard PCIE slot respectively, the transceiver channel of each PCIE slot is connected to the high-speed transceiver of FPGA, wherein main end points passage is connected to the passage of Altera FPGA cvp configuration feature appointment, use PCIE end points IP CORE by the corresponding a plurality of endpoint devices of slot instantiation in the FPGA, endpoint device is connected to can weave into the logic module part, this part carries out the apparatus logic programming by actual demand, can realize any digital exchange agreement.Because these end points are incorporated in the FPGA with above-mentioned physics and logical organization, so had the high-speed communication basis between the different processor blade.In follow-up explanation at the explanation of different application example.
Cvp (Configuration via Protocol) configuration mode is the FPGA configuration mode that passes through the Pcie port that Altera company 28nm FPGA device provides.EP is PCIE equipment end points (End point)
The slot that Pcie IO interface ﹠ processor blade connects is in full accord, but the high speed receiving and transmitting signal uses as device extension on the slot.
Be the primary processor blade structure of blade server able to programme of the present utility model as shown in Figure 3, the primary processor blade has front panel network interface RJ45, is used for remote update.
Embodiment 1
Blade server gigabit/ten thousand mbit ethernets expansion
As shown in Figure 4 and Figure 5.The high speed transceiver channel of using among the figure in the PCIE interface connects SFP expansion blade.PCS is high-speed transceiver physical code layer in the FPGA, and PMA is high-speed transceiver medium extra play in the FPGA.
Agreement exchange in the blade server
The FPGA (Field Programmable Gate Array) part can realize any digital exchange agreement in the FPGA, is exchanged for example with the Ethernet protocol among Fig. 6, and each blade server end points logic and ethernet mac have been realized the ethernet network interface card function among the figure.The Ethernet protocol exchange logic is realized the agreement exchange by fpga logic.
Blade server storage expansion
As shown in Figure 7 and Figure 8, EP is PCIE equipment end points (End point) among the figure, and PCS is high-speed transceiver physical code layer in the FPGA.PMA is high-speed transceiver medium extra play in the FPGA.4 high-speed channels are realized the storage expansion, and are connected to a PCIE interfacing equipment in logic respectively as the transceiver channel of 4 road SATA interfaces in the PCIE interface in FPGA.
Blade server high speed interconnected communication
As shown in Figure 9, be high-speed communication between the illustration meaning server with FIFO communication between FPGA inner treater blade apparatus, we can use more complicated internal memory sharing module and interrupt realizing the direct dma operation of big data in the practical application.
The BAR register write access FIFO A-of blade processor A by EP A among the figure〉the input data port of B.
The BAR register read visit FIFO A-of blade processor B by EP B〉the output data port of B.
In like manner:
The BAR register write access FIFO B-of blade processor B by EP B〉the input data port of A.
The BAR register read visit FIFO B-of blade processor A by EP A〉the output data port of A.
By above-mentioned fpga logic realization a high-speed data channel.
The high-performance computing function of trooping
As shown in figure 10, set up the blade processor of a PCIE slot as main system in FPGA, middle in the drawings is the primary processor blade.
Implementation procedure is as follows:
1.FPGA setting BAR0 ~ 1 when the EP endpoint device is realized in the inherence is the supervisor register space, to distribute a block size be the DMA memory headroom of DMA_SIZE to each processor blade during device initialize, and with physical address by in the DMA address register in the BAR0 write device register space.
2.FPGA setting BAR2 ~ 3 when the EP endpoint device is realized in the inherence is the shared data space of N * DMA_SIZE for the size of shining upon, wherein N is blade server quantity.Primary processor is visited the DMA memory headroom of all blade servers by BAR2, address mapping and read-write steering logic.
3. main control processor blade EP endpoint device can be controlled address mapping memory read-write module, by interrupting the control module initiation to the interruption of other processors.
4. be in the wait interrupt mode from processor when working, the primary processor blade writes deal with data DMA from the processor memory space, triggers then from processor to interrupt, and enters processing from processor, and the back of finishing dealing with is by BAR0 set handling status register.Primary processor reads state of a control, and from fetching result from processor DMA memory headroom.
Because logic is programmable in the FPGA, so above-mentioned realization is one of method.
The above only is preferred embodiment of the present utility model, not in order to limiting the utility model, all any modifications of doing within spirit of the present utility model and principle, is equal to and replaces and improvement etc., all is included within the protection domain of the present utility model.
Claims (5)
1. blade server structure able to programme, comprise that backboard and several are inserted in the processor blade on the backboard PCIE slot, it is characterized in that the transceiver channel of each PCIE slot connects the high-speed transceiver of FPGA, wherein main end points passage is connected to the passage of the cvp configuration feature appointment of FPGA, be connected with the corresponding equipment end points respectively by corresponding PCIE slot by several PCIE end points IP kernels in the FPGA, the equipment end points is connected with programmed logical module, and programmed logical module is connected with PCIE IO interface.
2. a kind of blade server structure able to programme as claimed in claim 1 is characterized in that primary processor blade in the described processor blade is provided with the front panel network interface for remote update.
3. a kind of blade server structure able to programme as claimed in claim 1, it is characterized in that described PCIE IO interface is connected with Ethernet SFP optical interface by the high speed transceiver channel, described equipment end points connects the ethernet mac in the FPGA, and ethernet mac connects PCS, and PCS connects PMA.
4. a kind of blade server structure able to programme as claimed in claim 1, it is characterized in that described equipment end points connects the ethernet mac in the FPGA, ethernet mac is connected with the Ethernet protocol exchange logic, and the Ethernet protocol exchange logic is realized the agreement exchange by fpga logic.
5. a kind of blade server structure able to programme as claimed in claim 1, it is characterized in that described equipment end points connects the SATA MAC in the FPGA, SATA MAC connects PCS, and PCS connects PMA, and described PCIE IO interface is connected with the SATA interface by the high speed transceiver channel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320068852 CN203149556U (en) | 2013-02-06 | 2013-02-06 | Programmable blade server structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN 201320068852 CN203149556U (en) | 2013-02-06 | 2013-02-06 | Programmable blade server structure |
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| CN203149556U true CN203149556U (en) | 2013-08-21 |
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| CN 201320068852 Expired - Fee Related CN203149556U (en) | 2013-02-06 | 2013-02-06 | Programmable blade server structure |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108234264A (en) * | 2017-12-29 | 2018-06-29 | 杭州迪普科技股份有限公司 | A kind of data packet forwarding method and device based on the extension of PCIe signaling interfaces |
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2013
- 2013-02-06 CN CN 201320068852 patent/CN203149556U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108234264A (en) * | 2017-12-29 | 2018-06-29 | 杭州迪普科技股份有限公司 | A kind of data packet forwarding method and device based on the extension of PCIe signaling interfaces |
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| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130821 Termination date: 20170206 |