CN203118407U - Display driving circuit and display device - Google Patents

Abstract

The utility model discloses a display driving circuit and a display device. The display driving circuit comprises a timing controller, a gate electrode driving circuit and a source electrode driving circuit. The timing controller is connected to the gate electrode driving circuit and the source electrode driving circuit, sends source electrode driving signals to the gate electrode driving circuit, and sends timing signals containing clocks, OE (output encoding) 1 and OE2 to the gate electrode driving circuit to generate gate electrode driving signals with cutting angle voltage. The display driving circuit further comprises a negative pressure generating circuit connected with the timing controller. The negative pressure generating circuit receives the timing signals containing the OE1 and OE2 from the timing controller, and generates negative voltage stacked with the gate electrode driving signals between the falling edge of the OE2 and the rising edge of the OE1. The utility model further discloses the display device with the display driving circuit. By the display driving circuit, flickers of a display device screen are reduced.

Description

Display driver circuit and display device

Technical field

The utility model relates to the display technique field, particularly a kind of gate driver circuit, display driver circuit and display device.

Background technology

In the existing gate driver circuit, control grid by clock signal and drive signal sequence, come the compartment of terrain that gate drive signal is imported next bar grid line by the first enable signal OE1, produce the top rake signal by the second enable signal OE2, thereby produce the top rake signal gate drive signal is carried out the top rake modulation and produces the gate drive signal with top rake voltage, have the gate drive signal of top rake voltage by V _GhAnd V _Gl1Generate, have the effect that reduces film flicker.As shown in Figure 1, gate drive signal (forward voltage) waveform and the signal waveform comparison diagram under Gate RC delay (capacitance-resistance delay) influence thereof for having top rake voltage.As the waveform on Fig. 1 left side, when not being subjected to Gate RC delay voltage influence, from V _GhChange to V _Gl1Divide two-stage to change, the pressure reduction of variation is still bigger, and flicker (Flicker) is more obvious, especially large scale, high-resolution liquid crystal panel, if reduce stage head, flicker can improve.

In addition, along with the continuous development of lcd technology, the high-resolution liquid crystal panel of large scale is more and more.But on the grid line of large scale liquid crystal display panel, from top to the end, Gate RC delay value is bigger with change in location, causes the high voltage V of gate drive signal _GhThe actual voltage value difference.Two waveforms about in the comparison diagram 1, the top of same grid line: Δ V _Gh=V _Gh-V _Gl1, Δ V _Gh'=V _Gh'-V _Gl1Terminal: Δ V _{Gh_a}=V _{Gh_a}-V _Gl1, Δ V _{Gh_b}=V _{Gh_b}-V _Gl1, since the influence of Gate RC delay, V _Gh≠ V _{Gh_a}, Δ V _Gh≠ Δ V _{Gh_a}, Δ V _Gh' ≠ Δ V _{Gh_b}So, V _GhDifferent with place grid line change in location with stage head, cause thin film transistor (TFT) TFT charge volume difference, pixel voltage changes with the position, and it is more little more to arrive terminal voltage, and terminal TFT charge volume is more little.Therefore, in display panels, have the problem of the electric capacity undercharge in the pixel, thereby flicker (Flicker) is serious.

The utility model content

(1) technical matters that will solve

The technical problems to be solved in the utility model is: the display screen that how to reduce to be caused by gate drive signal glimmers.

(2) technical scheme

For solving the problems of the technologies described above, the utility model provides a kind of display driver circuit, comprise: time schedule controller, gate driver circuit and source electrode drive circuit, described time schedule controller connects gate driver circuit and source electrode drive circuit, described time schedule controller sends the source drive signal to described source electrode drive circuit, and transmission comprises clock, the clock signal of the first enable signal OE1 and the second enable signal OE2 to described gate driver circuit has the gate drive signal of top rake voltage with generation, also comprise: the negative pressure that is connected with described time schedule controller produces circuit, described negative pressure produces circuit and receives the clock signal that comprises described OE1 and OE2 that described time schedule controller sends, to produce the negative voltage with described gate drive signal stack between the rising edge of the negative edge of OE2 and OE1.

Wherein, described negative pressure produces circuit and comprises: negative edge detecting unit, rising edge detecting unit and negative pressure generation unit, and described negative edge detecting unit is connected the negative pressure generation unit with the rising edge detecting unit;

The negative edge detecting unit connects described time schedule controller, detects the trigger pip that sends behind the negative edge of OE2 for generation of described negative voltage to the negative pressure generation unit;

The rising edge detecting unit connects described time schedule controller, detects to send behind the rising edge of OE1 to be used for stopping the trigger pip of described negative voltage to the negative pressure generation unit.

Wherein, described negative pressure generation unit comprises: the underbalance pulse generator.

The utility model also provides a kind of display device, comprise: array base palte, also comprise above-mentioned display driver circuit, described source electrode drive circuit connects the data line on the described array base palte, and gate driver circuit is connected the grid line on the described array base palte with negative pressure generation circuit.

(3) beneficial effect

The utility model produces the negative voltage that produces between the rising edge that circuit is negative edge and OE1 at OE2 with described gate drive signal stack by negative pressure, make gate drive signal diminish step by step, namely reduce the voltage variety on the pixel electrode, thereby alleviated the screen flicker phenomenon; And, influenced by Gate RC delay, end at same grid line, the forward voltage of negative voltage and gate drive signal, forward and negative sense torsional deformation can take place, positive negative sense torsional deformation is because polarity is opposite, can realize that the difference of previous section and aft section feedthrough (feed-through) voltage is basic identical on the same scan signal line, thereby further alleviate the screen flicker phenomenon.

Description of drawings

Fig. 1 is existing gate drive signal waveform (left side) and its signal waveform (right side) comparison diagram under Gate RC delay influence with top rake voltage.

Fig. 2 is a kind of display driver circuit structural representation of the utility model embodiment;

Fig. 3 is the connection diagram of display driver circuit and array base palte among Fig. 2;

Fig. 4 is the timing diagram of gate drive signal output waveform in the utility model, negative voltage waveform and other timing control signal;

Fig. 5 is negative voltage signal waveform (left side) and waveform (right side) comparison diagram under Gate RC delay influence thereof;

Fig. 6 is the gate drive signal waveform (left side) with top rake voltage and its signal waveform (right side) comparison diagram under Gate RC delay influence after the stack negative voltage of the present utility model.

Embodiment

Below in conjunction with drawings and Examples, embodiment of the present utility model is described in further detail.Following examples are used for explanation the utility model, but are not used for limiting scope of the present utility model.

As shown in Figure 2, the display driver circuit of present embodiment comprises: time schedule controller 210, source electrode drive circuit 220 and gate driver circuit 230, time schedule controller 210 connects source electrode drive circuit 220 and gate driver circuit 230.Time schedule controller sends the source drive signal to source electrode drive circuit 220, and transmission comprises that the clock signal of clock, OE1 and OE2 has the gate drive signal of top rake voltage with generation to gate driver circuit 230.

In order to alleviate the flicker of display device, this display driver circuit also comprises: the negative pressure that is connected with time schedule controller 210 produces circuit 240.The clock signal that time schedule controller 210 comprises clock, OE1 and OE2 in transmission also comprises this that clock signal of OE1 and OE2 is sent to negative pressure and produces circuit 240 during to gate driver circuit 230 simultaneously.This negative pressure produces the clock signal that circuit 240 receives OE1 and OE2, with at OE2 be produce between the rising edge of negative edge and OE1 be lower than described gate drive signal low level voltage and with the negative voltage of described gate drive signal stack.Namely when arriving, the OE2 negative edge produces negative voltage, this negative voltage and the gate drive signal stack with top rake voltage, make this gate drive signal further produce pressure drop, this gate drive signal is down to predetermined low-voltage when the rising edge of OE1 arrives then.Because the stack of negative voltage makes gate drive signal diminish step by step, namely reduces the voltage variety on the pixel electrode, thereby has alleviated the display screen scintillation.

In the present embodiment, negative pressure produces circuit 240 and comprises: negative edge detecting unit 241, rising edge detecting unit 242 and negative pressure generation unit 243, negative edge detecting unit 241 is connected negative pressure generation unit 243 with rising edge detecting unit 242.

Wherein, negative edge detecting unit 241 detects the trigger pip that sends behind the negative edge of OE2 for generation of negative voltage to negative pressure generation unit 243, triggers negative pressure generation unit 243 and produces negative voltage.Rising edge detecting unit 242, detect to send behind the rising edge of OE1 and be used for stopping the trigger pip of negative voltage to the negative pressure generation unit, so that negative pressure generation unit 243 stops to produce negative voltage, negative pressure generation unit 243 can be the underbalance pulse generator, this underbalance pulse generator can produce a negative voltage between the rising edge of OE2 negative edge and OE1, also can produce a plurality of negative voltage that magnitude of voltage diminishes gradually, negative voltage is more many, the level that gate drive signal diminishes step by step is more many, reduce the voltage variety on the pixel electrode further, thereby alleviated flicker further.

The utility model also provides a kind of display device as shown in Figure 3, comprising: array base palte (equivalent circuit diagram of one of them pixel cell on the array base palte has been shown among Fig. 3) also comprises above-mentioned display driver circuit.Wherein, the data line 300 that source electrode drive circuit 220 connects on the array base palte, gate driver circuit 230 is connected the grid line 400 on the array base palte with negative pressure generation circuit 240, the gate drive signal with top rake voltage is being input to grid line 400 between the rising edge of OE2 negative edge and OE1 with after the negative voltage stack.

Principle of work below in conjunction with the display driver circuit that drives sequential chart explanation present embodiment.

As shown in Figure 4, CKL, OE1 and OE2 are the clock signal waveform that time schedule controller 210 produces.G _nAnd G _N+1Be the n bar of gate drivers 230 generations and the gate drive signal waveform of n+1 bar grid line, its high voltage is V _Gh, low-voltage is V _Gl1V _Gl2For negative pressure produces the negative voltage signal waveform that circuit 240 produces, its negative voltage value is ﹣ V _a

To having negative voltage signal ﹣ V of gate drive signal stack of top rake voltage _a, to realize that gate drive signal is by V _GhTo V _Gh1, V _Gh1To V _Gh2, V _Gh2To V _Gl1Diminish step by step.If do not superpose negative voltage, gate drive signal is directly from V so _Gh1Drop to V _Gl1, stage head Δ V _pChange greatlyyer, the voltage variety on the pixel electrode is also bigger, can produce flicker; Between the rising edge of OE2 negative edge and OE1, also namely after the top rake voltage superimposed voltage value be ﹣ V _a(less than V _Gh1) negative voltage, make gate drive signal diminish step by step, simultaneously stage head Δ V _pAlso diminish thereupon, thereby alleviate scintillation.

As shown in Figure 5, be negative voltage signal waveform (left side waveform among the figure) and the signal waveform under Gate RC delay influence (the right waveform among the figure) thereof.Since the influence of Gate RC delay, the negative voltage signal V of stack _Gl2The negative sense torsional deformation has taken place, and its magnitude of voltage is by ﹣ V _aBecome ﹣ V _b, wherein, V _bLess than V _a

As shown in Figure 6, have waveform and the signal waveform under Gate RC delay influence thereof behind the gate drive signal stack negative voltage signal of top rake voltage.The top of same grid line: Δ V _Gh=V _Gh-V _Gl1, Δ V _Gh2=V _Gh2-V _Gl1Terminal: Δ V _{Gh_c}=V _{Gh_c}-V _Gl1, Δ V _{Gh_e}=V _{Gh_e}-V _Gl1The negative voltage signal V of gate drive signal and stack _Gl2The polarity that forward and negative sense torsional deformation take place respectively is opposite, therefore, has gate drive signal and the negative voltage signal V of top rake voltage _Gl2After the stack, V _Gh1And V _{Gh_d}Substantially equal, V _Gh2And V _{Gh_e}Substantially equal, so Δ V _Gh2With Δ V _{Gh_e}Substantially equal, thus realized that the difference of previous section and aft section feedthrough (feed-through) voltage is basic identical on the same scan signal line, thus reduce the flicker problem of liquid crystal panel.

Above embodiment only is used for explanation the utility model; and be not to restriction of the present utility model; the those of ordinary skill in relevant technologies field; under the situation that does not break away from spirit and scope of the present utility model; can also make a variety of changes and modification; therefore all technical schemes that are equal to also belong to category of the present utility model, and scope of patent protection of the present utility model should be defined by the claims.

Claims (4)

1. A display driving circuit, comprising: a timing controller, a gate driving circuit and a source driving circuit, the timing controller is connected to the gate driving circuit and the source driving circuit, and the timing controller sends a source driving signal To the source drive circuit, and send the timing signal including the clock, the first enable signal OE1 and the second enable signal OE2 to the gate drive circuit to generate a gate drive signal with a clipping voltage, its characteristic In that, it also includes: a negative voltage generation circuit connected to the timing controller, the negative voltage generation circuit receives the timing signal including the OE1 and OE2 sent by the timing controller, and uses the negative voltage generation circuit on the falling edge of OE2 and OE1 A negative voltage superimposed on the gate drive signal is generated between the rising edges of . 2. The display drive circuit according to claim 1, wherein the negative voltage generation circuit comprises: a falling edge detection unit, a rising edge detection unit and a negative pressure generation unit, the falling edge detection unit and the rising edge detection The unit is connected to a negative pressure generating unit; The falling edge detection unit is connected to the timing controller, and sends a trigger signal for generating the negative voltage to the negative voltage generating unit after detecting the falling edge of OE2; The rising edge detection unit is connected to the timing controller and sends a trigger signal for stopping the negative voltage to the negative voltage generating unit after detecting the rising edge of OE1. 3. The display driving circuit according to claim 2, wherein the negative pressure generating unit comprises: a negative pressure pulse generator. 4. A display device, comprising: an array substrate, further comprising the display driving circuit according to any one of claims 1 to 3, the source driving circuit connected to the data line on the array substrate , the gate driving circuit and the negative voltage generating circuit are connected to the gate lines on the array substrate.

Images