CN203102064U - Overshoot protection circuit of low-dropout linear regulator (LDO) and LDO - Google Patents

Abstract

The utility model discloses an overshoot protection circuit of a low-dropout linear regulator (LDO). The overshoot protection circuit of the LDO comprises an RC delay circuit and an upward-pull PMOS transistor, wherein the RC delay circuit is composed of a first PMOS transistor and a semiconductor capacitor. A source electrode of the first PMOS transistor is connected with supply voltage, and a grid electrode of the PMOS transistor is grounded. A drain electrode of the PMOS transistor is connected with one end of the semiconductor capacitor and a grid electrode of the upward-pull PMOS transistor. The other end of the semiconductor capacitor is grounded. A source electrode of the upward-pull PMOS transistor is connected with the supply voltage, and a drain electrode of the upward-pull PMOS transistor is connected with a grid electrode of a grid electrode of a power PMOS transistor of the LDO. The utility model further discloses the LDO adopting the overshoot protection circuit. The overshoot protection circuit can supply effective protection for overquick starting of the LDO, and can effectively save the area of a chip.

Description

Overshoot protection circuit and the LDO of LDO

Technical field

The utility model relates to LDO(low-dropout linear regulator low pressure difference linear voltage regulator) field, particularly relate to the overshoot protection circuit when a kind of LDO is too fast to be started.The utility model also relates to a kind of LDO that adopts described overshoot protection circuit.

Background technology

Outstanding advantages such as that LDO has is simple in structure, low noise and low-power consumption have a wide range of applications in portable type electronic product.The supply voltage of LDO is higher voltage often, and output voltage is that stable lower voltage is to satisfy the requirement of digital circuit low-power consumption.

Referring to shown in Figure 1, existing LDO, its supply voltage often powers on very fast, and the time is in the ns magnitude, at this moment LDO loop operate as normal not also; And the size of power P MOS transistor M0 is often bigger, grid capacitance is bigger, its grid voltage Vgate is difficult to follow the supply voltage ascending velocity of LDO, cause power P MOS transistor M0 to open, have bigger electric current to flow into output terminal, thereby cause output voltage V out overshoot, if the overshoot of LDO output voltage V out is too high, and the device after the output voltage V out is a low-voltage device, and breakdown risk is then arranged, and easily low voltage mos transistor is produced infringement.

Along with the development of integrated circuit processing technique, the live width of MOS transistor is more and more narrow, and the thickness of gate oxide is also more and more thinner, and the voltage breakdown of MOS transistor is more and more lower.Therefore the overshoot that suppresses the LDO output voltage necessity very that then seems.

Existing LDO often adopts bigger electric capacity (as the capacitor C among Fig. 1 0), even adopts with off-chip capacitive and hold the overshoot that prevents output voltage, and its shortcoming is that the shared chip area of electric capacity is often bigger.

The utility model content

The technical problems to be solved in the utility model provides the overshoot protection circuit of a kind of LDO, can provide effective overshoot protection to the too fast startup of LDO, and can effectively save chip area; For this reason, the utility model also will provide a kind of LDO that adopts described overshoot protection circuit.

For solving the problems of the technologies described above, the overshoot protection circuit of LDO of the present utility model comprises: draw the PMOS transistor on the RC delay circuit and;

Described RC delay circuit is made up of a PMOS transistor and semiconductor electric capacity; The transistorized source electrode of the one PMOS is connected with supply voltage, its grounded-grid, its drain electrode and an end of semicoductor capacitor with on draw the transistorized grid of PMOS to be connected; The other end ground connection of semicoductor capacitor;

On draw the transistorized source electrode of PMOS to be connected with supply voltage, its drain electrode is connected with the grid of the power P MOS transistor of low pressure difference linear voltage regulator LDO.

Described semicoductor capacitor is polysilicon capacitance, metal-insulator medium-metal M IM electric capacity or one the 2nd PMOS transistor; When adopting the 2nd PMOS transistor as semicoductor capacitor, its grid is as an end of electric capacity, and its source electrode and drain electrode are as the other end ground connection of electric capacity.

Described low pressure difference linear voltage regulator LDO comprises:

One error amplifier, a power P MOS transistor, first resistance and second resistance;

The source electrode of described power P MOS transistor is connected with supply voltage, and first resistance and second resistance string are associated between the drain electrode and ground of power P MOS transistor;

The reverse input end input reference voltage of described error amplifier, its positive input is connected with the node that second resistance is connected in series with first resistance, and its output terminal is connected with the grid of power P MOS transistor;

The drain electrode of power P MOS transistor is as the output voltage terminal of low pressure difference linear voltage regulator LDO; Wherein, also comprise an overshoot protection circuit recited above.

The RC delay circuit that the utility model adopts common PMOS transistor to form, can adjust the PMOS transistor size as required, thereby can effectively prevent the output voltage overshoot phenomenon that the LDO electrifying startup causes when too fast, not need bigger capacity cell, can effectively save chip area.

Description of drawings

Below in conjunction with accompanying drawing and embodiment the utility model is described in further detail:

Fig. 1 is existing LDO circuit theory diagrams;

Fig. 2 is the LDO circuit theory diagrams that adopt the utility model one embodiment overshoot protection circuit.

Embodiment

Referring to shown in Figure 2, described LDO comprises: an error amplifier, a power P MOS transistor M0, resistance R 1, R2.

The source electrode of described power P MOS transistor M0 is connected with supply voltage VDD, and resistance R 1, R2 are connected between the drain electrode and ground of power P MOS transistor M0.

The reverse input end input reference voltage Vref of described error amplifier, its positive input is connected with the node that resistance R 1, R2 are connected in series, and its output terminal is connected with the grid of power supply PMOS transistor M0.

Part among Fig. 2 in the frame of broken lines is described overshoot protection circuit one embodiment, and it comprises: draw PMOS transistor M3 on the RC delay circuit and.Described RC delay circuit is made up of a PMOS transistor M1 and the 2nd PMOS transistor M2; The transistorized source electrode M1 of the one PMOS is connected with supply voltage VDD, its grounded-grid, its drain electrode and the grid of the 2nd PMOS transistor M2 with on draw the grid of PMOS transistor M3 to be connected; Source electrode and the grounded drain of the 2nd PMOS transistor M2.The one PMOS transistor M1 is as resistance, and the 2nd PMOS transistor M2 is as electric capacity.On draw the source electrode of PMOS transistor M3 to be connected with supply voltage VDD, its drain electrode is connected with the grid of power P MOS transistor M0.

The drain electrode of power P MOS transistor M0 is as the output voltage terminal of LDO, output voltage V out.Be connected a storage capacitor C1 between the output voltage terminal of LDO and the ground.Storage capacitor C1 can prevent the overshoot of output voltage.Owing to adopted the overshoot protection circuit, the capacity of capacitor C 1 can reduce greatly than the capacitor C 0 of existing LDO output voltage terminal, to save area of chip.

During original state, the grid of the 2nd PMOS transistor M2 is a zero potential, on draw PMOS transistor M3 to open, the output voltage V gate(of described error amplifier is the grid voltage of power P MOS transistor M0) identical with supply voltage VDD, power P MOS transistor M0 is in closed condition.When the supply voltage VDD of LDO started with the speed of ns magnitude, a PMOS transistor M1 and the 2nd PMOS transistor M2 formed certain delay, and power P MOS transistor M0 remains in closed condition; Behind the LDO loop start, on draw the grid voltage of PMOS transistor M3 to raise to be supply voltage VDD, to become high-impedance state, do not influence the operate as normal of LDO loop thereby close.PMOS transistor M1, the size of M2 and M3 can suitably be adjusted as required, other the 2nd PMOS transistor M2 also can be with polysilicon (poly) electric capacity or MIM(metal-insulator medium-metal) electric capacity realizes.

Though the utility model utilizes specific embodiment to describe, the explanation of embodiment is not limited scope of the present utility model.The one skilled in the art is by with reference to explanation of the present utility model, under the situation that does not deviate from spirit and scope of the present utility model, carries out various modifications easily or can make up embodiment.

Claims (3)

1. the overshoot protection circuit of a low pressure difference linear voltage regulator LDO is characterized in that, comprising: draw the PMOS transistor on the RC delay circuit and;

Described RC delay circuit is made up of a PMOS transistor and semiconductor electric capacity; The transistorized source electrode of the one PMOS is connected with supply voltage, its grounded-grid, its drain electrode and an end of semicoductor capacitor with on draw the transistorized grid of PMOS to be connected; The other end ground connection of semicoductor capacitor;

On draw the transistorized source electrode of PMOS to be connected with supply voltage, its drain electrode is connected with the grid of the power P MOS transistor of low pressure difference linear voltage regulator LDO.

2. overshoot protection circuit as claimed in claim 1 is characterized in that: described semicoductor capacitor is polysilicon capacitance, metal-insulator medium-metal M IM electric capacity or one the 2nd PMOS transistor; When adopting the 2nd PMOS transistor as semicoductor capacitor, its grid is as an end of electric capacity, and its source electrode and drain electrode are as the other end ground connection of electric capacity.

3. low pressure difference linear voltage regulator LDO comprises:

One error amplifier, a power P MOS transistor, first resistance and second resistance;

The source electrode of described power P MOS transistor is connected with supply voltage, and first resistance and second resistance string are associated between the drain electrode and ground of power P MOS transistor;

The reverse input end input reference voltage of described error amplifier, its positive input is connected with the node that second resistance is connected in series with first resistance, and its output terminal is connected with the grid of power P MOS transistor;

The drain electrode of power P MOS transistor is as the output voltage terminal of low pressure difference linear voltage regulator LDO; It is characterized in that, also comprise a claim 1 or 2 described overshoot protection circuit.

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