CN203055466U - Shift register unit, shift register, array substrate and display device - Google Patents

Abstract

The embodiment of the utility model discloses a shifting register unit, a shifting register, an array substrate and a display device, relates to the field of displays and can independently reset all the shifting register units. The shifting register unit comprises a sampling part, an outputting part and a resetting part, wherein the sampling part comprises a first switching tube and a second switching tube; the outputting part comprises a fifth switching tube, a sixth switching tube, a first capacitor and a second capacitor; and the resetting part comprises a third switching tube and a fourth switching tube.

Description

Shift register unit, shift register, array substrate and display device

technical field

The utility model relates to the field of displays, in particular to a shift register unit, a shift register, an array substrate and a display device.

Background technique

With the continuous development of display technology, active matrix displays using thin film transistors have become the most common flat panel display devices, and their gate drive circuits are usually implemented in the form of shift registers, which are composed of multiple The shift register units are composed of register units, and each shift register unit outputs signals in sequence to realize the progressive driving of the gate.

The existing shift register unit includes three working states of sampling, output and reset. In two adjacent shift register units, the output signal of the latter shift register unit is used as the reset signal of the former shift register unit, so that the former shift register unit stops outputting. However, if the previous shift register unit does not receive the reset signal from the latter shift register unit, the previous shift register unit will not stop outputting. Therefore, in the prior art, the reset of the previous shift register unit is controlled by the latter shift register unit, if the reset signal from the latter shift register unit cannot be fed back smoothly or delayed to the previous shift register unit , the previous shift register unit will not stop outputting according to the predetermined time, which may cause the failure of the entire array substrate and even the liquid crystal display. Therefore, it is necessary to solve the problem that the shift register unit cannot be reset independently.

Utility model content

The technical problem to be solved by the utility model is to provide a shift register unit, a shift register, an array substrate and a display device, so that each shift register unit can be reset independently.

In order to solve the above technical problems, the utility model adopts the following technical solutions:

The first aspect of the utility model provides a shift register unit, including:

Sampling section, output section and reset section,

Wherein, the sampling part includes a first switch tube and a second switch tube, the output part includes a fifth switch tube, a sixth switch tube, a first capacitor and a second capacitor, and the reset part includes a third switch tube, The fourth switch tube;

The source of the first switch tube is connected to the input terminal of the shift register unit to receive the input signal from the input terminal, the gate of the first switch tube is connected to the first clock signal; the second switch tube The gate and source of the third switching tube are connected to the second clock signal, and the second clock signal is inverse phase to the first clock signal; the gate and source of the third switching transistor are connected to the first clock signal; The gate of the fourth switching tube is connected to the second clock signal, the source of the fourth switching tube is connected to the power input signal; the source of the fifth switching tube is connected to the second clock signal, and the fifth switching tube is connected to the second clock signal. The gate of the switch tube is connected to the drains of the first switch tube and the second switch tube, the drain of the fifth switch tube is connected to the output end of the shift register unit; the sixth switch tube The gate is connected to the drains of the third switching tube and the fourth switching tube, the source of the sixth switching tube is connected to the power input signal, and the drain of the sixth switching tube is connected to the shift The output end of the register unit; one end of the first capacitor is connected to the gate of the fifth switch tube, and the other end is connected to the output end of the shift register unit; one end of the second capacitor is connected to the sixth switch The grid of the tube, and the other end is connected to the power input signal.

The first to sixth switching transistors are all MOS transistors or thin film transistors.

The thin film transistor is a P-type thin film transistor or an N-type thin film transistor.

When the first to sixth switch tubes are all P-type thin film transistors, the power input signal is at a high level;

In the first time period, the input signal is low level, the first clock signal is low level, and the second clock signal is high level, then the output signal of the shift register unit is high level;

In the second time period, the input signal is high level, the first clock signal is high level, and the second clock signal is low level, then the output signal of the shift register unit is low level;

In the third time period, the input signal is at high level, the first clock signal is at low level, and the second clock signal is at high level, then the output signal of the shift register unit is at high level level.

When the first to sixth switch tubes are all N-type thin film transistors, the power input signal is at a low level;

In the first time period, the input signal is high level, the first clock signal is high level, and the second clock signal is low level, then the output signal of the shift register unit is low level;

In the second time period, the input signal is low level, the first clock signal is low level, and the second clock signal is high level, then the output signal of the shift register unit is high level;

During the third time period, the input signal is at low level, and the first clock signal is at high level,

When the second clock signal is at low level, the output signal of the shift register unit is at low level.

The second aspect of the utility model provides a shift register, including n cascaded above-mentioned shift register units, where n is an integer greater than 1, wherein the input end of the first shift register unit is connected to To the signal input end of the shift register, the output end of the nth shift register unit is connected to the signal output end of the shift register.

The third aspect of the present invention provides an array substrate, including the above-mentioned shift register.

The fourth aspect of the utility model provides a liquid crystal display, including the above-mentioned array substrate.

In the embodiment of the utility model, the structure of the shift register unit is such that the shift register unit can output the corresponding output signal after receiving the input signal, and reset itself after outputting the output signal without waiting until the next After the output signal of a shift register unit is used as a reset signal, the reset is performed according to the reset signal. This ensures the normal operation of the shift register unit, thereby ensuring the normal operation of the entire array substrate and even the liquid crystal display.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings that need to be used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description are only the present invention For some novel embodiments, those of ordinary skill in the art can also obtain other drawings based on these drawings without any creative work.

Fig. 1 is the structural representation of the shift register unit in the utility model embodiment;

FIG. 2 is a schematic structural diagram of a shift register unit of a P-type thin film transistor in an embodiment of the present invention;

3 is a timing diagram of a shift register unit of a P-type thin film transistor in an embodiment of the present invention;

4 is a schematic structural diagram of a shift register unit of an N-type thin film transistor in an embodiment of the present invention;

FIG. 5 is a timing diagram of a shift register unit of an N-type thin film transistor in an embodiment of the present invention.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of them. . Based on the embodiments of the present utility model, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the scope of protection of the present utility model.

The first aspect of the embodiment of the present invention provides a shift register unit. In order to facilitate the description of the shift register unit, as shown in FIG. 1, the shift register unit includes:

Wherein, the sampling part includes a first switch tube T1 and a second switch tube T2, the output part includes a fifth switch tube T5, a sixth switch tube T6, a first capacitor C1 and a second capacitor C2, and the reset part Including the third switching tube T3 and the fourth switching tube T4;

Specifically, the source of the first switching transistor T1 is connected to the input terminal of the shift register unit to receive the input signal IN from the input terminal, and the gate of the first switching transistor T1 is connected to the first clock signal CK. ; The gate and source of the second switching transistor T2 are connected to the second clock signal CKB, and the second clock signal CKB is inverse to the first clock signal CK; the gate and the source of the third switching transistor T3 The source is connected to the first clock signal CK; the gate of the fourth switching transistor T4 is connected to the second clock signal CKB, and the source of the fourth switching transistor T4 is connected to the power input signal V; the fifth The source of the switching transistor T5 is connected to the second clock signal CKB, the gate of the fifth switching transistor T5 is connected to the drains of the first switching transistor T1 and the second switching transistor T2, and the fifth switching transistor T5 The drain of the transistor T5 is connected to the output terminal of the shift register unit; the gate of the sixth switching transistor T6 is connected to the drains of the third switching transistor T3 and the fourth switching transistor T4, and the sixth switching transistor T6 is connected to the drain of the fourth switching transistor T4. The source of the switch tube T6 is connected to the power input signal V, the drain of the sixth switch tube T6 is connected to the output terminal of the shift register unit; one end of the first capacitor C1 is connected to the fifth switch tube The other end of the gate of T5 is connected to the output end of the shift register unit; one end of the second capacitor C2 is connected to the gate of the sixth switching transistor T6, and the other end is connected to the power input signal V.

In the technical solution of this embodiment, the structure of the shift register unit is such that the shift register unit can output the corresponding output signal after receiving the input signal, and reset itself after outputting the output signal, without waiting until the next After the output signal of a shift register unit is used as a reset signal, the reset is performed according to the reset signal. This ensures the normal operation of the shift register unit, thereby ensuring the normal operation of the entire array substrate and even the liquid crystal display.

It should be noted that, in the embodiment of the present invention, the high level is represented by VGH, and the low level is represented by VGL.

Preferably, the first to sixth switching transistors may all be MOS transistors or thin film transistors. Further, the thin film transistor may be a P-type thin film transistor or an N-type thin film transistor, wherein, because of the high mobility of the polysilicon thin film transistor, it is especially suitable for a shift register unit.

As shown in Figure 2, when the first to sixth switching transistors are all P-type thin film transistors,

In the first time period t1, the input signal IN is at low level VGL, the first clock signal CK is at low level VGL, and the second clock signal CKB is at high level VGH, then the shift The output signal OUT of the register unit is a high level VGH;

Specifically, within the first time period t1, the shift register unit enters a sampling phase.

At this time, the input signal IN is at low level VGL, and the first clock signal CK is at low level VGL, so that the first and third switching transistors T1 and T3 are turned on; at the same time, due to the second clock The signal CKB is inverse to the first clock signal CK, then the second clock signal CKB is VGH, and the second switch T2 and the fourth switch T4 cannot be turned on. So at this time, the levels of points N1 and N2 are correspondingly pulled down to (low level VGL+Vth (threshold voltage of any thin-film transistor)), so the sixth switching tube T6 is turned on, because the sixth switching tube T6 The source is connected to the high level VGH, and the drain is connected to the output terminal of the shift register unit. Then the output signal OUT of the shift register unit is at a high level VGH.

And because the level of point N1 is (low level VGL+Vth), the output terminal of the sixth switching tube T6 outputs a high level VGH. A capacitor C1 is charged to charge the input signal IN, and the voltage difference across the first capacitor C1 is (high level VGH−low level VGL−threshold voltage Vth).

In the second time period t2, the input signal is at high level VGH, the first clock signal CK is at high level VGH, and the second clock signal CKB is at low level VGL, then the shift register The output signal of the unit is low level VGL;

Specifically, within the second time period t2, the shift register unit enters an output stage.

At this time, both the input signal IN and the first clock signal CK are at a high level VGH, so that the first switching tube T1 is turned off, and due to the effect of the first capacitor C1, the level at point N1 is maintained and is still (low level VGL+threshold voltage Vth), so T5 is turned on and outputs low level VGL. At the same time, since the level of the second clock signal CKB is low level VGL, the second and fourth switching transistors T2 and T4 are turned on, and since the source of the fourth switching transistor T4 is connected to the high level VGH, at this time, the The level is high level VGH, and the sixth switching tube T6 is turned off. At this time, the output signal of the shift register unit is the low level VGL output by the fifth switching transistor T5.

In the third time period t3, the input signal IN is at high level VGH, the first clock signal CK is at low level VGL, and the second clock signal CKB is at high level VGH, then the shift The output signal of the register unit is a high level VGH.

Specifically, within the third time period t3, the shift register unit enters a reset phase.

At this time, the first clock signal CK is at low level VGL, the input signal IN is at high level VGH, the first switching tube T1 is turned on, so that the level at point N1 is pulled up to high level VGH, and the fifth switching tube T5 is turned off. At the same time, since the first clock signal CK is at low level VGL, the third switching tube T3 is turned on, and the potential of N2 is pulled down to (low level VGL+threshold voltage Vth), so that the sixth switching tube T6 is turned on, so that The output signal OUT of the shift register unit is pulled high again to a high level VGH to realize the independent reset of the shift register unit.

In addition, in other stages of the shift register unit, the second capacitor C2 keeps the point N2 at a low level VGL, which ensures the conduction of the sixth switching tube T6, so that the output signal OUT is always at a high level VGH, improving the Stability of the output signal OUT.

As shown in Figure 4, when the first to sixth switch tubes are all N-type thin film transistors, the shift register unit can also realize an independent reset function. At this time, the power input signal V is a low level VGL, because the N The working process of the shift register unit of the P-type thin film transistor is similar to that of the P-type thin film transistor, and will not be repeated here.

It should be noted that the input signal IN, the first clock signal CK, the second clock signal CKB, and the output signal OUT of the shift register unit of the N-type thin film transistor are all inverted from those of the shift register unit of the P-type thin film transistor. For details, see Figure 5.

In addition, the source and drain of a general thin film transistor can be set interchangeably.

The second aspect of this embodiment provides a shift register, including n cascaded above-mentioned shift register units, where n is an integer greater than 1, wherein the input terminal of the first shift register unit connected to the signal input end of the shift register, and the output end of the nth shift register unit is connected to the signal output end of the shift register.

Since the shift register provided by the embodiment of the utility model has the same technical features as the shift register unit provided by the above-mentioned embodiment of the utility model, it can also produce the same technical effect and solve the same technical problem.

A third aspect of this embodiment provides an array substrate, including the above-mentioned shift register.

A fourth aspect of this embodiment provides a display device, including the above-mentioned array substrate. The liquid crystal display can be any product or component with a display function, such as a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television set, a monitor, a notebook computer, a digital photo frame, a navigator, and the like. In particular, active organic light-emitting diode displays using low-temperature polysilicon technology.

The above is only a specific embodiment of the present utility model, but the scope of protection of the present utility model is not limited thereto. Anyone familiar with the technical field can easily think of changes or changes within the technical scope disclosed by the utility model Replacement should be covered within the protection scope of the present utility model. Therefore, the protection scope of the present utility model should be based on the protection scope of the claims.

Claims (8)

1. a shift register cell is characterized in that, comprising:

Sampling section, output and the part that resets,

Wherein, described sampling section comprises first switching tube and second switch pipe, and described output comprises the 5th switching tube, the 6th switching tube, first electric capacity and second electric capacity, and described reset portion branch comprises the 3rd switching tube, the 4th switching tube;

The source electrode of described first switching tube connects the input end of described shift register cell, receives the input signal from described input end, and the grid of described first switching tube connects first clock signal; The grid of described second switch pipe is connected the second clock signal with source electrode, described second clock signal and described first clock signal are anti-phase; The grid of described the 3rd switching tube is connected described first clock signal with source electrode; The grid of described the 4th switching tube connects described second clock signal, and the source electrode of described the 4th switching tube connects power supply input signal; The source electrode of described the 5th switching tube connects described second clock signal, and the grid of described the 5th switching tube connects the drain electrode of described first switching tube and described second switch pipe, and the drain electrode of described the 5th switching tube connects the output terminal of described shift register cell; The grid of described the 6th switching tube connects the drain electrode of described the 3rd switching tube and described the 4th switching tube, and the source electrode of described the 6th switching tube connects described power supply input signal, and the drain electrode of described the 6th switching tube connects the output terminal of described shift register cell; One end of described first electric capacity connects the grid of described the 5th switching tube, and the other end connects the output terminal of described shift register cell; One end of described second electric capacity connects the grid of described the 6th switching tube, and the other end connects described power supply input signal.

2. shift register cell according to claim 1 is characterized in that, described first to the 6th switching tube is metal-oxide-semiconductor or thin film transistor (TFT).

3. shift register cell according to claim 2 is characterized in that, described thin film transistor (TFT) is P type thin film transistor (TFT) or is the N-type thin film transistor (TFT).

4. shift register cell according to claim 3 is characterized in that, when described first to the 6th switching tube was P type thin film transistor (TFT), described power supply input signal was high level;

In very first time section, described input signal is low level, and described first clock signal is low level, and described second clock signal is high level, and then the output signal of described shift register cell is high level;

In second time period, described input signal is high level, and described first clock signal is high level, and described second clock signal is low level, and then the output signal of described shift register cell is low level;

In the 3rd time period, described input signal is high level, and described first clock signal is low level, and described second clock signal is high level, and then the output signal of described shift register cell is high level.

5. shift register cell according to claim 3 is characterized in that, when described first to the 6th switching tube was the N-type thin film transistor (TFT), described power supply input signal was low level;

In very first time section, described input signal is high level, and described first clock signal is high level, and described second clock signal is low level, and then the output signal of described shift register cell is low level;

In second time period, described input signal is low level, and described first clock signal is low level, and described second clock signal is high level, and then the output signal of described shift register cell is high level;

In the 3rd time period, described input signal is low level, and described first clock signal is high level, and described second clock signal is low level, and then the output signal of described shift register cell is low level.

6. shift register, it is characterized in that, comprise n cascade as each described shift register cell of claim 1-5, described n is the integer greater than 1, wherein, the input end of the 1st described shift register cell is connected to the signal input part of described shift register, and the output terminal of n described shift register cell is connected to the signal output part of described shift register.

7. an array base palte is characterized in that, comprises shift register as claimed in claim 6.

8. a display device is characterized in that, comprises array base palte as claimed in claim 7.

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