CN203038923U - Radiation hardened silicon on insulator structure - Google Patents

Abstract

The utility model relates to the field of integrated circuits, in particular to a radiation-resistant and reinforced silicon-on-insulator structure. In the utility model, the polysilicon substrate is covered with a polysilicon oxide layer (201), the oxide layer is covered with a semi-insulating polysilicon film (301), the semi-insulating polysilicon layer is covered with a silicon dioxide layer (401), and the silicon dioxide layer is covered with a silicon dioxide layer (401). Covered with a polysilicon layer (601). There are vias (501) between the polysilicon substrate and the uppermost polysilicon layer of the structure. The utility model proposes a structure specially designed by adding a semi-insulating polysilicon film (SIPOS) with charge balancing function in the double-layer _SiO2 layer as the buried insulating layer of the SOI structure, and designs on the buried insulating layer The through-hole structure is used as a window to form the top SOI layer by selective epitaxial growth, and it also has the functions of heat conduction and charge conduction, which improves the heat conduction, heat dissipation capability and anti-total dose radiation performance of SOI devices, and achieves the improvement of thermal performance of SOI devices. Stability and radiation hardening purposes.

Description

A radiation-hardened silicon-on-insulator structure

technical field

The utility model relates to the field of integrated circuits, in particular to a radiation-resistant reinforced silicon-on-insulator (SOI) structure. the

Background technique

SOI (Silicon On Insulator) technology is a new type of microelectronic chip technology that grows a thin layer of single crystal silicon on the insulating layer and makes a semiconductor layer on the insulating layer to form a unique structure. SOI (Silicon On Insulator) technology has attracted attention since the 1960s, and has developed greatly since the 1980s. It gradually entered the commercial field in the late 1990s. Because SOI devices have good scaling properties, the application of SOI technology in deep submicron VLSI is very attractive and has a good development prospect. the

As a full dielectric isolation technology, SOI has many incomparable advantages compared with the bulk silicon structure because the device and the substrate are separated by a buried oxide layer. SOI devices have the advantages of low power consumption, strong radiation resistance, high integration density, fast speed, simple process, strong anti-interference ability, and eliminate the latch-up effect of bulk silicon devices, but the SOI structure itself also has some parasitic effects. In radiation-resistant applications, compared with fully depleted SOI devices, partially depleted SOI devices have obvious advantages in resisting total dose radiation, but the floating body effect in partially depleted SOI devices will seriously affect the characteristics of analog circuits. , It will also lead to logic errors and increased power consumption of digital circuits, which affects the application of SOI technology in the field of radiation resistance to a certain extent. the

The relevant characteristics of semi-insulating polysilicon layer (SIPOS) mainly include that SIPOS can effectively prevent charge accumulation and charge pollution on the device surface. SIPOS is not only semi-insulating, but also electrically neutral, and there are high-density traps in the film. When the SIPOS film encounters ions, it will induce charges of opposite polarity near the surface. These charges are captured by the high-density traps in the SIPOS film, thereby forming a space charge region, which has a shielding effect on the external electric field. Based on the above characteristics of SIPOS, its application in radiation-resistant hardening technology is of great significance. the

Contents of the invention

The purpose of the utility model is to provide a high SOI device thermal stability and anti-radiation reinforced SOI structure. the

The purpose of this utility model is achieved in that:

The polysilicon substrate is covered with a polysilicon oxide layer (201), the oxide layer is covered with a semi-insulating polysilicon layer (301), the semi-insulating polysilicon layer is covered with a silicon dioxide layer (401), and the silicon dioxide layer is covered with polysilicon layer (601). the

There are vias (501) between the polysilicon substrate and the uppermost polysilicon layer of the structure. the

The beneficial effects of the utility model are:

The utility model proposes a structure specially designed by adding a semi-insulating polysilicon layer (SIPOS) with a charge balancing function in the double-layer _SiO2 layer as a buried insulating layer of the SOI structure, and a design is made on the buried insulating layer. The through-hole structure is used as a window to form the top SOI layer by selective epitaxial growth, and it also has the functions of heat conduction and charge conduction, which improves the heat conduction, heat dissipation and radiation resistance of SOI devices, and achieves the improvement of the thermal stability of SOI devices and Anti-radiation hardening purpose.

Description of drawings

Fig. 1P-type or N-type doped polysilicon substrate schematic diagram;

Fig. ₂ forms SiO on the polysilicon substrate surface The schematic diagram of the thin film;

Figure 3 forms a schematic diagram of a SIPOS layer on the surface of the oxide layer;

Fig. 4 forms a thin SiO _layer schematic diagram on the surface of the SIPOS layer;

Figure 5 forms a schematic diagram of a through hole on an insulating layer;

Fig. 6 is a schematic diagram of generating a single crystal silicon layer on an insulating layer. the

Detailed ways

Below in conjunction with accompanying drawing, the utility model is further described in detail. the

The utility model relates to an anti-radiation reinforced SOI structure. In particular, the semi-insulating polysilicon layer (SIPOS) is combined with the conventional SOI structure, and the structure formed by adding the semi-insulating polysilicon layer (SIPOS) in the double-layer SiO ₂ layer is used as the buried insulating layer of the SOI structure, and in the buried insulating layer A through-hole structure is designed on the layer. It is mainly used in the fields of anti-radiation, low voltage, low power consumption, and high reliability integrated circuits.

1. The design feature of this utility model is that the structure formed by adding a semi-insulating polysilicon layer (SIPOS) into the double-layer SiO ₂ layer is used as the buried insulating layer of the SOI structure. And a through-hole structure is designed in the buried insulating layer. Refer to Figure 6 for details.

2. First select a polysilicon substrate, as shown in Figure 1. On the polysilicon substrate, the oxide layer 201 in FIG. 2 is formed by thermal oxidation growth method, and its thickness is determined by the process used and design requirements. Its structure is shown in FIG. 2 . The oxide layer plays a role of dielectric isolation in the SOI structure. the

3. On the oxide layer 201 shown in FIG. 2, the semi-insulating polysilicon (SIPOS) layer 301 in FIG. 3 is formed by low-pressure vapor deposition (LPVCD). The SIPOS layer plays a role in balancing charges in the device and improves the SOI The anti-single event effect ability of the device improves the anti-radiation performance of the SOI device. The SIPOS layer thickness is determined by the process used and design requirements. the

4. On the SIPOS layer 301 in FIG. 3, use LPVCD technology to obtain the thin SiO ₂ layer 401 in FIG. 4. The oxide layer acts to change the interface characteristics with the top polysilicon film.

5. Etching a through hole 501 connecting the SOI layer and the bulk silicon substrate as shown in FIG. 5 on the top oxide layer of the structure shown in FIG. 4 . The through hole plays the role of heat conduction and charge conduction, which improves the thermal conductivity of the SOI device to a certain extent, reduces the floating body effect caused by the accumulation of charges in the body region, and improves the anti-single event effect and thermal stability of the SOI device. resistance and total dose radiation resistance. the

6. On the basis of the structure in Fig. 5, a thin polysilicon layer (SOI layer) 601 as shown in Fig. 6 is formed on the insulating layer by selective epitaxial growth, and its thickness is determined according to actual design requirements. Then, the bulk silicon process is used to complete the processing and manufacturing of SOI devices on the SOI layer. the

Without departing from the essence and scope of the present utility model, some adjustments and optimizations can be made, and the protection scope of the present utility model shall be determined by the claims. the

Claims (2)

1. A radiation-resistant silicon-on-insulator structure, characterized in that: a polysilicon substrate is covered with a polysilicon oxide layer (201), the oxide layer is covered with a semi-insulating polysilicon layer (301), and the semi-insulating polysilicon layer is covered with There is a silicon dioxide layer (401), and the silicon dioxide layer is covered with a polysilicon layer (601). the 2. The radiation-hardened silicon-on-insulator structure according to claim 1, characterized in that there is a through hole (501) between the polysilicon substrate and the uppermost polysilicon layer of the structure. the

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