CN203012703U - A Nand Flash Block Redundant Storage Control Circuit for Embedded Systems - Google Patents

Abstract

The utility model discloses a redundant storage control circuit of NandFlash piece towards embedded system, including NandFlash memory chip (1), NandFlash memory chip (2) and control chip (3). The utility model has the advantages that: the interface driver of the NandFlash interface of the external main processor can realize the data redundant storage of the embedded main processor without additional overhead; two identical memory chips are adopted to form mutually redundant memory units to realize hardware-level redundant memory, and the influence of bad blocks of the NandFlash memory chip on data storage is effectively reduced. The utility model discloses it is applicable in the embedded system main memory unit that requires higher to data storage reliability.

Description

A Nand Flash Block Redundant Storage Control Circuit for Embedded Systems

technical field

The utility model belongs to the technical field of data storage, in particular to an embedded system-oriented Nand Flash block redundant storage control circuit.

Background technique

With the rapid development of semiconductor electronic technology and technology, Nand Flash memory chips have been widely used in the storage field of embedded systems due to their characteristics of high storage density, low power consumption, long life, and low cost. Typical embedded processors (such as Power PC, ARM, DSP, etc.) all support Nand Flash memory interface. Due to its inherent defects, the Nand Flash memory chip is a device with non-ideal data accuracy. A certain number of bad blocks will be generated during the delivery and use of the Nand Flash memory chip, resulting in errors or loss of stored data. Therefore, in order to improve the reliability of Nand Flash storage units and ensure the reliable operation of embedded systems, data redundancy storage based on Nand Flash is particularly necessary.

Currently, there are several methods for redundant storage of Flash:

(1) Redundant coding. The method is to use a certain coding method to generate redundant codes and store them in the reserved data redundancy space. When errors occur in the stored data, the redundant codes are used to correct the errors. Patent 200910053399 "A Multi-level Data Redundancy Method for Large-Scale Flash Storage Array" is to use redundant coding methods to redundant data at the page level, Flash chip level, and Flash chipset level. This method increases the amount of software calculation and the complexity of data storage control, and when there is a bad block and the data cannot be read, the redundant coding loses its meaning.

(2) Establish a data backup area. The method is to divide the data backup area inside the Flash storage unit, and read the data in the data backup area when a bad block occurs in the original data area. Patent 200810029685 "Secondary Backup Method of Flash Memory" is to use data backup for redundant storage. Since the original data area and the backup area are not equally redundant, this method increases the complexity of the storage control program during data storage and reduces the efficiency of data access.

(3) Hardware-level redundant storage. The method is to include two mutually redundant data storage areas on the hardware, and when a data block in one area fails, data can be recovered from the corresponding data block in the other area. Patent 201120005567 "A Data Redundancy Protection Flash Solid State Disk" includes two equal and mutually redundant storage arrays and data storage controllers to improve the reliability and integrity of data stored in the solid state disk, but the patent is limited to Applied to the design of Flash storage arrays and solid-state disks, it does not support the Nand Flash interface of embedded processors, and cannot be directly used in the design of the main memory unit of embedded systems.

Contents of the invention

The purpose of this utility model is to provide a kind of Nand Flash block redundant storage control circuit facing the embedded system for the deficiency of the existing redundant storage circuit based on Nand Flash, adopt the redundant storage method of hardware level to realize the redundant storage circuit based on Nand Flash It uses field programmable logic gate array FPGA (Field Programmable Gate Array) device as the control chip to realize the parallel operation of redundant storage units and provide a Nand Flash memory interface directly connected to the embedded processor, which can be applied to Embedded system main memory unit that requires high data storage reliability.

The utility model relates to an embedded system-oriented Nand Flash block redundant storage control circuit, comprising: a Nand Flash storage chip (1), a Nand Flash storage chip (2) and a control chip (3). The Nand Flash memory chip (1) and the Nand Flash memory chip (2) use the same memory chip to form two mutually redundant memory units. The IO pins 5 to 12, IO pin 17, IO pin 21, IO pin 22, IO pin 23, IO pin 24, IO pin 26, and IO pin 27 of the control chip (3) are respectively connected to Nand The pins I/O0 to I/O7, CLE, ALE, RE#, WE#, CE#, R/B#, WP# of the Flash memory chip (1) are connected, and the IO pin 78 of the control chip (3) is connected to 85. IO pin 92, IO pin 93, IO pin 94, IO pin 95, IO pin 97, IO pin 98, and IO pin 99 are respectively connected to the pin I/O of the Nand Flash memory chip (2). O0 to I/O7, CLE, ALE, RE#, WE#, CE#, R/B#, WP# are connected to control the IO pins 114 to 121, IO pin 126, and IO pin 127 of the chip (3) , IO pin 131, IO pin 132, IO pin 133, and IO pin 134 are respectively connected to the Nand Flash interface pins I/O0 to I/O7, CLE, ALE, RE#, WE#, CE#, R/B# are connected.

What described Nand Flash memory chip (1) and Nand Flash memory chip (2) adopted is the K9K8G08U0M of Samsung.

The FPGA chip used in the control chip (3) is Xilinx XC6SLX4TQG144. The control chip (3) realizes the Nand Flash block redundant storage control function, and uses the redundant mechanism to process the Nand Flash control command issued by the external main processor, and then performs corresponding processing on the Nand Flash memory chip (1) and the Nand Flash memory chip (2). operate.

The utility model applies the above-mentioned chip models, but is not limited to the above-mentioned models, and any chip models that can meet the same functional requirements can be substituted for each other.

Described external main processor refers to built-in Nand Flash controller and contains the embedded processor of Nand Flash memory interface.

The Nand Flash block redundant storage control method adopted in the utility model includes a power-on bad block self-inspection process, a data storage process, a data reading process and a data erasing process.

The power-on bad block self-test process includes the following steps:

S1 Nand Flash memory chip (1) and Nand Flash memory chip (2) are two mutually redundant storage units. Each Nand Flash memory chip contains n memory blocks (Block), respectively numbered from 0 to (n-1 );

After S2 is powered on, the control chip (3) scans the Nand Flash memory chip (1) and the Nand Flash memory chip (2) for bad blocks at the same time, and establishes a list of bad block information.

The data storage process consists of the following steps:

S1 control chip (3) receives data storage commands and data from the external main processor through the Nand Flash interface;

S2 control chip (3) extracts the block address number m of the currently operating storage block according to the row address in the command;

The S3 control chip (3) detects whether the mth storage block of the Nand Flash memory chip (1) and the Nand Flash memory chip (2) is a bad block according to the bad block information list, and only writes data into the mth block as a normal block In the memory chips of the two memory chips, if the mth blocks of the two memory chips are all bad blocks, the control chip (3) returns an unsuccessful write response to the external main processor.

The data reading process includes the following steps:

The S1 control chip (3) receives the data read command from the external main processor through the Nand Flash interface;

S2 control chip (3) extracts the block address number m of the currently operating storage block according to the row address in the command;

The S3 control chip (3) detects whether the mth storage block of the Nand Flash memory chip (1) and the Nand Flash memory chip (2) is a bad block according to the bad block information list, when the mth block of the Nand Flash memory chip (1) When it is a normal block, read the data of the Nand Flash memory chip (1) and return it to the external main processor, otherwise, read the data of the Nand Flash memory chip (2), if the mth blocks of both memory chips are bad blocks , read the default value of the page register and return to the external main processor;

S4 When the data is read successfully, judge whether the current page read is the mth block containing bad block information page (usually page 1) according to the row and column addresses in the command, if the data of the page containing bad block information is read Then update the bad block information of the mth block.

The data erasure process includes the following steps:

The S1 control chip (3) receives the data erasing command from the external main processor through the Nand Flash interface;

S2 control chip (3) extracts the block address number m of the currently operating storage block according to the row address in the command;

The S3 control chip (3) performs an erase operation on the Nand Flash memory chip (1) and the mth block of the Nand Flash memory chip (2) at the same time.

The beneficial effects produced by the utility model are: a kind of Nand Flash block redundant storage control circuit facing embedded system provided by the utility model can be directly connected with the Nand Flash memory interface of the external main processor, and the Nand Flash memory interface of the external main processor The Flash interface driver can realize the data redundancy storage of the embedded main processor without additional overhead; the control chip adopts the FPGA chip, which can realize the data parallel reading and writing and erasing operation of the redundant storage unit, which improves the Nand in the embedded system. The read and write speed of the Flash redundant storage unit; the hardware-level redundant storage method is used to effectively reduce the impact of bad blocks of the Nand Flash storage chip on data storage.

Description of drawings

Fig. 1 is a block diagram of the utility model;

Fig. 2 is the electrical schematic diagram of the utility model;

Fig. 3 is a block diagram of the internal structure of the control chip FPGA;

Fig. 4 is a flow chart of the self-inspection process of power-on bad blocks;

Fig. 5 is a flow chart of the data storage process;

Fig. 6 is a flow chart of the data reading process;

FIG. 7 is a flow chart of the data erasing process. the

Detailed ways

Below in conjunction with accompanying drawing, the utility model is described in further detail.

Accompanying drawing 1 is a structural block diagram of the present utility model, has described the connection relation between each component. The utility model comprises a control chip (3), a Nand Flash storage chip (1) and a Nand Flash storage chip (2) which are mutually redundant storage units.

The control chip (3) is respectively connected with the Nand Flash storage chip (1) and the Nand Flash storage chip (2), and the control chip (3) is also connected with the Nand Flash interface of the external main processor.

Accompanying drawing 2 is the electrical schematic diagram of the utility model.

Accompanying drawing 2 shows Nand Flash storage chip, control chip and other configuration chips.

The Nand Flash memory chip (1) uses Samsung’s K9K8G08U0M (U1), and the Nand Flash memory chip (2) also uses Samsung’s K9K8G08U0M (U2).

The FPGA chip adopted by the control chip (3) is XC6SLX4TQG144 (U3) of Xilinx Company.

The IO pins 5 to 12, IO pin 17, IO pin 21, IO pin 22, IO pin 23, IO pin 24, IO pin 26, and IO pin 27 of the control chip (3) are respectively connected to Nand The pins I/O0 to I/O7, CLE, ALE, RE#, WE#, CE#, R/B#, WP# of the Flash memory chip (1) are connected, and the IO pin 78 of the control chip (3) is connected to 85. IO pin 92, IO pin 93, IO pin 94, IO pin 95, IO pin 97, IO pin 98, and IO pin 99 are respectively connected to the pin I/O of the Nand Flash memory chip (2). O0 to I/O7, CLE, ALE, RE#, WE#, CE#, R/B#, WP# are connected to control the IO pins 114 to 121, IO pin 126, and IO pin 127 of the chip (3) , IO pin 131, IO pin 132, IO pin 133, and IO pin 134 are respectively connected to the Nand Flash interface pins I/O0 to I/O7, CLE, ALE, RE#, WE#, CE#, R/B# are connected.

Accompanying drawing 3 is a block diagram of the internal structure of the control chip FPGA.

Control chip (3) FPGA internal structure block diagram includes external main processor Nand Flash interface control sub-module, command decoding and block address extraction module, writing Nand Flash sub-module, reading Nand Flash sub-module, erasing Nand Flash sub-module , memory chip selection sub-module, power-on bad block self-test sub-module, bad block information list, memory chip 1Nand Flash interface control sub-module, memory chip 2Nand Flash interface control sub-module and digital frequency manager module.

The control chip (3) first receives instructions from the external main processor through the Nand Flash interface, selects the current operating sub-module of the Nand Flash through command decoding, selects the current operating memory chip through block address extraction and combined with bad block information, and finally passes the memory chip The Nand Flash interface control sub-module performs the current operation on the selected Nand Flash memory chip.

Accompanying drawing 4 is the flow chart of power-on bad block self-inspection process. The power-on bad block self-test process includes the following steps:

S1 Nand Flash memory chip (1) and Nand Flash memory chip (2) are both K9K8G08U0M, each Nand Flash memory chip contains 8192 memory blocks (Block), respectively numbered 0 to 8191;

After S2 is powered on, the control chip (3) scans the bad blocks of the Nand Flash memory chip (1) and the Nand Flash memory chip (2) at the same time, and establishes a list of bad block information.

The method for judging the bad block information of the Nand Flash memory chip is: judge whether the data of the 2048th byte of the first page of each block is FFh, if not FFh, the block is a bad block.

The bad block information is the logical AND result of the bad block information of the Nand Flash memory chip (1) and the bad block information of the Nand Flash memory chip (2). If and only when the current blocks of both memory chips are bad blocks, the current block is a bad block.

Accompanying drawing 5 is the flow chart of data storage process. The data storage process consists of the following steps:

S1 control chip (3) receives data storage commands and data from the external main processor through the Nand Flash interface;

S2 control chip (3) extracts the block address number m of the currently operating storage block according to the row address in the command;

The S3 control chip (3) detects whether the mth storage block of the Nand Flash memory chip (1) and the Nand Flash memory chip (2) is a bad block according to the bad block information list;

When the mth block of the two memory chips is normal, the data is stored in the Nand Flash memory chip (1) and the Nand Flash memory chip (2) at the same time; when the mth block of the Nand Flash memory chip (1) is bad block, the data is only stored in the Nand Flash memory chip (2); when the mth block of the Nand Flash memory chip (2) is a bad block, the data is only stored in the Nand Flash memory chip (1); when the Nand When the mth block of the Flash memory chip (1) and the Nand Flash memory chip (2) are all bad blocks, an unsuccessful write response is returned to the external main processor.

Accompanying drawing 6 is a flow chart of the data reading process. The data reading process includes the following steps:

The S1 control chip (3) receives the data read command from the external main processor through the Nand Flash interface;

S2 control chip (3) extracts the block address number m of the currently operating storage block according to the row address in the command;

The S3 control chip (3) detects whether the mth storage block of the Nand Flash memory chip (1) and the Nand Flash memory chip (2) is a bad block according to the bad block information list, when the mth block of the Nand Flash memory chip (1) When it is a normal block, read the data of the Nand Flash memory chip (1) and return it to the external main processor, otherwise, read the data of the Nand Flash memory chip (2), if the mth blocks of both memory chips are bad blocks , read the default value of the page register and return to the external main processor;

S4 When the data is read successfully, judge whether the current page read is the first page of the mth block according to the row and column addresses in the command. If the read is the first page, update the first page according to whether the data of the 2048th byte is FFh Bad block information of block m.

Accompanying drawing 7 is the flow chart of data erasing process. The data erasure process includes the following steps:

The S1 control chip (3) receives the data erasing command from the external main processor through the Nand Flash interface;

S2 control chip (3) extracts the block address number m of the currently operating storage block according to the row address in the command;

The S3 control chip (3) performs an erase operation on the Nand Flash memory chip (1) and the mth block of the Nand Flash memory chip (2) at the same time.

Claims (1)

1. A Nand Flash block redundant storage control circuit for embedded systems, characterized in that: comprise Nand Flash memory chip (1), Nand Flash memory chip (2) and control chip (3); Nand Flash memory chip ( 1) Use the same memory chip as the Nand Flash memory chip (2) to form two mutually redundant storage units; control the IO pins 5 to 12, IO pin 17, IO pin 21, and IO pins of the control chip (3). Pin 22, IO pin 23, IO pin 24, IO pin 26, and IO pin 27 are respectively connected to pins I/O0 to I/O7, CLE, ALE, RE#, WE#, CE#, R/B#, WP# are connected, and the IO pins 78 to 85, IO pin 92, IO pin 93, IO pin 94, IO pin 95, and IO pins of the control chip (3) Pin 97, IO pin 98, and IO pin 99 are respectively connected to pins I/O0 to I/O7, CLE, ALE, RE#, WE#, CE#, R/B#, WP of the Nand Flash memory chip (2) # is connected, the IO pins 114 to 121, IO pin 126, IO pin 127, IO pin 131, IO pin 132, IO pin 133, IO pin 134 of the control chip (3) are connected with the external main The processor's Nand Flash interface pins I/O0 to I/O7, CLE, ALE, RE#, WE#, CE#, R/B# are connected.

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