CN202818272U - Rubidium clock frequency conversion circuit without frequency synthesizer - Google Patents

Abstract

The rubidium clock frequency conversion circuit of the utility model frequencyless synthesizer is mainly composed of a non-integer voltage-controlled crystal oscillator, a frequency division and DDS synthesis circuit designed by CPLD, a phase modulation circuit, a servo amplifier circuit, a synchronous phase detection circuit, and a 1PPS signal processor. Composition, wherein: the output of the non-integer voltage-controlled crystal oscillator generates a 144Hz triangular wave signal through a frequency division and synthesis circuit, and the signal modulates the phase of the voltage-controlled crystal oscillator;

doubler and

Microwave frequency multiplication, and the microwave signal generated by the stimulated transition of rubidium atoms is processed by the physical system for quantum frequency discrimination; then it is converted into an error electrical signal by a photoelectric cell, and the deviation correction voltage is obtained through a 144Hz synchronous phase discrimination and a low-pass filter to control the non-integer voltage. Control the crystal oscillator to lock state. The utility model has the advantages of simple structure and convenient debugging, which is beneficial to improving the integration degree and miniaturization of the rubidium atomic frequency standard, and has good application prospect.

Description

Rubidium clock frequency conversion circuit without frequency synthesizer

technical field

The utility model relates to the technical field of atomic frequency standards, in particular to an improved rubidium clock frequency conversion circuit without a frequency synthesizer, which is suitable for making miniaturized rubidium atomic frequency standards. the

Background technique

The rubidium atomic frequency standard has the advantages of small size, power consumption, strong environmental adaptability, high frequency stability and low drift rate. Although the frequency stability and drift rate indicators are not as good as the cesium and hydrogen atomic frequency standards, it has the characteristics of simple structure and low cost, and is still the most widely used atomic frequency standard. Its development trend is high performance and miniaturization. In the rubidium atomic frequency standard, the physical system provides an atomic resonance absorption line with stable frequency and narrow linewidth. The ultra-fine energy level transition frequency signal has extremely high frequency accuracy, but its output is a non-integer microwave frequency, and the output power is extremely small, so it is not practical. the

。由于采用频率综合器在微波腔中混频的方式，使频率变换电路的复杂程度增加。同时腔内存在5.3125MHz及其谐波的旁频分量，使杂散增加并影响了原子频标的性能指标。  The traditional rubidium clock frequency conversion servo circuit system converts the output frequency of the 10MHz voltage-controlled crystal oscillator to 90MHz, and then superimposes with the 5.3125MHz fractional frequency signal generated by the frequency synthesizer and sends it to the microwave cavity for 76 step frequency multiplication and Simultaneous mixing to obtain a microwave frequency signal determined by the transition of the rubidium atom:

. Due to the use of frequency synthesizer to mix frequency in the microwave cavity, the complexity of the frequency conversion circuit is increased. At the same time, there are side frequency components of 5.3125MHz and its harmonics in the cavity, which increases the stray and affects the performance index of the atomic frequency standard.

Contents of the invention

The technical problem to be solved by the utility model is: to provide an improved rubidium clock frequency conversion circuit without a frequency synthesizer, without using a frequency synthesizer, to realize the transfer of the stability of the atomic frequency standard, which will be inconvenient for practical use The rubidium atomic microwave frequency signal is converted into a standard integer and power practical high-stable frequency standard signal output. the

MHz非整数压控晶体振荡器、

倍频电路、复杂可编程器件(CPLD)设计的分频与合成电路、DDS三角波合成电路、调相电路、伺服放大器、同步鉴相电路、1PPS信号处理器组成。其中：非整数压控晶体振荡器的输出经分频与合成电路产生144Hz三角波信号，该信号对非整数压控晶振的输出进行调相；再经

倍频器和微波倍频至6.8346875GHz，与铷原子受激跃迁产生的微波信号对物理系统进行鉴频；然后由光电池转换为误差电信号，通过144Hz同步鉴相和低通滤波器获得纠偏电压，控制非整数压控晶体振荡器至锁定状态。  The technical solution that the utility model solves its technical problem adopts is: mainly by

MHz non-integer voltage controlled crystal oscillator,

It is composed of frequency multiplication circuit, frequency division and synthesis circuit designed by complex programmable device (CPLD), DDS triangular wave synthesis circuit, phase modulation circuit, servo amplifier, synchronous phase detection circuit, and 1PPS signal processor. Among them: the output of the non-integer voltage-controlled crystal oscillator generates a 144Hz triangular wave signal through the frequency division and synthesis circuit, and the signal modulates the phase of the output of the non-integer voltage-controlled crystal oscillator;

doubler and The microwave frequency is multiplied to 6.8346875GHz, and the microwave signal generated by the stimulated transition of rubidium atoms is used to discriminate the physical system; then it is converted into an error electrical signal by a photocell, and the deviation correction voltage is obtained through a 144Hz synchronous phase discrimination and a low-pass filter to control the non-integer VCO to lock.

said The MHz non-integer voltage-controlled crystal oscillator directly obtains the microwave excitation signal through the frequency multiplication chain, which is processed by the physical system for frequency discrimination, without frequency adjustment by the frequency synthesizer.

The frequency division factor of the frequency divider designed by CPLD is 131072, and the output synchronous pulse is 144Hz. 144Hz triangular wave signal is synthesized, and the signal output by the non-integer voltage-controlled crystal oscillator is indirectly frequency-modulated. The synthesis circuit designed by the CPLD is a dual-channel direct digital frequency synthesizer designed by the CPLD, which consists of a frequency control word register, a phase accumulator, a sine It consists of a waveform lookup table, a digital-to-analog converter, etc., one of which is a fixed 10MHz frequency output, and the other can be set for an applicable frequency output. the

The 1PPS processing circuit generates 1PPS signal output, or is controlled by 1PPS signal input, so that the non-integer voltage-controlled crystal oscillator is synchronized with the standard 1PPS signal. the

Compared with the traditional rubidium atomic frequency standard frequency conversion circuit, the technical scheme adopted by the utility model to solve its technical problems has the following main advantages:

1. It has continuously adjustable frequency resolution. Because the correction voltage directly voltage-controls the non-integer crystal oscillator, it can obtain continuously variable mantissa output frequency. After frequency multiplication by the frequency multiplier chain, theoretically the resolution of the output frequency can be infinitely narrow.

MHz的单一频率，而无频率综合器分量。有效减小了相位噪声和杂散分量，也有效降低了杂散分量对频标的影响。  2. The microwave signal spectrum of rubidium frequency standard microwave cavity has high purity. After being multiplied by the RF frequency multiplier, the signal input to the step diode microwave cavity is

A single frequency in MHz without frequency synthesizer components. It effectively reduces the phase noise and spurious components, and also effectively reduces the influence of spurious components on the frequency standard.

3. The hardware circuit is simplified, and it is easy to miniaturize the rubidium atomic frequency standard. Because all digital circuits, including frequency division circuit and triangular wave synthesis circuit, direct digital frequency synthesizer and 1PPS processing circuit, are designed with CPLD, and the frequency synthesizer and addition and mixing unit in the frequency conversion circuit are omitted, optimizing and simplifying The hardware circuit structure. the

4. The applicable output frequency of rubidium atomic frequency standard is easy to obtain, because the dual DDS technology designed by the complex programmable device CPLD is adopted, and one of the two outputs is a fixed 10MHz frequency. The output frequency of the other DDS can be set within the applicable frequency range to obtain the output frequency. the

In a word, the utility model has the advantages of system optimization, simple circuit structure, small volume, low power consumption and convenient debugging, etc. It is beneficial to improve the integration and miniaturization of the rubidium atomic frequency standard, and has a good application prospect. the

Description of drawings

Fig. 1 is the structural block diagram of the rubidium clock frequency conversion circuit of the utility model frequencyless synthesizer. the

FIG. 2 is a structural block diagram of the servo control circuit in FIG. 1 . the

Fig. 3 is the functional block diagram of the digital-to-analog conversion diagram for DDS or triangular wave of the present invention. the

Fig. 4 is the functional block diagram of the digital system designed by CPLD in Fig. 3. the

Detailed ways

Below in conjunction with embodiment and accompanying drawing, the utility model is further described. the

MHz，物理系统获取的纠偏信息所得到的误差信号去伺服非整数压控晶振，能有效补偿因各种因素系统所产生的总频率偏移，实现整机的闭环锁定。省除了控制环路中的频率综合器及倍频器与频率综合器的相加混频单元，杜绝了频综器相位噪声与杂散的影响。  The utility model discloses an improved frequency conversion circuit of a rubidium clock of a frequencyless synthesizer, the resonant frequency of the non-integer voltage-controlled crystal oscillator adopted is

MHz, the error signal obtained from the deviation correction information obtained by the physical system is used to serve the non-integer voltage-controlled crystal oscillator, which can effectively compensate the total frequency offset generated by the system due to various factors, and realize the closed-loop locking of the whole machine. The frequency synthesizer in the control loop and the addition and mixing unit of the frequency multiplier and the frequency synthesizer are omitted, and the influence of the phase noise and spurs of the frequency synthesizer is eliminated.

The utility model will be further described below in conjunction with the embodiments and accompanying drawings, but it is not limited to the structure and implementation details described below or shown in the drawings. the

倍频及微波倍频后，得到6.8346875GHz的己调制的微波信号，物理系统的

原子基态超精细跃迁频率信号对非整数压控晶振倍频后的微波激励信号鉴频，若微波信号频率大于谱线中心频率，经鉴相后产生负的纠偏电压，使压控晶振的频率降低；反之若激励信号频率小于谱线中心频率，经鉴相后产生正的纠偏电压，使压控晶振的频率上升；若激励信号频率等于谱线中心频率，则输出为调制频率的两倍的信号，经鉴相后不产生纠偏电压，此时非整数压控晶振的频率不变，实现对非整数压控晶振的锁定，再通过DDS输出稳定的铷原子频标信号。  The rubidium clock frequency conversion circuit of the frequencyless synthesizer provided by the utility model is shown in Fig. 1 and Fig. 2 . Because the physical system can be equivalent to a frequency discriminator, in the frequency conversion circuit The output signal of MHz non-integer voltage-controlled crystal oscillator is indirectly FM,

After frequency doubling and microwave frequency doubling, a modulated microwave signal of 6.8346875 GHz is obtained. The physical system

The atomic ground state ultra-fine transition frequency signal is used to discriminate the frequency of the microwave excitation signal after the frequency multiplication of the non-integer voltage-controlled crystal oscillator. If the frequency of the microwave signal is greater than the center frequency of the spectral line, a negative deviation correction voltage will be generated after phase discrimination to reduce the frequency of the voltage-controlled crystal oscillator. ; Conversely, if the frequency of the excitation signal is less than the center frequency of the spectrum line, a positive correction voltage will be generated after phase discrimination to increase the frequency of the voltage-controlled crystal oscillator; if the frequency of the excitation signal is equal to the center frequency of the spectrum line, the output signal will be twice the modulation frequency , no deviation correction voltage is generated after phase detection, and the frequency of the non-integer voltage-controlled crystal oscillator remains unchanged at this time, so as to realize the locking of the non-integer voltage-controlled crystal oscillator, and then output a stable rubidium atomic frequency standard signal through DDS.

Because the voltage-controlled crystal oscillator has a certain voltage control range, the correction voltage can completely make the frequency of the microwave signal within the range of the atomic absorption line width, so that the reliable closed-loop locking of the whole machine can be realized. the

(148322Hz)、除

(144Hz)分频器与包括D/A的三角波合成电路、调相电路、倍频器及微波倍频、伺服放大器、144Hz同步鉴相器与低通滤波器、288Hz锁定检测与指示组成，其中：作为铷原子频标系统的初始信号源的非整数压控晶体振荡器的输出经除

、除产生288Hz 和

分频器产生144Hz的方波信号，分别作为144Hz同步鉴相脉冲和288Hz锁定检测与指示脉冲信号。除分频器经D/A变换形成三角波信号后，再由调相电路对压控晶振输出

MHz的信号进行调相，实际上是间接调频。已调制后的信号经

倍频器得到

MHz的射频信号，再经

微波倍频至6.8346875GHz，它由原子受激跃迁产生的高稳6.8346875GHz的微波信号鉴频。鉴频光误差信号由光电池转换为误差电信号，经伺服号放大器放大后，再由144Hz同步鉴相器、低通滤波器获得纠偏电压，控制非整数压控晶体振荡器至锁定状态，并由288Hz的方波信号控制锁定指示电路给出锁定指示信号。  The rubidium clock servo control circuit of the frequency-free synthesizer provided by the utility model has a specific structure as shown in Figure 2, mainly composed of a non-integer voltage-controlled crystal oscillator, a divider

(148322Hz), except

(144Hz) frequency divider and triangular wave synthesis circuit including D/A, phase modulation circuit, Composed of frequency multiplier and microwave frequency multiplier, servo amplifier, 144Hz synchronous phase detector and low-pass filter, 288Hz lock detection and indication, among which: the non-integer voltage-controlled crystal oscillator as the initial signal source of the rubidium atomic frequency standard system Output divided by

,remove produces 288Hz and

The frequency divider generates a 144Hz square wave signal, which is used as a 144Hz synchronous phase detection pulse and a 288Hz lock detection and indication pulse signal respectively. remove The frequency divider forms a triangular wave signal through D/A conversion, and then the voltage-controlled crystal oscillator is output by the phase modulation circuit.

The phase modulation of the MHz signal is actually indirect frequency modulation. The modulated signal has been

The doubler gets

MHz RF signal, and then

The microwave frequency is multiplied to 6.8346875GHz, and it is discriminated by the high-stable 6.8346875GHz microwave signal generated by the stimulated transition of atoms. The optical error signal of frequency discrimination is converted into an error electrical signal by a photocell, and after being amplified by a servo signal amplifier, the deviation correction voltage is obtained by a 144Hz synchronous phase detector and a low-pass filter, and the non-integer voltage-controlled crystal oscillator is controlled to a locked state, and is controlled by The 288Hz square wave signal controls the lock indication circuit to give a lock indication signal.

MHz输出经除

、除得到144Hz和288Hz的矩形脉冲信号，

中

输出给由CPLD及外加电阻阵列构成的D/A，由它合成三角波，数模转换图原理框图如图3所示。而同步相位捡测中的开关鉴相电路选用高精度通断接近理想状态的高速模拟开关(如MAX392等)。  The error signal preamplifier selects a high-precision low-drift integrated operational amplifier (such as AD8628, etc.), a low-noise field effect transistor, etc., and the non-integer voltage-controlled crystal oscillator in Figure 1 and Figure 2

MHz output divided by

,remove Obtain rectangular pulse signals of 144Hz and 288Hz,

middle

It is output to the D/A composed of CPLD and external resistance array, and it synthesizes triangular wave. The principle block diagram of the digital-analog conversion diagram is shown in Figure 3. The switch phase detection circuit in the synchronous phase detection selects a high-speed analog switch (such as MAX392, etc.) with high-precision on-off close to the ideal state.

由可逆计数器构成，

中输出送给由CPLD构成的并行高速数据缓冲寄存器，将计数脉冲变換成三角阶梯波频率信号输出。  As shown in Figure 3, the structure diagram of a 10-bit DAC conversion circuit designed by CPLD is given. The CPLD design includes 10 parallel high-speed data buffer registers and bit switching switches. The external high-precision reference voltage source and low-error R-2R resistor network are controlled by a bit switch, and its output is buffered and amplified by a high-speed, low-noise, rail-to-rail output operational amplifier (such as ADA4897-1) and then output, and the sinusoidal The frequency data of the waveform lookup table is transformed into a sinusoidal step frequency signal for output. When used as a triangular wave synthesis circuit, except

Consists of a reversible counter,

middle The output is sent to the parallel high-speed data buffer register composed of CPLD, and the counting pulse is converted into a triangular ladder wave frequency signal for output.

、除

、三角波数模转换、1PPS处理电路等，非整数压控晶体振荡器的输出信号经

倍频器得到

MHz的射频信号，作为高精度参考源输出给DDS，再由DDS合成标准铷频标信号输出，CPLD可以是ALTERA公司的MAXⅡ系列或XILINX等其它公司。  The utility model adopts CPLD to design a direct digital frequency synthesizer (DDS). In order to conveniently select the applicable frequency, a double DDS direct digital synthesis technology is adopted, which can convert the output frequency of the non-integer voltage-controlled crystal oscillator locked by the system into a high-precision rubidium atom. Frequency standard signal. Figure 4 is a block diagram of the digital system designed by CPLD in the frequency conversion circuit, which includes dual DDS, divider

,remove

, triangular wave digital-to-analog conversion, 1PPS processing circuit, etc., the output signal of the non-integer voltage-controlled crystal oscillator is passed

The doubler gets

The MHz radio frequency signal is output to DDS as a high-precision reference source, and then the DDS synthesizes a standard rubidium frequency standard signal for output. The CPLD can be MAXⅡ series of ALTERA company or XILINX and other companies.

As shown in Figure 4, the direct digital synthesizer (DDS) designed by CPLD includes frequency control word register, phase accumulator, sinusoidal waveform look-up table, digital-to-analog conversion and filter circuit and other parts. The frequency control word register, phase accumulator, sine waveform lookup table, and digital-to-analog conversion part are designed by CPLD, especially the digital-to-analog converter designed by CPLD has the characteristics of fast response, low power consumption and low cost. The designed data register stores the frequency control data (frequency control word), and has serial/parallel data input function, and the serial and parallel input comes from the controller or microcomputer. This technology transforms the output frequency of the non-integer voltage-controlled quartz crystal oscillator locked by the servo system into two outputs. The frequency control data is input to the phase accumulator in parallel, and the number of bits of the phase accumulator can be selected according to the resolution required by the frequency synthesizer. the

，能很好满足铷频标输出频率准确度的要求，输出10MHz所对应的的频率控制字为

，转换为二进制为  The known clock is MHz, if a 44-bit phase accumulator is selected, the lowest output frequency (frequency resolution) can be obtained as

, which can well meet the requirements of rubidium frequency standard output frequency accuracy, the frequency control word corresponding to output 10MHz is

, converted to binary as

 

The 10MHz output can be processed by narrowband filtering to eliminate out-of-band noise and spurs. The output frequency of any applicable DDS can be set and selected, and the output is filtered by a low-pass filter.

、除

分频器、D/A中的并行高速数据缓冲寄存器、高速切换开关、1PPS处理电路也均由CPLD设计。  Except that DDS is designed by Complex Programmable Devices (CPLD), except in Figure 4

,remove

The frequency divider, the parallel high-speed data buffer register in D/A, the high-speed switching switch, and the 1PPS processing circuit are also designed by CPLD.

The complex programmable device (CPLD) in the utility model adopts as MAX2 series CPLD of ALTERA company, or the CPLD of Xilinx company, can also select FPGA for use. The complex programmable device (CPLD) has better flexibility. the

The above-mentioned improved rubidium clock frequency conversion circuit of a frequency-free synthesizer provided by the utility model is used for making miniaturized rubidium atomic frequency standards. the

The above is only a preferred embodiment of the present utility model, and is not intended to limit the structure of the present utility model in any form. Any simple modification or equivalent change made to the above embodiments according to the technical essence of the present utility model is acceptable. Still belong to the scope of the technical solution of the utility model. the

Claims (5)

1. rubidium clock frequency-conversion circuit without Frequency Synthesizer, it is characterized in that mainly by the non-integer VCXO,

The frequency division of frequency multiplier circuit, CPLD design and combiner circuit, phase modulation circuit, servo amplifier, synchronous phase discriminator, 1PPS signal processor form, wherein: the output of non-integer VCXO produces the 144Hz triangular signal through frequency division and combiner circuit, and this signal carries out phase modulation to the output of non-integer VCXO; Warp again

Frequency multiplier and

Microwave multiple-frequency carries out frequency discrimination with the microwave signal that the transition of rubidium atom-exciting produces to physical system to 6.8346875GHz; Then be converted to the error signal of telecommunication by photocell, obtain correction voltage by the synchronous phase demodulation of 144Hz and low pass filter, control non-integer VCXO is to lock-out state.

2. the rubidium clock frequency-conversion circuit without Frequency Synthesizer according to claim 1 is characterized in that the non-integer VCXO adopts

MHz non-integer VCXO, the microwave excitation signal that its output obtains through frequency multiplier chain is done to lock this VCXO after frequency discrimination is processed by physical system, need not frequency synthesizer and carries out the frequency adjustment.

3. the rubidium clock frequency-conversion circuit without Frequency Synthesizer according to claim 2 is characterized in that: described

The output of MHz signal produces the 144Hz triangular signal through frequency division and the DDS combiner circuit of CPLD design, and this signal carries out phase modulation to the output of non-integer VCXO, is equivalent to indirect frequency modulation; Warp again

After the frequency multiplication, obtain

MHz delivers to microwave snap-off diode frequency multiplier circuit.

4. the rubidium clock frequency-conversion circuit without Frequency Synthesizer according to claim 1, it is characterized in that: the combiner circuit of described CPLD design is the two-way Direct Digital Frequency Synthesizers of CPLD design, formed by FREQUENCY CONTROL word register, phase accumulator, sinusoidal waveform question blank, digital to analog converter, it is two-way output that this synthesizer is Shuaied Bian Change with the Pin of the voltage-controlled quartz oscillator of non-integer output, and one the tunnel is fixing 10MHz frequency; Another road obtains applicable output frequency by arranging.

5. the rubidium clock frequency-conversion circuit without Frequency Synthesizer according to claim 1, it is characterized in that: described 1PPS signal processor is designed by CPLD, and this processor produces the output of 1PPS signal or is subjected to 1PPS signal input control.

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