CN202816958U - Thin film transistor TFT array substrate and display device - Google Patents

Abstract

The utility model discloses a TFT array substrate and a display device. On the basis of the existing TFT structure, a second grid located above the semiconductor layer is added on the passivation layer of the TFT. When the TFT is working, the newly added second gate After the second gate is energized, a current channel will be formed in the semiconductor layer below it, and after the original first gate of the TFT is energized, a current channel will also be formed in the semiconductor layer, that is, two channels will be formed in the semiconductor layer. In this way, on the premise of not increasing the gate scan signal strength of the gate line, the overall conduction current of the TFT semiconductor layer is improved; and, since the newly added second gate is arranged above the semiconductor layer, it will not The size of the pixel unit occupied by the entire TFT structure is increased, so the aperture ratio of the pixel unit will not be reduced.

Description

Thin film transistor TFT array substrate and display device

technical field

The utility model relates to the field of display technology, in particular to a thin film transistor TFT array substrate and a display device.

Background technique

At present, with the development of liquid crystal display technology, the requirements for the conduction current of the TFT switches in the liquid crystal panel are getting higher and higher. As shown in Figure 1 and Figure 2, in the existing liquid crystal panel, the TFT of the TFT array substrate is composed of a gate 1, a semiconductor layer 3, a source 4 and a drain 5 arranged on the substrate in sequence, wherein the gate The electrode 1 is electrically connected to the gate line 8, the gate 1 is isolated from the semiconductor layer 3 through the gate insulating layer 2, the source 4 is electrically connected to the data line 9, and the drain 5 is connected to the pixel electrode through the via hole on the passivation layer 6. 7 are electrically connected, and the source 4 and the drain 5 face each other to form a channel structure.

Its working principle is: when the gate line 8 is loaded with a gate scanning signal, the gate 1 electrically connected to it is energized, so that the semiconductor 3 above the gate will change from a semiconductor state to a conductor state, and the charge of the semiconductor 3 will be insulated along the gate. The surface of the layer moves, as shown in Figure 3a, that is, a current channel a is formed on the surface of the gate insulating layer 2 in the semiconductor layer 3. The amount of current that can pass through the current channel a is called the conduction current (Ion). a The electrical signal loaded by the data line 9 to the source 4 flows to the pixel electrode 7 through the drain 5, so that the pixel unit is in an on state. When the gate line 8 is not loaded with a gate scanning signal, as shown in FIG. 3b, there is no current channel a in the semiconductor layer 3, and the electrical signal loaded by the data line 9 to the source 4 cannot flow to the pixel electrode 7 through the source 4. Turns the pixel cell off.

It can be seen from the working principle of the above TFT that the greater the gate scan signal loaded by the gate line 8 on the gate 1, the greater the conduction current of the current channel a formed in the semiconductor layer 3, and the greater the current flow of the current channel a formed on the semiconductor layer 3, the greater the current load of the data line 9 The signal can well control the pixel electrode 7 to realize high picture quality of display. However, in actual operation, due to the restriction of the power consumption of the display panel, the voltage of the gate scan signal applied to the gate 1 cannot be too high. Then, in order to increase the conduction current of the current channel a formed by the semiconductor layer 3, it is necessary to adopt a method of changing the TFT structure to expand the overall area, which will inevitably lead to the problem of decreasing the aperture ratio of the pixel unit.

Therefore, how to increase the conduction current of the TFT semiconductor layer as much as possible while ensuring the aperture ratio of the pixel unit is a technical problem to be solved urgently by those skilled in the art.

Utility model content

The embodiment of the utility model provides a TFT array substrate and a display device, which are used to increase the conduction current of the TFT semiconductor layer as much as possible while ensuring the aperture ratio of the pixel unit.

A thin film transistor TFT array substrate provided by an embodiment of the present invention includes: a first gate, a gate insulating layer, a semiconductor layer, a source electrode, a drain electrode and a passivation layer arranged on the substrate in sequence, and also includes: A second gate on the passivation layer and on the semiconductor layer.

A display device provided by an embodiment of the present invention includes the TFT array substrate provided by an embodiment of the present invention.

The beneficial effects of the utility model embodiment include:

A TFT array substrate and a display device provided by the embodiments of the present invention, on the basis of the existing TFT structure, a second grid located above the semiconductor layer is added on the passivation layer of the TFT, and when the TFT is working, a new grid is added After the second gate of the TFT is energized, a current channel will be formed in the semiconductor layer below it, and a current channel will be formed in the semiconductor layer after the original first gate of the TFT is energized, that is, a current channel will be formed in the semiconductor layer. Two current channels, thus, without increasing the gate scan signal strength of the gate line, the overall conduction current of the TFT semiconductor layer is improved; and, since the newly added second gate is arranged above the semiconductor layer, The size of the pixel unit occupied by the entire TFT structure will not be increased, so the aperture ratio of the pixel unit will not be reduced.

Description of drawings

1 is a top view of a TFT array substrate in the prior art;

Fig. 2 is the sectional view of A-A in Fig. 1;

Figure 3a and Figure 3b are working principle diagrams of TFT;

FIG. 4 is a top view of a TFT array substrate provided by an embodiment of the present invention;

Fig. 5 is the sectional view of A-A among Fig. 4;

Figure 6a and Figure 6b are working principle diagrams of the TFT array substrate provided by the embodiment of the present invention;

Fig. 7 is the sectional view of B-B in Fig. 4;

FIG. 8 is a flowchart of a method for preparing a TFT array substrate provided by an embodiment of the present invention.

Detailed ways

The specific implementation manners of the TFT array substrate and the display device provided by the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

The size and shape of each layer of films and regions in the drawings do not reflect the real proportion of the array substrate, but are only intended to schematically illustrate the content of the present invention.

A thin film transistor TFT array substrate provided by an embodiment of the present invention, as shown in Figure 4 and Figure 5, includes: a first gate 1, a gate insulating layer 2, a semiconductor layer 3, a source 4. The drain 5 and the passivation layer 6 further include: a second gate 10 disposed on the passivation layer 6 and above the semiconductor layer 3 .

In specific implementation, the semiconductor layer 3 can be prepared using a-Si or metal oxide materials. When the metal oxide is selected to prepare the semiconductor layer, since the contact resistance of the metal oxide is small, the ohmic contact layer is generally no longer used to reduce the contact resistance. Contact resistance; when selecting a-Si to prepare the semiconductor layer, an ohmic contact layer needs to be set between the semiconductor layer and the source and drain electrodes.

The TFT array substrate provided by the embodiment of the present invention is based on the existing TFT structure, and the second gate 10 located above the semiconductor layer 3 is added on the passivation layer 6 of the TFT. When the TFT is working, as shown in Figure 6a As shown, after the newly added second gate 10 is energized, a current channel b will be formed in the semiconductor layer 3 below it, and a current channel b will be formed in the semiconductor layer 3 after the original first gate 1 of the TFT is energized. The current channel a, that is, two current channels a and b are formed in the semiconductor layer. After these two current channels are superimposed, the overall TFT semiconductor layer 3 can be improved without increasing the gate scan signal strength of the gate line 1. and, since the newly added second gate 10 is disposed above the semiconductor layer 3, the size of the pixel unit occupied by the entire TFT structure will not be increased, and therefore the aperture ratio of the pixel unit will not be reduced. Figure 6b is a schematic diagram when the TFT is turned off.

Specifically, in the above-mentioned TFT array substrate provided by the embodiment of the present utility model, it is necessary to simultaneously apply a voltage signal to the first gate 1 and the second gate 10 to turn on the TFT switch, so as to increase the current conduction in the semiconductor layer 3. Therefore, the second gate line 10 and the first gate line 1 should be guaranteed to be electrically connected to the same gate line 8. Specifically, since the second gate line 10 is arranged on the passivation layer 6, as As shown in FIG. 7 , the second gate 10 is generally electrically connected to the corresponding gate line 8 through a via hole. Specifically, the via hole penetrating the passivation layer 6 and the gate insulating layer 2 is formed when forming the pattern of the passivation layer 6 .

Furthermore, since the newly added second gate 10 is located above the semiconductor layer 3, that is, the newly added second gate 10 will not occupy the opening area of the existing pixel unit, therefore, the newly added second gate 10 It can be prepared using, for example, the same metal material as the first gate 1 , or can be prepared using, for example, the same transparent conductive material as the pixel electrode, which is not limited here.

Further, the newly added second gate 10 in the above TFT structure can be arranged on the same layer as the pixel electrode 7 of the TFT array substrate on the passivation layer 6, so that the second gate 10 and the second gate can be formed by one patterning process. The pattern of the pixel electrode 7 will not increase the preparation process steps of the existing TFT array substrate, only need to change the existing mask plate pattern for preparing the passivation layer and the pixel electrode, and the above-mentioned TFT provided by the implementation of the utility model can be realized. structure, the manufacturing cost of the TFT array substrate will not be reduced as a whole.

The above-mentioned TFT array substrate structure provided by the embodiment of the present invention can be applied to such as Advanced Super Dimension Switch (ADS, Advanced Super Dimension Switch), Plane Switching (IPS, In Plane Switching) or Twisted Nematic (TN, Twisted Nematic) type The array substrate may also be applied in an organic electroluminescent device (OLED), which is not limited here.

Based on the same concept of the utility model, the embodiment of the utility model also provides a display device, including the above-mentioned TFT array substrate provided by the embodiment of the utility model. The implementation of the display device can refer to the above-mentioned embodiment of the TFT array substrate. No longer.

In a specific implementation, the display device may be a liquid crystal panel, an electronic paper, an OLED panel, a liquid crystal TV, a liquid crystal display, a digital photo frame, a mobile phone, a tablet computer, and other products or components with any display function.

Based on the same concept of the utility model, the embodiment of the utility model also provides a method for preparing the above-mentioned TFT array substrate, as shown in FIG. 8 , which specifically includes the following steps:

S101, forming a gate line and a first gate electrically connected to the gate line on the substrate;

S102, forming a gate insulating layer covering the first gate and the gate line;

S103, forming a semiconductor layer on the gate insulating layer and above the gate;

S104, forming opposite source electrodes and drain electrodes on the semiconductor layer;

Further, when forming the source electrode and the drain electrode, a data line electrically connected to the source electrode is also formed;

The above steps S101~S104 are the same as the prior art, and the specific patterning process and the specific materials of each component will not be described in detail here. The following steps S105~S106 are the differences between the utility model and the prior art:

S105, forming a passivation layer covering the source electrode and the drain electrode; wherein, when patterning the passivation layer, it is necessary to form a via hole connecting the drain electrode and the pixel electrode in the passivation layer; further, it is also necessary to form a via hole in the passivation layer and The gate insulating layer forms a via hole connecting the second gate and the gate line, so as to ensure the electrical connection between the second gate and the gate line.

S106, forming a pixel electrode electrically connected to the drain and a second gate electrically connected to the gate line on the passivation layer;

Specifically, the pixel electrode and the second gate can be made of transparent conductive materials such as indium tin oxide ITO or zinc tin oxide IZO.

A TFT array substrate and a display device provided by the embodiments of the present invention, on the basis of the existing TFT structure, a second grid located above the semiconductor layer is added on the passivation layer of the TFT, and when the TFT is working, a new grid is added After the second gate of the TFT is energized, a current channel will be formed in the semiconductor layer below it, and a current channel will be formed in the semiconductor layer after the original first gate of the TFT is energized, that is, a current channel will be formed in the semiconductor layer. Two current channels, thus, without increasing the gate scan signal strength of the gate line, the overall conduction current of the TFT semiconductor layer is improved; and, since the newly added second gate is arranged above the semiconductor layer, The size of the pixel unit occupied by the entire TFT structure will not be increased, so the aperture ratio of the pixel unit will not be reduced.

Obviously, those skilled in the art can make various changes and modifications to the utility model without departing from the spirit and scope of the utility model. In this way, if these modifications and variations of the utility model fall within the scope of the claims of the utility model and equivalent technologies thereof, the utility model is also intended to include these modifications and variations.

Claims (7)

1. thin-film transistor tft array substrate, comprise: be successively set on first grid, gate insulation layer, semiconductor layer, source electrode, drain electrode and passivation layer on the substrate, it is characterized in that, also comprise: be arranged on the described passivation layer and be positioned at the second grid of described semiconductor layer top.

2. tft array substrate as claimed in claim 1 is characterized in that, described second grid is electrical connected by grid line corresponding in via hole and the described tft array substrate.

3. tft array substrate as claimed in claim 1 or 2 is characterized in that, described second grid is transparent conductive material or metal material.

4. tft array substrate as claimed in claim 3 is characterized in that, described second grid arranges with layer with the pixel electrode that is positioned at the tft array substrate on the described passivation layer.

5. tft array substrate as claimed in claim 1 is characterized in that, also is provided with ohmic contact layer between described semiconductor layer and the source-drain electrode.

6. a display unit is characterized in that, comprises each described tft array substrate such as claim 1-5.

7. display unit as claimed in claim 6 is characterized in that, described display unit is liquid crystal panel, Electronic Paper, oled panel, LCD TV, liquid crystal display, DPF, mobile phone or panel computer.

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