CN202815089U - Active probe for measuring KHz-rate clock - Google Patents
Active probe for measuring KHz-rate clock Download PDFInfo
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- CN202815089U CN202815089U CN 201220406356 CN201220406356U CN202815089U CN 202815089 U CN202815089 U CN 202815089U CN 201220406356 CN201220406356 CN 201220406356 CN 201220406356 U CN201220406356 U CN 201220406356U CN 202815089 U CN202815089 U CN 202815089U
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- active probe
- electrically connected
- clock
- signal input
- cpld
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- 239000000523 sample Substances 0.000 title claims abstract description 33
- 238000006243 chemical reaction Methods 0.000 claims description 14
- 101100003180 Colletotrichum lindemuthianum ATG1 gene Proteins 0.000 claims description 4
- 238000005259 measurement Methods 0.000 description 5
- 101100439969 Arabidopsis thaliana CLPD gene Proteins 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000007812 deficiency Effects 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
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Abstract
Disclosed is an active probe for measuring a KHz-rate clock, comprising a counter (1), a frequency multiplication circuit (2), and an active probe (3), wherein the signal input part of the active probe (3) is electrically connected with the signal input part of the frequency multiplication circuit (2); and the signal output part of the frequency multiplication circuit (2) is electrically connected with the signal input part of the active probe (3). The active probe of the utility model, with a small and exquisite shape, is capable of carrying out 1000 times of frequency multiplication over the pick clock signals and lifting the precision of a common general counter for measuring the KHz-grade clock to the PPM rate.
Description
Technical field
Key in herein technical field and describe paragraph.The utility model relates to frequency signal fields of measurement technical field, is specifically related to a kind of active probe of the KHz of measurement level clock.
Background technology
Key in herein background technology and describe paragraph.At present, existing common active probe is without double frequency function, be equivalent to clock signal is directly inputted to counter equipment, the measured value of counter is the actual value of active probe input, and this method can't allow the general common counter realize the measurement of KHz level clock PPM levels of precision.
Summary of the invention
Key in herein summary of the invention and describe paragraph.The purpose of this utility model is exactly without double frequency function for present existing common active probe, be equivalent to clock signal is directly inputted to counter equipment, the measured value of counter is the actual value of active probe input, this method can't allow the general common counter realize the deficiency of the measurement of KHz level clock PPM levels of precision, and a kind of active probe of the KHz of measurement level clock is provided.
The utility model is comprised of counter, frequency multiplier circuit and active probe, and the signal output part of counter is electrically connected with the signal input part of frequency multiplier circuit, and the signal output part of frequency multiplier circuit is electrically connected with the signal input part of active probe 3.
Frequency multiplier circuit is by voltage controlled oscillator, CPLD and low-pass filter form, the output terminal of voltage controlled oscillator is electrically connected with the clock signal input terminal of active probe radio frequency interface and CPLD respectively, the clock signal output terminal of CPLD is electrically connected with the clock signal input terminal clk1 of counter clock, the clock signal input terminal of CPLD is electrically connected with the probe segment of active probe, the up-conversion of CPLD is connected with down-conversion signal with the up-conversion of low-pass filter and is connected with the down coversion pin, and the control signal output terminal of low-pass filter is electrically connected with the voltage-controlled end of voltage controlled oscillator.
The utility model has the advantages that: profile is smaller and more exquisite, can carry out 1000 times of frequencys multiplication with picking up clock signal, and the general common counter is brought up to the PPM level to the measuring accuracy of KHz level clock.
Description of drawings
Fig. 1 is the utility model structural representation.
Fig. 2 is the frequency multiplier circuit structural representation.
Embodiment
As shown in Figure 1, the utility model is comprised of counter 1, frequency multiplier circuit 2 and active probe 3, and the signal output part of counter 1 is electrically connected with the signal input part of frequency multiplier circuit 2, and the signal output part of frequency multiplier circuit 2 is electrically connected with the signal input part of active probe 3.
Frequency multiplier circuit 2 is by voltage controlled oscillator 4, CPLD 5 and low-pass filter 6 form, the output terminal of voltage controlled oscillator 4 is electrically connected with the clock signal input terminal of active probe 3 radio frequency interfaces and CPLD 5 respectively, the clock signal output terminal of CPLD 5 is electrically connected with the clock signal input terminal clk1 of counter 1 clock, the clock signal input terminal of CPLD 5 is electrically connected with the probe segment of active probe 3, the up-conversion of CPLD 5 is connected with down-conversion signal with the up-conversion of low-pass filter and is connected with the down coversion pin, and the control signal output terminal of low-pass filter is electrically connected with the voltage-controlled end of voltage controlled oscillator.
Principle of work: output terminal voltage controlled oscillator 4(VCXO) is electrically connected with the clock signal input terminal of active probe 3 radio frequency interfaces and CPLD 5 respectively, CPLD 5(CLPD) clock signal output terminal is electrically connected with the clock signal input terminal clk1 of counter 1 clock, the clock signal input terminal of CPLD 5 is seen Fig. 1 with the probe segment 3-1(of active probe 3) be electrically connected, be responsible for the collection of tested frequency signal, CPLD 5(CLPD) up-conversion signal (up) is connected down with down-conversion signal) signal is connected down with the up-conversion signal (up) of low-pass filter respectively with down-conversion signal) pin is connected, the phase demodulation output signal is processed by low-pass filter 6, output one direct current signal that is directly proportional with signal phase (the control signal output terminal is ctrout), control signal output terminal (ctrout) and the voltage controlled oscillator 4(VCXO of low-pass filter) voltage-controlled end (VTR) be electrically connected, control voltage controlled oscillator 4(VCXO) oscillation frequency guarantees control voltage controlled oscillator 4(VCXO) output frequency be always 100 times of measured signal frequency.
Claims (2)
1. active probe of measuring KHz level clock, it is characterized in that it is comprised of counter (1), frequency multiplier circuit (2) and active probe (3), the signal output part of counter (1) is electrically connected with the signal input part of frequency multiplier circuit (2), and the signal output part of frequency multiplier circuit (2) is electrically connected with the signal input part of active probe (3).
2. a kind of active probe of measuring KHz level clock according to claim 1, it is characterized in that frequency multiplier circuit (2) is by voltage controlled oscillator (4), CPLD (5) and low-pass filter (6) form, the output terminal of voltage controlled oscillator (4) is electrically connected with the clock signal input terminal of active probe (3) radio frequency interface and CPLD (5) respectively, the clock signal output terminal of CPLD (5) is electrically connected with the clock signal input terminal clk1 of counter (1) clock, the clock signal input terminal of CPLD (5) is electrically connected with the probe segment of active probe (3), the up-conversion of CPLD (5) is connected with down-conversion signal with the up-conversion of low-pass filter (6) and is connected with the down-conversion signal pin, and the control signal output terminal of low-pass filter (6) is electrically connected with the voltage-controlled end of voltage controlled oscillator (4).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220406356 CN202815089U (en) | 2012-08-16 | 2012-08-16 | Active probe for measuring KHz-rate clock |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220406356 CN202815089U (en) | 2012-08-16 | 2012-08-16 | Active probe for measuring KHz-rate clock |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202815089U true CN202815089U (en) | 2013-03-20 |
Family
ID=47873947
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201220406356 Expired - Fee Related CN202815089U (en) | 2012-08-16 | 2012-08-16 | Active probe for measuring KHz-rate clock |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202815089U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9952956B2 (en) | 2015-07-06 | 2018-04-24 | International Business Machines Corporation | Calculating the clock frequency of a processor |
-
2012
- 2012-08-16 CN CN 201220406356 patent/CN202815089U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9952956B2 (en) | 2015-07-06 | 2018-04-24 | International Business Machines Corporation | Calculating the clock frequency of a processor |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130320 Termination date: 20150816 |
|
| EXPY | Termination of patent right or utility model |