CN202134003U - A data processing card with multiple protection mechanisms for IP modules - Google Patents
A data processing card with multiple protection mechanisms for IP modules Download PDFInfo
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- CN202134003U CN202134003U CN201120268872U CN201120268872U CN202134003U CN 202134003 U CN202134003 U CN 202134003U CN 201120268872 U CN201120268872 U CN 201120268872U CN 201120268872 U CN201120268872 U CN 201120268872U CN 202134003 U CN202134003 U CN 202134003U
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- 238000012545 processing Methods 0.000 title claims abstract description 24
- 230000004224 protection Effects 0.000 title claims abstract description 6
- 230000007246 mechanism Effects 0.000 title claims abstract description 4
- 230000008859 change Effects 0.000 abstract description 2
- 230000002708 enhancing effect Effects 0.000 abstract 1
- 238000013461 design Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 5
- 238000004891 communication Methods 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 4
- 230000009979 protective mechanism Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
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- ATHVAWFAEPLPPQ-VRDBWYNSSA-N 1-stearoyl-2-oleoyl-sn-glycero-3-phosphocholine Chemical compound CCCCCCCCCCCCCCCCCC(=O)OC[C@H](COP([O-])(=O)OCC[N+](C)(C)C)OC(=O)CCCCCCC\C=C/CCCCCCCC ATHVAWFAEPLPPQ-VRDBWYNSSA-N 0.000 description 1
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
本实用新型公开了一种具有IP模块多重保护机制的数据处理卡，包括FPGA芯片，所述FPGA芯片连接SDRAM存储器和Flash存储器，所述FPGA芯片上设置PLB总线，其特征是：所述PLB总线上分别连接微处理器、ICAP内部配置访问通道、PCIExpress总线接口、IPIF接口和DMA控制器，所述IPIF接口连接用户程序模块，所述用户程序模块上设置局部重配置区域。局部重配置区域能实时改变硬件的配置，节约了硬件资源，增强了系统的灵活性。
The utility model discloses a data processing card with multiple protection mechanisms for IP modules, comprising an FPGA chip, the FPGA chip is connected to SDRAM memory and Flash memory, a PLB bus is set on the FPGA chip, and the feature is that: the PLB bus Respectively connect microprocessor, ICAP internal configuration access channel, PCIExpress bus interface, IPIF interface and DMA controller, described IPIF interface connects user program module, and local reconfiguration area is set on described user program module. The partial reconfiguration area can change the hardware configuration in real time, saving hardware resources and enhancing the flexibility of the system.
Description
Technical field
The utility model relates to the protection of IP module and the dynamic local reconfiguration technology field of FPGA, specifically, relates to a kind of data processing card of the IP of having module multiple protective mechanism.
Background technology
In recent years, single FPGA realizes that circuit scale constantly enlarges, and the deviser can realize a complete system on single FPGA.The design that appears as SOPC of IP module provides very big facility.The deviser accomplishes the IP design, needs corresponding protection mechanism to prevent to design by bootlegging, steal or distort.
(structure of the also weighing) technology of reshuffling of FPGA is divided into full weight structure and local reconstruct, and the full weight structure is that configured in one piece bit stream file is downloaded among the FPGA; Local reconstruct relative complex does not influence the work of system's remainder when it can change the components of system as directed function.And the dynamic local configuration is in program operation process, to carry out, and the configuration of ability real time altering hardware has the advantage of economize on hardware resource and enhanced system dirigibility.
Dynamic local is reshuffled the modular design based on FPGA, and global design is divided into plurality of modules, and some is a restructural not, and some is reconfigurable, and each module is implemented in the zone separately.In the dynamic local configuration; There is a fixing structure (bus is grand) to stride according on the border of two modules; Each module is linked to each other respectively at this fixing structure in zone separately, and each module not only can but also can communicate with proximity modules in realization in regulation regional like this.
The utility model content
The technical matters that the utility model will solve provides a kind of data processing card of the IP of having module multiple protective mechanism.
The utility model adopts following technical scheme to realize goal of the invention:
A kind of data processing card with IP module multiple protective mechanism; Comprise fpga chip; Said fpga chip connects SDRAM storer and Flash storer, and the PLB bus is set on the said fpga chip, it is characterized in that: connect microprocessor, ICAP internal configurations access path, PCI Express EBI, IPIF interface and dma controller on the said PLB bus respectively; Said IPIF interface connects the user program module, on the said user program module part is set and reshuffles the zone.
As further qualification, store module in the said Flash storer through ciphered data Processing Algorithm IP to the present technique scheme.
As the further qualification to the present technique scheme, said fpga chip is provided with the physical erase button.
Compared with prior art; The advantage and the good effect of the utility model are: store data encrypted Processing Algorithm IP module in the Flash storer of the utility model; Under the control of the embedded soft nuclear of MicroBlaze of fpga chip; Read the IP module and decipher, write the part through ICAP internal configurations access path again and reshuffle the zone, accomplish processing different pieces of information.PCI Express can realize two duplex, serial, differential data high-speed transfer of equipment room as the communication interface of data processing card and host computer, and the SDRAM storer is mainly used in the metadata cache in the program operation process; The user program module, wherein has the part and reshuffles the zone on the PLB bus through IPIF interface carry.The configuration of zone ability real time altering hardware is reshuffled in the part, has practiced thrift hardware resource, has strengthened the dirigibility of system.To leave data processing IP module among the Flash in order further protecting, also to increase physical erase button and timing erase feature on the fpga chip.
Description of drawings
Fig. 1 is the block diagram of the utility model preferred embodiment.
Embodiment
Below in conjunction with accompanying drawing and preferred embodiment the utility model is made detailed description further.
Referring to Fig. 1, the utility model comprises that fpga chip, SDRAM storer, Flash storer, PLB bus, microprocessor, ICAP internal configurations access path, PCI Express EBI, IPIF interface, user program module, part reshuffle zone, dma controller, local bus memory (LMB), MDM microprocessor debugging module and UART communication module.
Said fpga chip connects SDRAM storer and Flash storer; The PLB bus is set on the said fpga chip; Connect microprocessor, ICAP internal configurations access path, PCI Express EBI, IPIF interface on the said PLB bus respectively, said IPIF interface connects the part and reshuffles zone and dma controller.DMA is a kind of high-speed data transmission pattern, allows direct read data between external apparatus and the storer, neither through CPU, does not also need CPU to intervene.
Said PLB bus also is connected with local bus memory (LMB), MDM microprocessor debugging module and UART communication module, and said microprocessor is the soft nuclear of MicroBlaze.
Said fpga chip is provided with physical erase button (not shown).
Store module in the Flash storer through ciphered data Processing Algorithm IP; Under the control of the embedded soft nuclear of MicroBlaze of fpga chip; Read the IP module and decipher, write the part through ICAP internal configurations access path again and reshuffle the zone, accomplish processing different pieces of information.For further protected data Processing Algorithm IP module, increase physical erase button and timing erase feature on the fpga chip
PCI Express can realize two duplex, serial, differential data high-speed transfer of equipment room as the communication interface of data processing card and host computer, and the SDRAM storer is mainly used in the metadata cache in the program operation process; The user program module, wherein has the part and reshuffles the zone on the PLB bus through IPIF interface carry.
After system powered on, fpga chip at first carried out global configuration, and this part mainly accomplishes soft nuclear of MicroBlaze and Peripheral Interface modules configured.Global configuration adopts initiatively parallel (Master BPI) configuration mode; The guiding user program was carried out after global configuration was accomplished; User program reads the data processing algorithm IP module that is stored among the FLASH; The configuration of the part being reshuffled the zone is accomplished through ICAP internal configurations access path in its deciphering back, accomplish building of total system hardware logic this moment.
The software systems of whole design are made up of PC control software and fpga chip system software.PC control software mainly comprises driver and user application software, and fpga chip software comprises that mainly peripheral hardware drives and user program.
PC control software mainly realize with pending data according to certain requirement packing after, be delivered to data processing card through PCI Express EBI, the data after accepting simultaneously to have handled.Can realize control through the PC control terminal, clock on the integrated circuit board etc. for example can be set various peripheral hardwares on the fpga chip.
User program in the soft nuclear of MicroBlaze is at first accomplished the local configuration of data processing algorithm IP module, and the control command that receives host computer then starts each peripheral hardware.After for example host computer was ready to pending data, the soft nuclear of MicroBlaze started the dma controller reading of data and starts the IP module and carries out data processing.After the user program module receives regularly destruction instruction, start regularly destruction program, the time of treating is then wiped the data processing algorithm IP module that is stored among the FLASH, or when the physical erase button is pressed, carries out erasing move.
Certainly; Above-mentioned explanation is not the restriction to the utility model; The utility model also be not limited only to above-mentioned for example, variation, remodeling, interpolation or replacement that those skilled in the art are made in the essential scope of the utility model also belong to the protection domain of the utility model.
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Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201120268872U CN202134003U (en) | 2011-07-27 | 2011-07-27 | A data processing card with multiple protection mechanisms for IP modules |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201120268872U CN202134003U (en) | 2011-07-27 | 2011-07-27 | A data processing card with multiple protection mechanisms for IP modules |
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| CN202134003U true CN202134003U (en) | 2012-02-01 |
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| CN201120268872U Expired - Fee Related CN202134003U (en) | 2011-07-27 | 2011-07-27 | A data processing card with multiple protection mechanisms for IP modules |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103809158A (en) * | 2012-11-07 | 2014-05-21 | 中国科学院微电子研究所 | A SAR radar data encryption device and method based on SOC chip |
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2011
- 2011-07-27 CN CN201120268872U patent/CN202134003U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103809158A (en) * | 2012-11-07 | 2014-05-21 | 中国科学院微电子研究所 | A SAR radar data encryption device and method based on SOC chip |
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| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20120201 Termination date: 20140727 |
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| EXPY | Termination of patent right or utility model |