CN201816147U - Semiconductor chip splitting tool - Google Patents
Semiconductor chip splitting tool Download PDFInfo
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- CN201816147U CN201816147U CN2010205365428U CN201020536542U CN201816147U CN 201816147 U CN201816147 U CN 201816147U CN 2010205365428 U CN2010205365428 U CN 2010205365428U CN 201020536542 U CN201020536542 U CN 201020536542U CN 201816147 U CN201816147 U CN 201816147U
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- wafer
- support plate
- groove
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 9
- 239000004836 Glue Stick Substances 0.000 claims abstract description 8
- 239000013078 crystal Substances 0.000 claims abstract description 6
- 238000005096 rolling process Methods 0.000 claims abstract description 4
- 238000005336 cracking Methods 0.000 claims abstract description 3
- 235000012431 wafers Nutrition 0.000 abstract description 56
- 230000000903 blocking effect Effects 0.000 abstract description 2
- 238000006073 displacement reaction Methods 0.000 abstract 1
- 238000005520 cutting process Methods 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- GVVPGTZRZFNKDS-JXMROGBWSA-N geranyl diphosphate Chemical compound CC(C)=CCC\C(C)=C\CO[P@](O)(=O)OP(O)(O)=O GVVPGTZRZFNKDS-JXMROGBWSA-N 0.000 description 2
- 239000002699 waste material Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 1
- 238000003698 laser cutting Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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- Mechanical Treatment Of Semiconductor (AREA)
- Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
Abstract
半导体晶片的裂片工具。涉及半导体晶片加工中将晶片进行裂解的工具。避免晶粒出现水平位移。包括一弹性的晶片承托板,以及滚碾晶片使晶片分裂为若干晶粒的硬质胶棒,所述晶片承托板上设有容纳晶片的凹槽,所述凹槽的深度小于晶片厚度。本实用新型在晶片承托板上设置了一个浅凹槽,相当于给晶片整体的边缘设置了一个定位阻拦台阶。这样,无论从那个方向对晶片进行碾压,也不会造成晶粒的串动、错位。在晶片承托板下部设置底板,是为便于操作者转动晶片承托板,按90°角度转动,适应纵横交错的沟槽,也更符合操作者用力习惯。
Cleaving tool for semiconductor wafers. The utility model relates to a tool for cracking wafers in semiconductor wafer processing. Avoid horizontal displacement of grains. It includes an elastic wafer support plate and a hard glue stick for rolling the wafer to split the wafer into several grains. The wafer support plate is provided with a groove for accommodating the wafer, and the depth of the groove is less than the thickness of the wafer. . The utility model is provided with a shallow groove on the wafer support plate, which is equivalent to providing a positioning blocking step for the overall edge of the wafer. In this way, no matter from which direction the wafer is rolled, it will not cause serial movement and dislocation of the crystal grains. The base plate is arranged at the lower part of the wafer support plate to facilitate the operator to rotate the wafer support plate at an angle of 90° to adapt to the criss-cross grooves and more in line with the operator's habit of exerting force.
Description
技术领域technical field
本实用新型涉及半导体晶片加工中将晶片进行裂解的工具。The utility model relates to a tool for cracking wafers in semiconductor wafer processing.
技术背景technical background
随着半导体行业的迅速发展,拥有一种能够保证良好的晶粒外观的作业方式,是去除影响产量提高的贫瘠,保证产品的信赖性,增加企业形象,增强企业竞争力不可或缺的技术攻关。With the rapid development of the semiconductor industry, having an operation method that can ensure a good grain appearance is an indispensable technical breakthrough to remove the impoverishment that affects the increase in yield, ensure product reliability, increase corporate image, and enhance corporate competitiveness. .
GPP晶片采用刀片切割,在保证切割外观良好的前提下,切割的最大速度=50mm/s。对于大晶粒尺寸的晶片例如140mil,切割速度=20mm/s,切割效率偏低。而采用激光半切透,激光切割的速度=160mm/s。其二,对于O/J的晶片若采用刀片切割完全切透的方式,由于刀片刀刃处呈现梯形的坡度,造成晶粒侧面P/N结呈现波度,影响晶粒电压以及电性的稳定性。其三,采用刀片切割造成兰膜的浪费,水、气的浪费。GPP wafers are cut with a blade, and the maximum cutting speed is 50mm/s under the premise of ensuring a good cutting appearance. For a wafer with a large grain size such as 140mil, the cutting speed is 20mm/s, and the cutting efficiency is low. However, if the laser is used for half-cutting, the speed of laser cutting is 160mm/s. Second, if the O/J wafer is completely cut with a blade, due to the trapezoidal slope at the blade edge, the P/N junction on the side of the grain will show waviness, which will affect the voltage and electrical stability of the grain. . Its three, adopt blade cutting to cause the waste of blue film, the waste of water, gas.
在微电子行业半导体制程中,对于O/J晶片(没有沟槽的类型晶片)采用刀片半切透状态后,或GPP晶片(具有玻璃钝化保护P/N结的类型晶片)在激光切割硅片后,对呈现半切透状态的硅片采用被切割面朝下,在相反的一面施加垂直于晶片均匀的力进行裂片,已达到将整个硅片分割成符合要求的单个小晶粒的目的。为此,我们将晶片放置在弹性承托板上,再将晶片上覆盖一层膜,然后,用胶棒对晶片来回碾压,着力点对准晶片上沟槽部位。但使用中,我们发现晶片在胶棒往复碾压过程中,分裂下来的晶粒会出现水平位移,造成错位。In the semiconductor manufacturing process of the microelectronics industry, after the O/J wafer (the type wafer without grooves) is used in the half-cut state of the blade, or the GPP wafer (the type wafer with glass passivation to protect the P/N junction) is laser cut on the silicon wafer Finally, the cut side of the silicon wafer in a half-cut state is facing downward, and a uniform force perpendicular to the wafer is applied on the opposite side for splitting, which has achieved the purpose of dividing the entire silicon wafer into single small grains that meet the requirements. To this end, we place the wafer on an elastic support plate, cover the wafer with a layer of film, and then use a glue stick to roll the wafer back and forth, focusing on the groove on the wafer. However, during use, we found that during the reciprocating rolling process of the wafer with the glue stick, the split crystal grains will be displaced horizontally, resulting in misalignment.
实用新型内容Utility model content
本实用新型的目的在于避免晶粒出现水平位移的半导体晶片的裂片工具。The purpose of the utility model is to avoid the splitting tool of the semiconductor wafer in which the crystal grains are horizontally displaced.
本实用新型的技术方案是:包括一弹性的晶片承托板,以及滚碾晶片使晶片分裂为若干晶粒的硬质胶棒,所述晶片承托板上设有容纳晶片的凹槽,所述凹槽的深度小于晶片厚度。The technical scheme of the utility model is: comprising an elastic wafer supporting plate, and a hard glue stick for rolling the wafer to split the wafer into several grains, the wafer supporting plate is provided with a groove for accommodating the wafer, so The depth of the groove is less than the thickness of the wafer.
所述晶片承托板下还设有底板。A bottom plate is also provided under the wafer supporting plate.
本实用新型在晶片承托板上设置了一个浅凹槽,相当于给晶片整体的边缘设置了一个定位阻拦台阶。这样,无论从那个方向对晶片进行碾压,也不会造成晶粒的串动、错位。在晶片承托板下部设置底板,是为便于操作者转动晶片承托板,按90°角度转动,适应纵横交错的沟槽,也更符合操作者用力习惯。The utility model is provided with a shallow groove on the wafer support plate, which is equivalent to providing a positioning blocking step for the overall edge of the wafer. In this way, no matter from which direction the wafer is rolled, it will not cause serial movement and dislocation of the crystal grains. The bottom plate is arranged at the bottom of the wafer support plate to facilitate the operator to rotate the wafer support plate at an angle of 90° to adapt to the criss-cross grooves and more in line with the operator's habit of exerting force.
附图说明Description of drawings
图1是本实用新型的结构示意图Fig. 1 is a structural representation of the utility model
图中1是晶片承托板,2是凹槽,3是沟槽,4是晶粒,5是胶棒,6是晶片,7是底板。Among the figure, 1 is a chip supporting plate, 2 is a groove, 3 is a groove, 4 is a grain, 5 is a glue stick, 6 is a wafer, and 7 is a base plate.
图2是图1的俯视图Figure 2 is a top view of Figure 1
具体实施方式Detailed ways
本实用新型如图1、2所示,包括一弹性的晶片承托板1,以及滚碾晶片6使晶片6分裂为若干晶粒4的硬质胶棒5,所述晶片承托板1上设有容纳晶片6的凹槽2,所述凹槽2的深度小于晶片6厚度。The utility model, as shown in Figures 1 and 2, comprises an elastic wafer support plate 1, and a
所述晶片承托板1下还设有底板7。A
本实用新型使用方法如下:The utility model using method is as follows:
1)、将晶片6置入凹槽2内,再施加其它工艺手段;1), the
2)、采用胶棒5沿晶片6上的沟槽3进行滚碾,横向沟槽3滚碾完毕后,转动晶片承托板1,对纵向沟槽再进行滚碾,直至晶片6沿沟槽3分裂为若干晶粒4。2), use the
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010205365428U CN201816147U (en) | 2010-09-19 | 2010-09-19 | Semiconductor chip splitting tool |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010205365428U CN201816147U (en) | 2010-09-19 | 2010-09-19 | Semiconductor chip splitting tool |
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| Publication Number | Publication Date |
|---|---|
| CN201816147U true CN201816147U (en) | 2011-05-04 |
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| CN2010205365428U Expired - Fee Related CN201816147U (en) | 2010-09-19 | 2010-09-19 | Semiconductor chip splitting tool |
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| Country | Link |
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| CN (1) | CN201816147U (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102814868A (en) * | 2012-08-24 | 2012-12-12 | 深圳市金洲精工科技股份有限公司 | Method for processing graphene plate and processing device thereof |
| CN103811422A (en) * | 2014-02-25 | 2014-05-21 | 福建安特微电子有限公司 | Cmos silicon wafer lobe processing device and processing method thereof |
| CN107672065A (en) * | 2017-10-10 | 2018-02-09 | 覃其伦 | The sliver apparatus of silicon chip |
| CN109304816A (en) * | 2017-07-26 | 2019-02-05 | 天津环鑫科技发展有限公司 | Silicon wafer cutting and splitting process |
-
2010
- 2010-09-19 CN CN2010205365428U patent/CN201816147U/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102814868A (en) * | 2012-08-24 | 2012-12-12 | 深圳市金洲精工科技股份有限公司 | Method for processing graphene plate and processing device thereof |
| CN103811422A (en) * | 2014-02-25 | 2014-05-21 | 福建安特微电子有限公司 | Cmos silicon wafer lobe processing device and processing method thereof |
| CN103811422B (en) * | 2014-02-25 | 2016-04-13 | 福建安特微电子有限公司 | A kind of processing unit of cmos silicon chip sliver and processing method thereof |
| CN109304816A (en) * | 2017-07-26 | 2019-02-05 | 天津环鑫科技发展有限公司 | Silicon wafer cutting and splitting process |
| CN107672065A (en) * | 2017-10-10 | 2018-02-09 | 覃其伦 | The sliver apparatus of silicon chip |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20110504 Termination date: 20150919 |
|
| EXPY | Termination of patent right or utility model |