CN201378803Y - A cascaded multilevel converter - Google Patents

Abstract

The utility model relates to a cascaded multilevel converter, which comprises: the input end of a pulse width modulation rectifier is connected with the power grid, the output end of the pulse width modulation rectifier is connected with a DC bus, and the DC bus is connected with an inverter. At the input end, the inverter supplies power to the AC motor; the information exchange between a control unit and the pulse width modulation rectifier makes the voltage at both ends of the pulse width modulation rectifier and the capacitor voltage balance between the DC bus and the input power factor of the grid side as follows: 1, and control the inverter to output alternating current with variable frequency. The utility model does not need a phase-shifting transformer, is small in size, light in weight, low in cost, can operate in four quadrants, has obvious economic benefits, and is suitable for popularization and application.

Description

A cascaded multilevel converter

technical field

The utility model relates to a topology structure of a power electronic high-voltage large-capacity multilevel converter, in particular to a cascaded multilevel converter.

Background technique

High-voltage and large-capacity AC motors are widely used in industrial fields such as steel rolling, papermaking, cement, coal, railways, and ships. The frequency conversion and speed regulation of AC motors by multi-level technology can not only achieve the purpose of energy saving, but also improve the process conditions, production efficiency and product quality.

At present, there are mainly two types of multilevel converters for frequency conversion and speed regulation of high-power AC motors: one is a medium-voltage three-level converter using diode clamping, and the other is an H-bridge cascaded high-voltage multi-level converter. level shifter. Three-level converters control AC motors with a voltage of 3kV and below, while H-bridge cascaded multilevel converters mainly control large-capacity high-voltage AC motors with a voltage of 6kV to 10kV.

Although the transformer in the three-level converter is relatively simple, and the harmonics of the output voltage are also low, the three-level converter has the problem of difficulty in applying high voltage (generally, high voltage refers to 6kV ~ 10kV). It is also difficult to balance the capacitor voltage of the level converter.

The H-bridge cascaded converter is easy to apply high voltage, and the input side uses a specially manufactured phase-shifting transformer. Through the superposition effect of this phase-shifting transformer, a sinusoidal grid-side current can be generated, making its power factor close to 1. At the same time Harmonic pollution to the grid is avoided. However, there are also some problems in the H-bridge cascaded multilevel converter. For example, since the front end of each power unit in the H-bridge cascaded multilevel converter uses a diode uncontrolled rectification, the AC motor braking At this time, the converter cannot realize four-quadrant operation, that is, the energy is fed back to the power grid; in addition, the phase-shifting transformer has many taps, and its weight and volume are large, and its cost is high.

Contents of the invention

In view of the above problems, the purpose of this utility model is to provide an intelligent cascaded multilevel converter that does not need a transformer and can realize four-quadrant operation.

In order to achieve the above object, the utility model adopts the following technical solutions: a cascaded multilevel converter, which is characterized in that it includes: the input end of a pulse width modulation rectifier is connected to the power grid, and the output end of the pulse width modulation rectifier Connect the DC bus, the DC bus is connected to the input end of an inverter, and the inverter supplies power to the AC motor; a control unit performs information interaction with the pulse width modulation rectifier, and controls the pulse width modulation rectifier at both ends of the pulse width modulation rectifier The capacitor voltage between the voltage and the DC bus is balanced, the input power factor of the grid side is controlled to be 1, and the inverter is controlled to output alternating current with variable frequency.

In the pulse width modulation rectifier, the power grid transmits alternating current to the multilevel bridge arm connected to the inductance through an inductor; a voltage and current detection unit is connected to the input end of the pulse width modulation rectifier, which connects the power grid The current and voltage signals input into the pulse width modulation rectifier are detected and sent to the control unit.

The multi-level bridge arm includes an odd number of basic units, and the basic unit includes a plurality of power switching devices connected in series, and the series circuit is connected in parallel with a clamping capacitor and a voltage sensor, and the voltage sensor connects the clamping capacitor The voltage signal at both ends is detected and transmitted to the control unit.

The control unit includes: an analog-to-digital acquisition module, which receives the signal sent by the voltage and current detection unit and the voltage sensor in the pulse width modulation rectifier, and converts it into a digital signal; a switching value acquisition module, which acquires the signal of the power switching device Overcurrent and overheating fault signals; a digital signal microprocessor, including a voltage balance module and a pulse width modulation generation module, the voltage balance module receives and calculates the signal transmitted by the analog-to-digital acquisition module, and obtains the pulse The deviation between the voltage at both ends of the rectifier and the normal value is wide modulated, and then the pulse width modulation generating module sends out a pulse width modulation control pulse signal and an auxiliary control signal according to the deviation; the digital signal microprocessor is in the When there is a fault in the power switching device, it receives the fault signal transmitted by the switching value acquisition module and sends a corresponding protection command in time; a switching value output module receives the auxiliary control signal and protection command transmitted by the digital signal microprocessor; A pulse width modulation expansion module, receiving the pulse width modulation control pulse signal transmitted by the pulse width modulation output module and the auxiliary control signal transmitted by the switch output module, and expanding the pulse width modulation control pulse signal; at least one The drive circuit receives the pulse width modulation control pulse signal transmitted by the pulse width modulation expansion module and expands it again to drive the corresponding power switching devices in the pulse width modulation rectifier and inverter to turn on or off, so that the The capacitor voltage balance between the voltage at both ends of the pulse width modulation rectifier and the DC bus and the input power factor of the grid side is 1, and the inverter is controlled to output alternating current with variable frequency.

The inverter includes at least one multilevel bridge arm, which receives the direct current delivered by the pulse width modulation rectifier, converts it into alternating current with variable frequency and outputs it.

The pulse width modulation rectifier and the inverter are in a back-to-back structure.

Because the utility model adopts the above technical scheme, it has the following advantages: 1. Since the utility model omits the phase-shifting transformer, the volume and weight are reduced, and the cost is reduced. 2. Since a voltage balance module and a pulse width modulation generation module are preset in the control unit adopted by the utility model, it can control the AC power input to the PWM rectifier, the AC power output by the inverter, and the voltage at both ends of the power switching device. Real-time monitoring and control, thus improving the quality of grid power factor and inverter output voltage waveform, ensuring capacitor voltage balance, and easy to control high-voltage, large-capacity and multi-level AC motors. 3. Since the pulse width modulation rectifier and the inverter adopted in the utility model are in a back-to-back structure, the converter can realize four-quadrant operation when the AC motor brakes, which improves the use efficiency of the AC motor. The utility model is small in size, light in weight, low in cost, can also operate in four quadrants, has obvious economic benefits, and is suitable for the field of speed regulation of different middle and high voltage AC motors.

Description of drawings

Fig. 1 is the block diagram of the utility model converter

Fig. 2 is the structural diagram of the utility model pulse width modulation rectifier

Fig. 3 is the structural diagram of the utility model inverter

Fig. 4 is the structural diagram of multi-level bridge arm of the present invention

Fig. 5 is one of the structural diagrams of the basic unit in the two-level bridge arm of the present invention

Fig. 6 is one of the structural diagrams of the basic unit in the two-level bridge arm of the present invention

Fig. 7 is the structural diagram of the intermediate unit of the utility model two-level bridge arm

Fig. 8 is a block diagram of the utility model control unit

Fig. 9 is a composition diagram of the utility model digital signal microprocessor

Detailed ways

Below in conjunction with accompanying drawing and embodiment the utility model is described in detail.

As shown in FIG. 1 , the utility model includes a pulse width modulation rectifier 10 , a DC bus 20 , an inverter 30 and a control unit 40 . The input terminals 11, 12 and 13 on the pulse width modulation rectifier 10 are all connected to the grid, and the output terminals on the pulse width modulation rectifier 10 are respectively connected to a positive DC bus P and a negative DC bus N in the DC bus 20. A plurality of capacitors 21 are connected in series between the bus P and the DC bus N, and the anodes of the capacitors 21 are connected to the DC bus P, and both the DC bus P and the DC bus N are connected to the input terminal of the inverter 30 at the same time. The three-phase alternating current Usa, Usb and Usc output from the power grid are respectively sent to the pulse width modulation rectifier 10 through the input terminals 11, 12 and 13, and then converted into a stable amplitude direct current through the pulse width modulation rectifier 10, and the direct current is transmitted through the direct current bus 20 To the inverter 30, through the inverter 30, it is converted into frequency-variable alternating current Ua, Ub and Uc, and then delivered to the three-phase alternating current motor through the output terminals 31, 32 and 33 on the inverter 30 (not shown in the figure) shown) power supply. The output phases of the alternating currents Ua, Ub, and Uc correspond to the input phases of the alternating currents Usa, Usb, and Usc.

In the above process, the control unit 40 and the PWM rectifier 10 perform information interaction, so that the voltage at both ends of the PWM rectifier 10 and the voltage of the capacitor 21 between the DC bus 20 are balanced, and at the same time, the three-phase alternating current Usa, The input power factors of Usb and Usc are both 1, and the inverter 30 is controlled to output alternating current with variable frequency.

In the above embodiment, the pulse width modulation rectifier 10 and the inverter 30 are arranged back to back, so the utility model realizes four-quadrant movement, that is, bidirectional flow of energy, thereby improving the efficiency of the three-phase AC motor.

As shown in FIG. 2 , the pulse width modulation rectifier 10 includes a three-phase cascaded multilevel bridge arm 14 , an inductor 15 and a voltage and current detection unit 16 . Among them, the input terminals 11, 12 and 13 are respectively connected to three multi-level bridge arms 14 through three inductors 15, and the three-phase alternating current Usa, Usb and Usc output from the power grid are transmitted to the three multi-level bridges through three inductors 15 respectively. Inside the arm 14. The voltage and current detection unit 16 is connected to the input terminals 11 , 12 and 13 , detects the current and voltage signal 17 of the grid input pulse width modulation rectifier 10 through the voltage sensor and the current sensor, and then transmits these signals to the control unit 40 . In this embodiment, the voltage sensor and the current sensor constituting the voltage and current detection unit 16 are detection devices in the prior art.

As shown in FIG. 3 , the inverter 30 includes a three-phase cascaded multilevel bridge arm 14, and the direct current output by the pulse width modulation rectifier 10 is correspondingly delivered to the multilevel bridge arm 14 of the inverter 30, Under the control of the control unit 40 , the multilevel bridge arm 14 converts the input direct current into alternating frequency with variable frequency, and outputs it to the three-phase alternating current motor.

As shown in FIG. 4, in the above-mentioned embodiment, each phase multilevel bridge arm 14 includes M (M is an odd number) basic units 141 connected in series, and the (M+1)/2 basic unit 141 is defined as middle unit. Wherein, each basic unit 141 is provided with a terminal X1 and a terminal X2 , and the intermediate unit is provided with a terminal X1 , a terminal X2 and a terminal X3 .

As shown in Fig. 5 and Fig. 6, in the above embodiment, each basic unit 141 includes two power switching devices 1411 connected in series, a clamping capacitor 1412 and a voltage sensor 1413, and the clamping capacitor 1412 and the voltage sensor 1413 are respectively connected with The power switching devices 1411 connected in series are connected in parallel, so the voltage sensor 1413 can detect the voltage signal 1414 at both ends of the clamping capacitor 1412 and send it to the control unit 40 . The sum of the voltages across the clamping capacitors 1412 in the multilevel bridge arm 14 of each phase is equal to the voltage across the PWM rectifier 10 . Terminal X1 is used to connect terminal X2 or DC bus P of another basic unit 141; terminal X2 is used to connect terminal X1 or DC bus N of another basic unit 141; terminal X3 in the intermediate unit is connected to the power grid or three-phase AC motor. In the above embodiment, the terminal X1 and terminal X2 in the basic unit 141 other than the intermediate unit are determined as follows: one end of the series circuit composed of two power switching devices 1411 is provided with a terminal X1 or a terminal X2, corresponding to this, A terminal X2 or a terminal X1 is provided at the midpoint of the series circuit.

As shown in FIG. 7 , the terminal X1, terminal X2 and terminal X3 of the basic unit 141 defined as the intermediate unit are determined as follows: a terminal X1 and a terminal X2 are respectively provided at both ends of the series circuit formed by the power switching device 1411, A terminal X3 is provided at the midpoint of the series circuit.

In the above embodiments, the power switching devices 1411 in the basic unit 141 may be connected in four series, or may be connected in series. The type of power switching device 1411 is based on the difference in the output voltage level of each basic unit 1411, and the power semiconductor switching device of the corresponding level is selected, such as IGBT (Insulated Gate Bipolar Transistor, insulated gate bipolar transistor), IGCT (Intergrated Gate Commutated Thyristors, integrated gate pole commutation thyristor), etc.

As shown in Figure 8, the control unit 40 includes a digital signal microprocessor 41, an analog-to-digital acquisition module 42, a switch value acquisition module 43, several switch value output modules 44, a pulse width modulation output module 45, a pulse width Modulation expansion module 46 , several driving circuits 47 and a man-machine communication interface 48 .

As shown in Figure 9, what the digital signal microprocessor 41 adopted is a high-performance DSP (digital signal processor, digital signal processor) chip, such as the DSP chip produced by TI Company as the model TMS320F2812, and a voltage balance module 411 is preset in it. And a pulse width modulation generation module 412, the digital signal microprocessor 41 completes the keyboard display and PC communication and monitoring functions through the serial man-machine communication interface 48.

The analog-to-digital acquisition module 42 is an analog-to-digital conversion circuit, which collects the current in the input pulse width modulation rectifier 10 detected by the voltage and current detection unit 16, the voltage signal 17 (as shown in Figure 2 ), and the voltage detected by the voltage sensor 1413. The voltage signal 1414 of each clamping capacitor 1412 in the basic unit 141 (as shown in FIG. 5 ), and the collected current, voltage signal 17 and voltage signal 1414 are converted into digital signals and sent to the digital signal microprocessor 41 .

The switching value acquisition module 43 collects the fault signal when the power switching device 1411 has faults such as overcurrent and overheating, and sends it to the digital signal microprocessor 41, so that the digital signal microprocessor 41 sends a protection instruction in time to take protective measures; When the power switching device 1411 does not have faults such as overcurrent and overheating, the switching value acquisition module 43 does not work. At the same time, the switching value output module 44 is an I/O interface, which can receive the switching value control signal output by the digital signal microprocessor 41, and assist the pulse width modulation expansion module 46 to perform signal expansion.

The voltage balance module 411 preset in the digital signal microprocessor 41 calculates the input current, the voltage signal signal 17 and the voltage signal 1414 to obtain the deviation between the voltage signal 1414 and the preset normal value, and then pulse width modulation The generation module 412 sends a PWM control pulse signal to the PWM output module 45 and an auxiliary control signal to the switch output module 44 according to the deviation. When the digital signal microprocessor 41 receives the fault signal transmitted by the switching value acquisition module 43, the digital signal microprocessor 41 judges the input fault signal, and sends out corresponding protection instructions, such as instructions such as shutting down or reducing power operation, For the switching value output module 44, the switching value output module 44 controls the opening and closing of the corresponding switch 49 through the relay 48, so as to execute the instruction issued by the digital signal microprocessor 41.

The pulse width modulation output module 45 is a 6-way pulse width modulation output interface, which transmits the pulse width modulation control pulse signal output by the digital signal microprocessor 41 to the pulse width modulation expansion module 46 . Under the auxiliary control of the switching value output module 44, the pulse width modulation expansion module 46 divides the 6×M pulse width modulation control pulse signals output by the pulse width modulation output module 45 into two 3×M pulse width modulation control pulse signals , M is the number of basic units 141 connected in series with each multilevel bridge arm 14 . Wherein each path of PWM control pulse signal passes through the corresponding driving circuit 47, and the driving circuit 47 expands the path of PWM control pulse signal into 2 paths of complementary PWM control pulse signals to drive the PWM rectifier 10 and The corresponding power switching device 1411 in the inverter 30 is turned on or off, so that the voltage at both ends of the PWM rectifier 10 and the voltage of the capacitor 21 between the DC bus 20 are balanced, so that the input power factor of the grid side is 1, and the The inverter 30 outputs alternating current with a variable frequency. The pulse width modulation extension module 46 in the present embodiment is a field programmable gate array device (FPGA, Field Programmable Gate Array) or a complex programmable logic device (CPLD, Complex ProgrammableLogic Device), such as the EPM7128S chip produced by Altera Corporation, which will pulse The width modulation control pulse signal is expanded into 6×M channels, and then output.

In each above-mentioned embodiment, the structure of each component, setting position, and connection thereof all can be changed to some extent, on the basis of the technical scheme of the present utility model, the improvement and equivalent transformation carried out to individual components should not be excluded in this application. outside the scope of protection of utility models.

Claims (8)

1. A cascaded multilevel converter, characterized in that it comprises: the input end of a pulse width modulation rectifier is connected to the power grid, the output end of the pulse width modulation rectifier is connected to a DC bus, and the DC bus is connected to an inverter The input terminal of the inverter, the inverter supplies power to the AC motor; a control unit performs information interaction with the pulse width modulation rectifier, and controls the voltage at both ends of the pulse width modulation rectifier and the capacitor voltage between the DC bus To achieve balance, control the input power factor of the grid side to be 1, and control the inverter to output alternating current with variable frequency. 2. A cascaded multilevel converter according to claim 1, characterized in that: in the pulse width modulation rectifier, the power grid transmits alternating current through an inductor to the multilevel converter connected to the inductor Bridge arm; a voltage and current detection unit connected to the input terminal of the pulse width modulation rectifier, which detects the current and voltage signals input from the power grid into the pulse width modulation rectifier and transmits them to the control unit. 3. A cascaded multilevel converter according to claim 2, wherein the multilevel bridge arm includes an odd number of basic units, and the basic units include a plurality of power switching devices connected in series, The series circuit is connected in parallel with a clamping capacitor and a voltage sensor, and the voltage sensor detects the voltage signal at both ends of the clamping capacitor and transmits it to the control unit. 4. A cascaded multilevel converter according to claim 1, 2 or 3, wherein the control unit includes: An analog-to-digital acquisition module, which receives the signals sent by the voltage and current detection unit and the voltage sensor in the pulse width modulation rectifier, and converts them into digital signals; A switching value acquisition module, which collects the overcurrent and overheating fault signals of the power switching device; A digital signal microprocessor, including a voltage balance module and a pulse width modulation generating module, the voltage balance module receives and calculates the signal transmitted by the analog-to-digital acquisition module, and obtains the voltage at both ends of the pulse width modulation rectifier and deviation between normal values, and then the pulse width modulation generating module sends out a pulse width modulation control pulse signal and an auxiliary control signal according to the deviation; , receiving the fault signal transmitted by the switching value acquisition module, and sending a corresponding protection instruction in time; A switch output module, receiving the auxiliary control signal and protection instruction transmitted by the digital signal microprocessor; A pulse width modulation expansion module, receiving the pulse width modulation control pulse signal transmitted by the pulse width modulation output module and the auxiliary control signal transmitted by the switch output module, and expanding the pulse width modulation control pulse signal; At least one drive circuit, receiving the pulse width modulation control pulse signal transmitted by the pulse width modulation expansion module and expanding it again, so as to drive the corresponding power switching devices in the pulse width modulation rectifier and inverter to turn on or off, so that The capacitor voltage balance between the voltage at both ends of the pulse width modulation rectifier and the DC bus and the grid-side input power factor is 1, and the inverter is controlled to output alternating current with variable frequency. 5. A cascaded multilevel converter according to claim 1, 2 or 3, characterized in that: said inverter comprises at least one said multilevel bridge arm, which receives said pulse width The direct current delivered by the modulating rectifier is converted into alternating current with variable frequency and output. 6. A cascaded multilevel converter according to claim 4, characterized in that: said inverter comprises at least one said multilevel bridge arm, which receives the pulse width modulation rectifier sent Direct current is converted into alternating current with variable frequency and output. 7. A cascaded multilevel converter as claimed in claim 1 or 2 or 3 or 6, characterized in that the pulse width modulation rectifier and the inverter are in a back-to-back structure. 8. A cascaded multilevel converter as claimed in claim 5, characterized in that the PWM rectifier and the inverter are in a back-to-back structure.

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