CN201374062Y

CN201374062Y - FPGA on-line configuration circuit

Info

Publication number: CN201374062Y
Application number: CN200820214384U
Authority: CN
Inventors: 魏洵佳
Original assignee: Konka Group Co Ltd
Current assignee: Konka Group Co Ltd
Priority date: 2008-12-12
Filing date: 2008-12-12
Publication date: 2009-12-30
Anticipated expiration: 2018-12-12

Abstract

The utility model discloses an FPGA on-line configuration circuit, which solves the technical problem that the FPGA can not accomplish the remote upgrade on programs through the FPGA per se. An FPGA chip arranged in the FPGA on-line configuration circuit is connected with a data selector; the data selector outputs different control signals to a FLASH chip during being electrified and after being electrified; and the FPGA chip is also respectively connected with a remote communication module and a socket. Compared with the prior art, the FPGA on-line configuration circuit can accomplish the configuration in a positive mode when the FPGA is electrified under the condition of no need of additional arrangement of a micro processor; the remote upgrade on the programs can be accomplished through the FPGA per se; data of users can also be stored in the FLASH chip; the application flexibility is improved; and the design cost is lowered. Simultaneously, the utility model also provides a program redundancy standby method, and the reliability of remote upgrade and the stability of the system are improved.

Description

FPGA Configuration Online circuit

Technical field

The utility model relates to a kind of FPGA application technology, especially a kind of FPGA Configuration Online circuit with remote upgrade ability.

Background technology

On-site programmable gate array FPGA (Field Programmable Gate Array), it is the product that further develops on the basis of programming devices such as PAL, GAL, EPLD.The use of FPGA is very flexible, and inner available resources is abundant, can produce different circuit functions with a slice FPGA by different designs.FPGA has obtained widespread use in various fields such as communication, data processing, network, instrument, Industry Control, LED, military affairs and Aero-Space, for example in the core technology of modern LED display is used, has just adopted fpga chip in a large number.

FPGA is based on the application technology of SRAM, and program can not be preserved, and needs when powering on FPGA to be configured.The configuration mode of FPGA generally has two classes: the one, directly it is configured by computing machine by the specific download cable, and program is kept among the read-write special-purpose EEPROM, so that FPGA by embedded configuration module, starts working after finishing configuration with active mode when off line powers on; The 2nd, adopt external microprocessor that it is configured by Passive Mode, this mode can change special-purpose EEPROM into SPI universal serial bus FLASH, except that the configuration of when powering on, finishing FPGA, also can utilize serial ports to be implemented in the sequence of threads upgrading, the new procedures code is write the FLASH zone of appointment, simultaneously also can be in non-program code area memory access user's data, the parameter of FLASH, this mode has brought dirigibility for the application of FPGA, and weak point is to have increased the Circuits System expense.

Summary of the invention

The purpose of this utility model provides a kind of FPGA Configuration Online circuit, the technical matters that solves is to allow FPGA except finishing the application configuration when powering on by active mode, can pass through FPGA itself again, finish remote upgrade to program, for improving the reliability of remote upgrade, a kind of program redundancy backup way has been proposed further simultaneously.

For solving the problems of the technologies described above, the utility model is by the following technical solutions: a kind of FPGA Configuration Online circuit, comprise fpga chip, described fpga chip connects data selector, described data selector power on power on after export different control signals to the FLASH chip, the data at different conditions transmit between FLASH and fpga chip to finish, and described fpga chip also connects telecommunication module and socket respectively.

The pin nCSO that initiatively programmes of the utility model fpga chip, ASDO, DCLK inserts three gate A0 of data selector respectively, B0, the input end of C0, three I/O pin IO_nCS of described fpga chip, IO_SO, IO_SCK inserts data selector A1 respectively, B1, the input end of C1, the CONF_DONE pin inserts the gating signal input end of data selector, the MSEL0 of described fpga chip, MSEL1 pin ground connection, the nSTATE pin meets power supply VCC by pull-up resistor R2, the nCONFIG pin meets power supply VCC by pull-up resistor R1, the cable of described fpga chip is downloaded pin gang socket, and the I/O pin connects the telecommunication module.

The signal output part Y0 of the utility model data selector connects the gating input end/CS of FLASH chip, signal output part Y1 connects serial input data end SI, signal output part Y2 connects input end of clock mouth SCK, and the serial data output terminal SO of described FLASH chip connects the active programming data input pin DATA0 and the I/O input pin IO_SI of fpga chip respectively.

Data selector of the present utility model is four alternative data selectors.

Data selector of the present utility model adopts the data selector of 74HC157.

FLASH chip of the present utility model adopts the nonvolatile flash memory chip with ISP universal serial bus.

FLASH chip of the present utility model adopts the W25X family chip.

The utility model compared with prior art, need not additionally to add under the situation of microprocessor, configuration in the time of both can finishing FPGA and power on by active mode, can finish remote upgrade by FPGA itself again to program, also can increase application flexibility, reduce design cost in non-program code area memory access user's data, the parameter of FLASH, utility model has proposed a kind of program redundancy backup way simultaneously, has improved the reliability of remote upgrade and the stability of system.

Description of drawings

Fig. 1 is a circuit diagram of the present utility model.

Embodiment

The utility model will be further described below in conjunction with drawings and Examples.

As shown in Figure 1, the utility model FPGA Configuration Online circuit comprises fpga chip, the nCSO of the pin of initiatively programming of described fpga chip, ASDO, the output terminal of DCLK respectively with the A0 of three alternative gates of data selector, B0, the input end of C0 links to each other, the data input pin DATA0 of fpga chip links to each other with the data output pin SO of FLASH chip, the CONF_DONE pin of fpga chip links to each other with the gating signal input end of data selector, the nSTATE pin of fpga chip meets power supply VCC by pull-up resistor R2, the nCONFIG pin of fpga chip meets power supply VCC by pull-up resistor R1, programming mode is selected signal MSEL0, MSEL1 ground connection, three I/O pin IO_nCS of described fpga chip, IO_SO, IO_SCK respectively with the A1 of three alternative gates of data selector, B1, the C1 input end links to each other, an I/O pin IO_SI input end links to each other with the data output pin SO of FLASH chip, the relevant pins that the cable of fpga chip is downloaded also links to each other with socket, part I/O pin links to each other with long-range communication interface, described FLASH CE input port/CS, serial input data port SI and input end of clock mouth SCK meet the output signal end Y0 of three alternative gates of data selector respectively, Y1 and Y2.

In the present embodiment, described FPGA is a field programmable gate array chip, and preference is the FPGA of ALTERA company; Described FLASH chip is the nonvolatile flash memory chip with ISP universal serial bus, and preference is the W25X family chip; Described data selector is four alternative data selectors, and preference is 74HC157; Described remote communication interface type is unrestricted, links to each other with FPGA with host computer respectively, bears the communication of fpga chip and host computer.

The major function of the utility model FPGA Configuration Online circuit is, send control signal by the dedicated pin of fpga chip when powering on, the program of solidifying in the FLASH chip is write in the fpga chip, after working on power, can receive host computer by fpga chip and pass the ROMPaq of coming, utilize the I/O pin of fpga chip that it is write in the FLASH chip.

Socket of the present utility model is that the cable of fpga chip is downloaded socket, and connected mode adopts common-mode, and main effect is to be finished configuration to fpga chip, debugging or program is write in the FLASH chip by computing machine.

Fpga chip mode select signal MSEL0 of the present utility model, MSEL1 ground connection, setting the fpga chip configuration mode that powers on is active mode, dedicated pin nCSO, ASDO, DCLK by fpga chip when promptly powering on send control signal, by the DATA0 pin program in the FLASH chip are write in the fpga chip.

In order to realize powering on by the dedicated pin configurator of fpga chip and I/O pin upgrading new procedures and the calling party data parameters of back that power on by fpga chip, the utility model utilizes the gating signal of the CONF_DONE signal of fpga chip as data selector, realize the exchange of dedicated pin and I/O pin control signal with this, the CONF_DONE signal of fpga chip is the indicator signal whether the fpga chip programming finishes, during the programming that powers on, be low, this moment, data selector was opened the input of 0 end, the special-purpose sheet of fpga chip select the Y0 of output signal nCSO by data selector output to the FLASH chip /CS sheet choosing end, special clock output signal DCLK outputs to the clock signal SCK input end of FLASH chip by the Y2 of data selector, exclusive data output signal ASDO outputs to the data SI input end of FLASH chip by the Y1 pin of data selector, the data output SO output code of control FLASH chip is to the exclusive data input port DATA0 of fpga chip, finish the configuration of fpga chip, fpga chip is during the programming that powers on, all I/O are ternary, and the IO_SI that is defined as I/O data input port does not have influence to input configuration pin DATA0; The programming that powers on finishes, the CONF_DONE signal uprises after fpga chip delays in work a period of time, this moment, data selector was opened the input of 1 end, the I/O sheet of fpga chip select the Y0 of output signal IO_nCS by data selector output to the FLASH chip /CS sheet choosing end, I/O clock output signal IO_SCK outputs to the clock signal SCK input end of FLASH chip by the Y2 of data selector, I/O data output signal IO_SO outputs to the data SI input end of FLASH chip by the Y2 of data selector, the data output SO of FLASH chip links the I/O data input port IO_SI of fpga chip, thereby finishes the online read-write control to the FLASH chip; Fpga chip can receive host computer by long-range communication module and pass the ROMPaq or the data parameters of coming, and it is write the BOOT program area or the data field of the appointment of FLASH chip.The FLASH chip capacity is enough big, except that the configurator that can write fpga chip, also can utilize the data of its complementary space read-write design, for example required pixel correction data, gamma curve table, controlled variable etc. in the LED display technique.

Simultaneously, for improving the reliability of remotely updating program, avoid the communication error code to cause the upgrading failure, the utility model has further proposed a kind of program redundancy backup way, in the FLASH chip, open up a memory block in addition, be specifically designed to fpga chip and write ROMPaq to the FLASH chip, only when communication errorless, ROMPaq transmits and verifies, and the new procedures code is swung to the BOOT program area in the FLASH chip again.

Claims

1. FPGA Configuration Online circuit, comprise fpga chip, it is characterized in that: described fpga chip connects data selector, described data selector power on power on after export different control signals to the FLASH chip, described fpga chip also connects telecommunication module and socket respectively.

2. FPGA Configuration Online circuit according to claim 1, it is characterized in that: the pin nCSO that initiatively programmes of described fpga chip, ASDO, DCLK inserts three gate A0 of data selector respectively, B0, the input end of C0, three I/O pin IO_nCS of described fpga chip, IO_SO, IO_SCK inserts data selector A1 respectively, B1, the input end of C1, the CONF_DONE pin inserts the gating signal input end of data selector, the MSEL0 of described fpga chip, MSEL1 ground connection, power supply VCC connects the nCONFIG pin of fpga chip by resistance R 1, resistance R 2 connects the nSTATE pin of fpga chip, the cable of described fpga chip is downloaded pin gang socket, and the I/O pin connects the telecommunication module.

3. FPGA Configuration Online circuit according to claim 2, it is characterized in that: the signal output part Y0 of described data selector connects the gating input end/CS of FLASH chip, signal output part Y1 connects serial input data end SI, signal output part Y2 connects input end of clock mouth SCK, and the serial data output terminal SO of described FLASH chip connects the active programming data input pin DATA0 and the I/O input pin IO_SI of fpga chip respectively.

4. FPGA Configuration Online circuit according to claim 3 is characterized in that: described data selector is four alternative data selectors.

5. FPGA Configuration Online circuit according to claim 4 is characterized in that: described data selector adopts the data selector of 74HC157.

6. FPGA Configuration Online circuit according to claim 5 is characterized in that: described FLASH chip adopts the nonvolatile flash memory chip with ISP universal serial bus.

7. FPGA Configuration Online circuit according to claim 6 is characterized in that: described FLASH chip adopts the W25X family chip.