CN201364577Y - Program execution safety enhancement module based on hardware embedded system - Google Patents

Abstract

A hardware-based embedded system program execution safety enhancement module is composed of a memory group and an information analysis and comparison logic circuit. The memory group is composed of 3 static random access memories, and its main function is to store the monitoring model and stack mapping storage; the information analysis and comparison logic circuit is the main control part of the module, which receives the program counter signal output by the external processor , calls the information of the memory group, and judges the legitimacy of the real-time operation control flow behavior of the embedded processor; it is composed of three functional circuits: information calling, monitoring comparison, and stack mapping. The data signal port, the address signal port and the read-write control signal port between the memory group and the information analysis and comparison logic circuit are interconnected. This module judges the legitimacy of its execution behavior by analyzing the processor execution path information, thereby preventing any execution behavior that is judged to be illegal. It enhances the security of system programs.

Description

A Hardware-Based Embedded System Program Execution Security Enhancement Module

(1) Technical field

The utility model relates to a module for enhancing program execution safety, in particular to a hardware-based embedded system program execution safety enhancement module, which utilizes a hardware-assisted mode to monitor program execution and prevent malicious execution behaviors caused by software attacks occurs, preventing the execution of malicious code. The invention belongs to the technical field of embedded system security.

(2) Background technology

Embedded systems are playing an increasingly important role in today's society. From consumer electronics products to aerospace and military products, embedded systems are getting closer and closer to us. However, while the application is more extensive, the operational safety of embedded systems has become more important. But its resource-constrained nature makes the related security protection design more difficult.

The usual software attacks use program vulnerabilities. In order to enhance the security of embedded system program execution, there are usually three kinds of technologies that can be used. They are: software-based static analysis technology, software-based real-time protection technology and hardware-based real-time protection technology. protection technology. The first technology uses offline code analysis to detect and repair related program vulnerabilities to prevent attackers from exploiting these vulnerabilities during program execution; the second technology monitors the real-time execution of the program by adding monitoring code to the program through software , to prevent wrong program execution behavior caused by attacks; the last one is to ensure the correctness of program execution behavior from the perspective of hardware, and protect the program execution process through stack protection and security coprocessors. The utility model belongs to the last technology, and uses a monitoring hardware module running in parallel with the processor to realize real-time monitoring of the execution process of the processor and enhance its safety.

(3) Contents of the invention

1. Purpose: The purpose of this utility model is to provide a hardware-based embedded system program execution security enhancement module, which is a real-time monitoring module for the execution state of the processor. This module involves a hardware for monitoring, which runs in parallel with the processor, and determines the legality of its execution behavior by analyzing the processor execution path information, thereby preventing any execution behavior that is judged to be illegal.

2. Technical solution: a hardware-based embedded system program execution safety enhancement module, which is composed of a memory group and an information analysis and comparison logic circuit.

The memory group is composed of three SRAMs SRAM1, SRAM2 and SRAM3 (using existing devices), and its main function is to store monitoring models and stack map storage. The monitoring model describes the scope of the legal control flow behavior of the program, which is obtained through offline program analysis, including function information and basic block information. Among the three SRAMs, SRAM1 is used to store function information in the monitor model, SRAM2 is used to store basic block information in the monitor model, and SRAM3 is used to store stack mapping information. Using the information in the memory group, a definite description of the legal control flow behavior of the program can be obtained.

The information analysis and comparison logic circuit is the main control part of the module, it receives the program counter signal output by the external processor, calls the information of the memory group, and judges the legality of the real-time operation control flow behavior of the embedded processor, if When an illegal control flow behavior is found, the circuit sends an interrupt control signal to the processor-related interrupt interface to trigger the corresponding interrupt emergency response. This part is mainly composed of 3 functional circuits, which are: 1, information call; 2, monitoring comparison; 3, stack mapping. The information call completes the data reading from the memory, and after each control flow conversion occurs, it will start to calculate the information address in the SRAM corresponding to the possible target of the next control flow jump. The monitoring comparison is to calculate the possible target address of the next program control flow jump by analyzing and calculating the data information (including function information and basic block information) output by the memory, that is, the legal execution path, and through processing The execution control flow information (program counter PC) of the device is used to determine the control flow transition. The stack map simulates the running process of the stack in the processor, saves the return address of the function call in real time, and can verify the return address when the function returns.

The data signal port, the address signal port and the read-write control signal port between the memory group and the information analysis and comparison logic circuit are interconnected. The information analysis and comparison logic circuit outputs the read-write control signal and the address signal to the memory group to control the corresponding address of the memory group for reading and writing. The data signal is a bidirectional signal. For memory banks and information analysis and comparison logic circuits, it can be an input signal or an output signal, which depends on the type of read and write operations.

The utility model can detect any program execution behavior that violates the legal definition. This real-time monitoring module mainly has the following advantages:

(1) Because the hardware monitoring module involved in the utility model adopts the design based on program control flow, it has a good monitoring effect on any kind of attack.

(2) The hardware monitoring module involved in the utility model can realize real-time detection within one clock cycle through hardware optimization, which greatly improves the detection efficiency.

(3) The hardware monitoring module involved in the utility model is independent, and the monitoring module itself has insensitivity to software attacks.

(4) The monitoring module involved in the utility model occupies less hardware resources, and reduces monitoring cost while improving reliability.

(5) The hardware monitoring module involved in the utility model does not need to change the development program of the original embedded system, only needs to analyze the program offline, and store the monitoring model obtained by the analysis into the memory of the monitoring hardware without modifying the hardware logic.

(6) The hardware monitoring module involved in the utility model has good scalability and can adapt to different types of embedded systems.

(4) Description of drawings

Fig. 1 is a schematic diagram of the relationship between the utility model module and the traditional embedded system

Fig. 2 is a schematic diagram of the module structure of the present invention

Fig. 3 is a schematic diagram of the application development process of the system possessing the module of the present invention

The symbols in the figure are explained as follows:

SRAM1 static memory 1; SRAM2 static memory 2; SRAM3 static memory 3.

(5) Specific implementation methods

See Fig. 1, Fig. 2, shown in Fig. 3, its specific implementation is as follows:

As shown in Figure 2, it is a schematic structural diagram of a hardware-based embedded system program execution security enhancement module. It can be seen from the figure that the module consists of a memory bank (shown in the right part of the box) and an information analysis and comparison logic circuit (shown in the box on the left part). The module receives control flow information and outputs interrupt control signals. This module needs to complete the real-time status monitoring of program execution and the generation of corresponding monitoring feedback signals.

The memory group includes three SRAMs: SRAM1, SRAM2 and SRAM3, and of course other types of memories (such as dynamic memory DRAM, etc.) can also be used instead. SRAM1 and SRAM2 in the three memories are used to store function information and basic block information in the supervisory model. The monitoring model is obtained through off-line program control flow analysis by software, including function information and basic block information. The function of the monitoring model is to describe the legal control flow execution path of program operation, where the function information includes the first address of the function and the index of the corresponding basic block; the basic block information includes the basic block type, the first address, the target index and the corresponding function index . Using the function information and basic block information stored in SRAM1 and SRAM2, the legal control flow execution path of the statically analyzed program can be described. SRAM3 is used to store stack mapping information, which is dynamically updated in real time. It simulates a processor stack storage function. Using this stack mapping information, the function return address can be deduced, thereby ensuring the legal control flow of the entire program. The path is fully described. The three SRAMs have no interconnection interface.

The information analysis and comparison logic circuit receives the program counter signal output by the external embedded processor, calls the information of the memory group, and monitors the validity of the real-time operation control flow behavior of the embedded processor. The circuit is mainly composed of three functional parts, namely: information calling, monitoring comparison and stack mapping control. The information call completes the data reading of the memory, and after each control flow conversion, it will start to calculate the information address in the SRAM corresponding to the possible target of the next control flow jump. Monitoring comparison is to calculate the possible target address of the next program control flow jump by analyzing and calculating the data information (including function information and basic block information) output by the memory, that is, the legal execution path, and through the execution of the processor The control flow information (program counter PC) determines the control flow conversion. If a conversion occurs, the actual jump address is compared with the previously calculated address. If they are inconsistent, a feedback control signal is generated to interrupt the operation of the processor and let It executes the corresponding security response mechanism. The stack map will simulate the running process of the stack in the processor. When a function call occurs during program execution, the current function information index and basic block information index will be pushed into the stack, that is, after the stack value is stored in SRAM, then the SRAM address plus one. If the current basic block jump type is a function return, the data of the current address in the stack mapping SRAM2 is pushed out, and the address is decremented by one. In this way, the return address of the function is saved, and the return address can be verified when the function returns. If the return address is damaged due to a stack overflow attack during the program, the module can detect it well.

The connection signals of the memory group and the information analysis and comparison logic circuit include data signals, address signals and read-write control signals. The data signal is a bidirectional signal. When the memory write operation is performed, the data signal direction is from the information analysis and comparison logic circuit to the memory. When the memory read operation is performed, the signal direction is just opposite. In addition, the signal directions of the address signal and the read/write control signal are sent from the information analysis and comparison logic circuit to the memory.

In practical application, the module needs to be connected with the embedded processor. As shown in Figure 1, the traditional embedded processor and the security enhancement module are connected by hard wires, and the execution flow information and interrupt control information are exchanged. run in parallel during real-time runtime. For the embedded system using this module, its corresponding development process is shown in Figure 3: the upper left part is consistent with the general embedded system software development process, and the difference is only in the upper right part, which requires the target code and binary The code performs program analysis, extracts information and generates a monitoring model describing the legal control flow behavior of the program, and then stores the monitoring model in the corresponding monitoring memory. When the binary code program and the monitoring model have been saved, the system can be run. The processor and the monitoring hardware will run in parallel. The monitoring hardware receives the execution information of the processor and verifies its control flow. It can be seen from the entire development process that the system development process does not change the traditional development process related to the processor, but only adds some additional processes related to monitoring, which is of great benefit to its application, because its It means that it is inherited to the previous software, that is, the original software needs to be transplanted into this system without changing the original design.

Claims (1)

1. A hardware-based embedded system program execution security enhancement module is characterized in that: the module is composed of a memory bank and an information analysis and comparison logic circuit; Described memory bank is made up of 3 SRAMs SRAM1, SRAM2 and SRAM3, and SRAM1 stores the function information in the monitoring model, SRAM2 stores the basic block information in the monitoring model, and SRAM3 stores stack mapping information; 3 static memories are not interconnected Interface; The information analysis and comparison logic circuit is the main control part of the module, it receives the program counter signal output by the external processor, and it is composed of three functional circuits: information call, monitoring comparison and stack mapping; The data signal port, address signal port and read-write control signal port between the memory group and the information analysis and comparison logic circuit are interconnected, and the information analysis and comparison logic circuit outputs the read-write control signal and address signal to the memory group to control the memory group The corresponding address is used for read and write control; the data signal is a bidirectional signal, which can be an input signal or an output signal for the memory bank and information analysis and comparison logic circuit.

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