CN201352879Y - Control circuit for inverter using pulse width modulation dimming - Google Patents

Abstract

A control circuit of an inverter using PWM dimming comprises a low-frequency timing capacitor, a low-frequency oscillator, a low-frequency PWM comparator, a feedback control circuit and an alternating current signal generator, wherein the output end of the low-frequency oscillator is coupled to the input ends of the low-frequency timing capacitor and the low-frequency PWM comparator, and the output end of the low-frequency PWM comparator is coupled to the feedback control circuit. The alternating current signal generator generates alternating current with proper size and frequency to charge the low-frequency timing capacitor, the charging current of the low-frequency timing capacitor is original direct current plus alternating current, and low-frequency slope voltage at the output end of the low-frequency oscillator generates disturbance according to the size of the alternating current, so that a low-frequency PWM signal at the output end of the low-frequency PWM comparator generates disturbance. The disturbed low-frequency PWM signal expands the signal energy of the inverter to a wider frequency range through a feedback control circuit so as to improve the electromagnetic interference generated at the moment of conversion of the inverter during the enabling and disabling periods of the low-frequency PWM signal.

Description

Control circuit of an inverter dimming using pulse width modulation

technical field

The utility model relates to a control circuit of an inverter, in particular to a control circuit of an inverter that uses pulse width modulation (Pulse Width Modulation, PWM for short) to adjust light.

Background technique

Figure 1A is a block diagram of a traditional cold cathode fluorescent lamp (Cold Cathode Fluorescent Lamp, referred to as CCFL) power system; please refer to Figure 1A. 11 to filter out the noise, and then rectified by the bridge rectifier 12 to become a DC pulsating signal. In order to comply with harmonic regulations, the DC pulsation signal of the power system with input power greater than 75W must pass through a power factor corrector (Power Factor Corrector, referred to as PFC) 13 to correct the current harmonic distortion and become a stable DC voltage Vbus with a typical value of 400Vdc To supply power to the standby power converter 14 and the main power converter 15 . The standby power converter 14 changes the DC voltage Vbus into a power supply with a typical value of 5Vdc, which supplies power to the microcontroller (Micro Controller Unit, MCU) of the main board (main board) in standby mode to maintain the work of the remote control receiver, and Turn off the PFC 13 and the main power converter 15 to reduce standby power consumption. The main power converter 15 converts the DC voltage Vbus into a typical value of 12Vdc, 14Vdc or other voltages for powering audio, video, control modules or other modules, and a typical value of 24Vdc for powering the inverter 16 . The inverter 16 changes the typical 24Vdc power provided by the main power converter 15 into an AC voltage Vlamp of a typical 1800Vac to start the CCFL, and dropping from 1800Vac to 800Vac after startup is enough to make the CCFL work stably.

In order to reduce manufacturing costs and improve conversion efficiency, a CCFL power supply system with LIPS architecture was developed later, where LIPS is the abbreviation of Lcd Integrated Power Supply. FIG. 1B is a block diagram of a CCFL power supply system with an existing LIPS architecture; please refer to FIG. 1A and FIG. 1B at the same time. Unlike the traditional power supply system 1, the inverter 16 is powered by the main power converter 15, and the LIPS power supply system 2 The inverter 26 of the inverter 26 is directly powered by the DC voltage Vbus with a typical value of 400Vdc provided by the PFC 13, so the electric energy for driving the CCFL is reduced by one level of energy conversion, that is, the loss of one level of conversion efficiency is saved, and the main power converter 25 can be reduced. Design power and structure complexity, not only improve heat dissipation and reduce manufacturing costs. However, since the LIPS power system 2 lacks the voltage stabilizing effect of the main power converter 25, its stability is relatively insufficient, especially when the inverter 26 uses pulse width modulation (PWM) for dimming, the DC provided by the PFC 13 Excessive transient AC changes may occur on the voltage Vbus.

FIG. 2 is a waveform diagram of the input and output signals of the inverter 26 of the LIPS power system 2 shown in FIG. 1B; please refer to FIG. 1B and FIG. Signal Vlpwm. PWM dimming is currently the most common dimming method because of its wide dimming range, good dimming linearity and easy circuit implementation. Each cycle T of the low frequency PWM signal Vlpwm includes an enable period T_ON and a disable period T_OFF. During the enable period T_ON, the inverter 26 works normally, and it generates an AC voltage Vlamp with a frequency of fhosc to drive the CCFL to emit light (that is, brighten); and during the disable period T_OFF, the inverter 26 does not work, and the AC voltage Vlamp is zero, unable to drive CCFL to emit light (that is, to dim). The frequency flosc of the low-frequency PWM signal Vlpwm is usually designed to be higher than 100Hz. Under the influence of temporary storage of human vision, it is impossible to see the CCFL brighten and then darken. (that is, adjusting the ratio of T_ON during the enabling period and T_OFF during the disabling period) can achieve the purpose of dimming. Since the LIPS power supply system 2 lacks the voltage stabilizing effect of the main power converter 25, when the inverter 26 uses PWM dimming, when the low-frequency PWM signal Vlpwm is enabled during T_ON and during the disabled period T_OFF, both transition instants, the inverter When the switch 26 is loaded or unloaded instantaneously, the DC voltage Vbus provided by the PFC 13 will experience excessive transient AC changes. The excessive transient AC change of the DC voltage Vbus is likely to map the frequency of the AC change through the inductor in the PFC 13 , and produce an EMI impact on the low frequency spectrum of the fundamental frequency of the frequency band.

Contents of the invention

The purpose of this utility model is to propose a control circuit of an inverter using pulse width modulation dimming to improve the electromagnetic interference generated by the inverter at the moment of switching between the enable period and the disable period of the low-frequency pulse width modulation signal. .

In order to achieve the above purpose and other purposes, the utility model proposes a control circuit of an inverter using pulse width modulation dimming, which includes a low frequency timing circuit, a low frequency oscillator, a low frequency pulse width modulation comparator, a feedback control circuit and an AC Signal generator. The low-frequency timing circuit includes a low-frequency timing resistor and a low-frequency timing capacitor. The low-frequency timing resistor determines the magnitude of a direct current and the direct current is used to charge the low-frequency timing capacitor. The low-frequency timing capacitor has a first end and a second end, and the second end is coupled to the ground potential. The low-frequency oscillator has an output terminal coupled to the low-frequency timing resistor and the first terminal of the low-frequency timing capacitor. The low-frequency oscillator controls the low-frequency timing capacitor to be repeatedly charged and discharged to generate a low-frequency slope voltage at the first terminal of the low-frequency timing capacitor. The low-frequency PWM comparator has a first input terminal, a second input terminal and an output terminal, the first input terminal of the low-frequency PWM comparator receives a DC dimming signal, and the second input terminal of the low-frequency PWM comparator is coupled to the low-frequency The first end of the timing capacitor generates a low frequency pulse width modulation signal at the output end of the low frequency pulse width modulation comparator, wherein each period of the low frequency pulse width modulation signal includes an enabling period and a disabling period. The feedback control circuit has an enabling terminal and an output terminal. The enabling terminal of the feedback control circuit is coupled to the output terminal of the low-frequency pulse width modulation comparator. During the enabling period, a driving signal is generated at the output terminal of the feedback control circuit. The output terminal of the circuit does not generate a driving signal, wherein the driving signal is used to drive switching of the switching circuit in the inverter. The AC signal generator has an output end coupled to the first end of the low-frequency timing capacitor, and an AC current is provided at the output end of the AC signal generator to charge the low-frequency timing capacitor.

The utility model uses an AC current of appropriate size and frequency to charge the low-frequency timing capacitor, so that the charging current of the low-frequency timing capacitor is the original DC current plus the AC current, so that the low-frequency slope voltage generated at the output terminal of the low-frequency oscillator will be based on this The magnitude of the AC current produces disturbances, which in turn cause disturbances to the low-frequency PWM signal, and extend the signal energy of the inverter to a relatively wide frequency range, thus improving the enablement of the inverter in the low-frequency PWM signal The electromagnetic interference generated at the moment of switching between the two during the period and the disable period.

In order to make the above and other objectives, features and advantages of the present invention more comprehensible, preferred embodiments will be described in detail below together with the accompanying drawings.

Description of drawings

FIG. 1A is a block diagram of a conventional CCFL power supply system;

FIG. 1B is a block diagram of a CCFL power supply system with an existing LIPS architecture;

FIG. 2 is a waveform diagram of the input and output signals of the inverter of the LIPS power system shown in FIG. 1B;

3 is a block diagram of an inverter using PWM dimming according to an embodiment of the present invention;

Fig. 4 is the circuit diagram of a specific embodiment of the control circuit shown in Fig. 3;

Fig. 5 is a circuit diagram of another specific embodiment of the control circuit shown in Fig. 3;

Fig. 6 is a circuit diagram of another specific embodiment of the control circuit shown in Fig. 3;

FIG. 7 is a circuit diagram of a specific embodiment of the AC signal generator shown in FIG. 4 .

Explanation of reference signs:

1, 2-CCFL power supply system; 11-electromagnetic interference (EMI) filter; 12-bridge rectifier; 13-power factor corrector (PFC); 14-standby power converter; 15,25-main power converter; 16, 26-inverter; 30-inverter; 31-switching circuit; 32-transformer; 33-resonant circuit; 34-voltage sensor; 35-current sensor; 36, 46, 56, 66-control circuit; 461 , 661-low frequency oscillator; 462, 662-low frequency timing circuit; 463-low frequency PWM comparator; 464-feedback control circuit; 4641-error amplifier; 4642-high frequency oscillator; 4643-high frequency timing circuit; 4644-high Frequency PWM comparator; 4645-control logic circuit; 4646-output drive circuit; 465, 765-AC signal generator; 466-comparator; 467, 567-switch; 7651-Wayne bridge oscillator;

Vbus-DC voltage; Vlamp-AC voltage (or CCFL voltage); Vvsen-voltage sensing signal; Visen-current sensing signal; Vdrv-driving signal; Vdim-dimming signal; Vlpwm-low frequency PWM signal; Vhpwm-high frequency PWM signal; Vlst-low frequency ramp voltage; Vhst-high frequency ramp voltage; Vref-reference voltage; Vea-error voltage; Vp1-first set voltage; Vdd-DC power supply; Vgnd-ground potential; Ilamp-CCFL current; Ic -DC current; Ia-AC current; R1-low frequency timing resistor; R2-high frequency timing resistor; R3～R7-resistor; C1-low frequency timing capacitor; C2-high frequency timing capacitor; C3～C6-capacitor; D1, D2-diode; T-low frequency PWM signal period; T_ON-low frequency PWM signal enable period; T_OFF-low frequency PWM signal disable period; flosc-low frequency PWM signal frequency; fhosc-high frequency PWM signal frequency.

Detailed ways

FIG. 3 is a block diagram of an inverter using PWM dimming according to an embodiment of the present invention; please refer to FIG. 3 , the inverter 30 adopts the structure of the LIPS power supply system 2 shown in FIG. 30 is directly powered by the DC voltage Vbus with a typical value of 400Vdc provided by the PFC, and outputs the AC voltage Vlamp to drive the CCFL. In this embodiment, the inverter 30 includes a switch circuit 31 , a transformer 32 , a resonant circuit 33 , a voltage sensor 34 , a current sensor 35 and a control circuit 36 . The switch circuit 31 is, for example, a full-bridge, half-bridge switch circuit or other switch circuits for changing the DC voltage Vbus into a square-wave AC voltage. The transformer 32 is used to step up the AC voltage in the form of a square wave. The resonant circuit 33 is used to filter the boosted square-wave AC voltage into a sine-wave AC voltage Vlamp, and provide a resonant voltage and current to enable the switch circuit 31 to have zero-voltage/zero-current switching characteristics. The voltage sensor 34 and the current sensor 35 respectively detect the voltage Vlamp and the current Ilamp of the CCFL to output a voltage sensing signal Vvsen and a current sensing signal Visen. The control circuit 36 uses the PWM dimming method to adjust the brightness of the CCFL according to the dimming signal Vdim, and outputs the driving signal Vdrv according to the current sensing signal Visen to feedback the switching of the switching circuit 31 to stabilize the brightness of the CCFL. protect the circuit. Since PWM dimming can be divided into external PWM dimming and internal PWM dimming, if the inverter 30 uses external PWM dimming, the dimming signal Vdim is a low-frequency PWM signal; and if the inverter 30 uses internal PWM dimming, then The dimming signal Vdim is a DC signal, and the control circuit 36 then generates a low-frequency PWM signal based on the DC signal. The internal PWM dimming is often used because it is relatively simple in design.

FIG. 4 is a circuit diagram of a specific embodiment of the control circuit 36 shown in FIG. 3 , wherein CMP is an abbreviation of a comparator (CoMParator), and EA is an abbreviation of an error amplifier (Error Amplifier). Please refer to FIG. 4 , the control circuit 46 includes a low frequency oscillator 461 , a low frequency timing circuit 462 , a low frequency PWM comparator 463 , a feedback control circuit 464 and an AC signal generator 465 . The low-frequency timing circuit 462 includes a low-frequency timing resistor R1 and a low-frequency timing capacitor C1. In this embodiment, the first end of the low-frequency timing resistor R1 is coupled to the DC power supply Vdd, and the second end of the low-frequency timing resistor R1 is coupled to the low-frequency oscillator. The output end of the device 461 and the first end of the low frequency timing capacitor C1, the second end of the low frequency timing capacitor C1 is coupled to the ground potential Vgnd. The DC power supply Vdd generates a DC current Ic through the low-frequency timing resistor R1 to charge the low-frequency timing capacitor C1, and the low-frequency timing resistor R1 will determine the magnitude of the DC current Ic. The low-frequency oscillator 461 controls the voltage on its output terminal or the first terminal of the low-frequency timing capacitor C1 to stop charging and start discharging when it is charged to the first set voltage Vp1, and stop discharging and start discharging when it is discharged to the second set voltage Vp2. Start charging. Therefore, the voltage at the output terminal of the low frequency oscillator 461 or the first terminal of the low frequency timing capacitor C1 will rise and fall repeatedly to form a low frequency slope voltage Vlst whose waveform is a triangular wave or a sawtooth wave, and whose peak voltage is the first set voltage Vp1, The valley voltage is the second preset voltage Vp2, whose frequency is flosc and is proportional to 1/(R1×C1).

In this embodiment, the inverter 30 uses internal PWM dimming, so the dimming signal Vdim is a DC signal. The first input terminal of the low-frequency PWM comparator 463 receives the DC dimming signal Vdim, and its second input terminal is coupled to the first terminal of the low-frequency timing capacitor C1 to receive the low-frequency ramp voltage Vlst. By comparing the DC dimming signal Vdim and the low-frequency ramp voltage Vlst And generate low-frequency PWM signal Vlpwm at its output terminal. An embodiment of the low-frequency PWM signal Vlpwm is shown in FIG. 2 , and each cycle T (=1/flosc) includes an enable period T_ON and a disable period T_OFF. The enable terminal of the feedback control circuit 464 is coupled to the output terminal of the low frequency PWM comparator 463 to receive the low frequency PWM signal Vlpwm. During the enable period T_ON of the low-frequency PWM signal Vlpwm, the output terminal of the feedback control circuit 464 generates a drive signal Vdrv to drive the switch circuit 31, so that the inverter 30 works normally and generates an AC voltage Vlamp with a frequency of fhosc to drive the CCFL to emit light; and During the disabled period T_OFF of the low-frequency PWM signal Vlpwm, no drive signal Vdrv is generated at the output terminal of the feedback control circuit 464, that is, the drive signal Vdrv is zero and cannot drive the switch circuit 31, so that the inverter 30 does not work. At this time, the AC voltage Vlamp If it is zero, the CCFL cannot be driven to emit light (that is, to dim). The output terminal of the AC signal generator 465 is coupled to the first terminal of the low-frequency timing capacitor C1 to provide an AC current Ia at the output terminal of the AC signal generator 465 . Therefore, the charging current of the low-frequency timing capacitor C1 is the original DC current Ic plus the AC current Ia, so that the low-frequency slope voltage Vlst generated at the output terminal of the low-frequency oscillator 461 or the first terminal of the low-frequency timing capacitor C1 will be based on the magnitude of the AC current Ia A disturbance is generated, causing the low-frequency PWM signal Vlpwm generated at the output terminal of the low-frequency PWM comparator 463 to produce a disturbance. The disturbed low-frequency PWM signal Vlpwm expands the signal energy of the inverter 30 to a relatively wide frequency range through the feedback control circuit 464, thus improving the T_ON and disabled periods of the inverter 30 during the enable period of the low-frequency PWM signal Vlpwm. T_OFF The electromagnetic interference generated at the moment of switching between the two.

The feedback control circuit 464 includes an error amplifier 4641 , a high frequency oscillator 4642 , a high frequency timing circuit 4643 , a high frequency PWM comparator 4644 , a control logic circuit 4645 and an output driving circuit 4646 . The enabling terminal of the error amplifier 4641 (that is, the enabling terminal of the feedback control circuit 464) receives the low-frequency PWM signal Vlpwm. During the enabling period T_ON, the error amplifier 4641 works normally to generate the drive signal Vdrv; while during the disabling period T_OFF, the error amplifier 4641 The driving signal Vdrv cannot be generated without working or the driving signal Vdrv is zero. When the error amplifier 4641 works normally, the error amplifier 4641 generates an error voltage Vea at its output terminal by comparing the current feedback signal Visen with the reference voltage Vref. The high-frequency oscillator 4642 generates the slope voltage in the same way as the low-frequency oscillator 461, that is, the output terminal of the high-frequency oscillator 4642 is coupled to the high-frequency timing circuit 4643 (which includes a high-frequency timing resistor R2 and a high-frequency timing capacitor C2), A high-frequency slope voltage Vhst is generated at its output terminal, and its frequency is fhosc and is proportional to 1/(R2×C2). Next, the high-frequency PWM comparator 4644 generates a high-frequency PWM signal Vhpwm at its output terminal by comparing the high-frequency slope voltage Vhst and the error voltage Vea, and the control logic circuit 4645 generates a driving signal Vdrv according to the high-frequency PWM signal Vhpwm to control the switching circuit 31. switch, so that as shown in FIG. 2 , during the enable period T_ON generates an AC voltage Vlamp with a frequency fhosc. Generally, the driving signal Vdrv is enhanced by the output driving circuit 4646 with architectures such as open drain, open collector or totem pole. In addition, the low-frequency oscillator 461, the low-frequency PWM comparator 463, the error amplifier 4641, the high-frequency oscillator 4642, the high-frequency PWM comparator 4644, the control logic circuit 4645 and the output driving circuit 4646 can be combined and packaged into an integrated circuit, such as OZ9938, in order to simplify the design.

In this embodiment, the control circuit 46 further includes a comparator 466 and a switch 467 . The first input terminal of the comparator 466 receives the DC dimming signal Vdim, and the second input terminal receives the first set voltage Vp1, which is the peak voltage of the low frequency ramp voltage Vlst. The switch 467 is, for example, a PNP bipolar transistor, its first terminal (or emitter terminal) is coupled to the output terminal of the AC signal generator 465, and its second terminal (or collector terminal) is coupled to the first terminal of the low-frequency timing capacitor C1 , the control terminal (or base terminal) of which is coupled to the output terminal of the comparator 466 . When the DC dimming signal Vdim is greater than or equal to the first set voltage Vp1, that is, the DC dimming signal Vdim is greater than or equal to the peak voltage of the low-frequency slope voltage Vlst, at this time the enabling period T_ON of the low-frequency PWM signal Vlpwm is the maximum (that is, T_ON = T) there is no T_OFF during the period of disabling, and there is no problem of electromagnetic interference generated at the moment of switching between T_ON during the period of enabling and T_OFF during the period of disabling. Therefore, the output signal of the output terminal of the comparator 466 can be used to control the switch 467 to be disconnected in order to save energy. , so that the output terminal of the AC signal generator 465 and the first terminal of the low-frequency timing capacitor C1 are disconnected. Conversely, when the DC dimming signal Vdim is lower than the first set voltage Vp1, the output signal of the output terminal of the comparator 466 controls the switch 467 to be turned on, so that the output terminal of the AC signal generator 465 is coupled to the first terminal of the low frequency timing capacitor C1. In addition, if the AC signal generator 465 is not designed to prevent signal backflow, a diode D1 must be provided between the switch 467 and the low-frequency timing capacitor C1 to provide a one-way conduction function. As shown in Figure 4, the anode of the diode D1 is coupled to the switch The second end of 467, the cathode end of the diode D1 is coupled to the first end of the low-frequency timing capacitor C1; or, a diode (not shown) is arranged between the switch 467 and the AC signal generator 465, and the anode end of the diode is coupled to the AC signal generator The output end of the switch 465, and the cathode end of the diode is coupled to the first end of the switch 467.

Fig. 5 is a circuit diagram of another specific embodiment of the control circuit 36 shown in Fig. 3; please refer to Fig. 4 and Fig. 5 simultaneously, the difference between the control circuit 56 and the control circuit 46 is only to control whether the AC signal Ia is provided to the low-frequency timing capacitor Implementation of C1. The control circuit 56 uses the comparator 466 to compare the DC dimming signal Vdim and the first setting voltage Vp1 so as to output a control signal to control the switch 567 . The switch 567 is, for example, an NPN bipolar transistor, its first terminal (or collector terminal) is coupled to the output terminal of the AC signal generator 465 and the anode terminal of the diode D2, and its second terminal (or emitter terminal) is coupled to the ground potential Vgnd, its control terminal (or base terminal) is coupled to the output terminal of the comparator 466 . When the DC dimming signal Vdim is greater than or equal to the first set voltage Vp1, the output signal at the output terminal of the comparator 466 controls the switch 567 to turn on, so that the anode of the diode D2 is coupled to the ground potential Vgnd, so the diode D2 is cut off and the AC signal The output terminal of the generator 465 is disconnected from the first terminal of the low frequency timing capacitor C1. Conversely, when the DC dimming signal Vdim is lower than the first set voltage Vp1, the output signal of the output terminal of the comparator 466 controls the switch 567 to turn off, and the output terminal of the AC signal generator 465 is of course coupled to the first terminal of the low frequency timing capacitor C1.

6 is a circuit diagram of another specific embodiment of the control circuit 36 shown in FIG. 3; please refer to FIG. 4 and FIG. The output terminal of the low frequency oscillator 661 of the control circuit 66 has a first output terminal and a second output terminal. The low frequency timing circuit 662 of the control circuit 66 includes a low frequency timing resistor R1 and a low frequency timing capacitor C1, the first end of the low frequency timing resistor R1 is coupled to the first output end of the low frequency oscillator 661, and the first end of the low frequency timing capacitor C1 is coupled to the low frequency The second output end of the oscillator 661 , the low frequency timing resistor R1 and the second end of the low frequency timing capacitor C1 are all coupled to the ground potential Vgnd. The low frequency oscillator 661 provides a DC current Ic to charge the low frequency timing capacitor C1, and the low frequency timing resistor R1 determines the magnitude of the DC current Ic. At this time, the second input terminal of the low frequency PWM comparator 463 and the output terminal of the AC signal generator 465 are coupled to the second output terminal of the low frequency oscillator 661 and the first terminal of the low frequency timing capacitor C1, and are not coupled to the first terminal of the low frequency oscillator 661. output and low frequency timing resistor R1.

FIG. 7 is a circuit diagram of a specific embodiment of the AC signal generator 465 shown in FIG. 4; please refer to FIG. 7, the AC signal generator 765 includes a Wien bridge oscillator (Wien bridge oscillator) 7651, wherein the Wien bridge oscillator The oscillator 7651 is composed of an operational amplifier OPA, resistors R4-R7 and capacitors C3-C6. The output terminal of the Wayne bridge oscillator 7651 is coupled to the resistor R3, so the sinusoidal voltage signal output from the output terminal generates an AC current Ia through the resistor R3.

In summary, the control circuit of the inverter using PWM dimming of the present invention uses an AC signal generator to generate an AC current of appropriate size and frequency to charge the low-frequency timing capacitor, so the charging current of the low-frequency timing capacitor is the original DC The current is added to the alternating current, and the low-frequency slope voltage generated at the output terminal of the low-frequency oscillator will generate disturbance according to the magnitude of the alternating current, so that the low-frequency PWM signal generated at the output terminal of the low-frequency PWM comparator will be disturbed. The disturbed low-frequency PWM signal expands the signal energy of the inverter to a relatively wide frequency range through the feedback control circuit, so it can improve the inverter's conversion instant during the enable period and the disable period of the low-frequency PWM signal. electromagnetic interference.

The above specific implementations are only preferred embodiments of the present utility model, which are illustrative rather than restrictive to the present utility model. Those skilled in the art may make changes, modifications or even equivalents without departing from the spirit and scope of the present utility model, and these changes will all fall within the protection scope of the claims of the present utility model.

Claims (7)

1. a control circuit that uses the inverter of impulse width modulation and light adjusting is characterized in that, comprising:

One low frequency timing circuit, comprise a low frequency timing resistor device and a low frequency time capacitor, low frequency timing resistor device determines the size of a direct current electric current, direct current charges to the low frequency time capacitor, the low frequency time capacitor has one first end and one second end, and low frequency time capacitor second end is coupled to an earthing potential;

One low-frequency oscillator, has an output, the low-frequency oscillator output is coupled to low frequency timing resistor device and low frequency time capacitor first end, and control low frequency time capacitor is discharged and recharged repeatedly and produces a low frequency ramp voltage at low frequency time capacitor first end;

One low frequency pulse-width modulation comparator, have a first input end, one second input and an output, low frequency pulse-width modulation comparator first input end receives a direct current dim signal, low frequency pulse-width modulation comparator second input is coupled to low frequency time capacitor first end, produce a low frequency pulse-width signal at low frequency pulse-width modulation comparator output terminal, each cycle of low frequency pulse-width signal comprise one enable during and a forbidden energy during;

One feedback control circuit, have an Enable Pin and an output, the feedback control circuit Enable Pin is coupled to low frequency pulse-width modulation comparator output terminal, produces a drive signal at the feedback control circuit output during enabling, and does not produce drive signal at the feedback control circuit output during forbidden energy; And

One AC signal generator has an output, and the AC signal generator output is coupled to low frequency time capacitor first end, provides an alternating current at the AC signal generator output.

2. the control circuit of the inverter of use impulse width modulation and light adjusting according to claim 1 is characterized in that, more comprises:

One comparator has a first input end, one second input and an output, and the comparator first input end receives the direct current dim signal, and comparator second input receives a setting voltage, and setting voltage is the peak voltage of low frequency ramp voltage; And

One switch has one first end, one second end and a control end, and switch first end is coupled to the AC signal generator output, and switch second end is coupled to low frequency time capacitor first end, and the switch control end is coupled to comparator output terminal,

Wherein, when direct current dim signal during more than or equal to setting voltage, comparator output terminal output signal control switch disconnects, AC signal generator output and low frequency time capacitor first end are disconnected, when direct current dim signal during less than setting voltage, the conducting of comparator output terminal output signal control switch makes the AC signal generator output be coupled to low frequency time capacitor first end.

3. the control circuit of the inverter of use impulse width modulation and light adjusting according to claim 2 is characterized in that, more comprises:

One diode has an anode tap and a cathode terminal, and the diode anode end is coupled to switch second end, and the diode cathode end is coupled to low frequency time capacitor first end.

4. the control circuit of the inverter of use impulse width modulation and light adjusting according to claim 2 is characterized in that, more comprises:

One diode has an anode tap and a cathode terminal, and the diode anode end is coupled to the AC signal generator output, and the diode cathode end is coupled to switch first end.

5. the control circuit of the inverter of use impulse width modulation and light adjusting according to claim 1 is characterized in that, more comprises:

One comparator has a first input end, one second input and an output, and the comparator first input end receives the direct current dim signal, and comparator second input receives a setting voltage, and setting voltage is the peak voltage of low frequency ramp voltage; And

One diode has an anode tap and a cathode terminal, and the diode cathode end is coupled to low frequency time capacitor first end; And

One switch has one first end, one second end and a control end, and switch first end is coupled to AC signal generator output and diode anode end, and switch second end is coupled to earthing potential, and the switch control end is coupled to comparator output terminal,

Wherein, when direct current dim signal during more than or equal to setting voltage, the conducting of comparator output terminal output signal control switch makes the diode anode end be coupled to earthing potential, when direct current dim signal during less than setting voltage, comparator output terminal output signal control switch disconnects.

6. the control circuit of the inverter of use impulse width modulation and light adjusting according to claim 1, it is characterized in that, low frequency timing resistor utensil has one first end and one second end, low frequency timing resistor device first end is coupled to a direct current power supply, and low frequency timing resistor device second end is coupled to low-frequency oscillator output and low frequency time capacitor first end.

7. the control circuit of the inverter of use impulse width modulation and light adjusting according to claim 1, it is characterized in that, the low-frequency oscillator output comprises one first output and one second output, low frequency timing resistor utensil has one first end and one second end, low frequency timing resistor device first end is coupled to low-frequency oscillator first output, low frequency timing resistor device second end is coupled to earthing potential, and low frequency time capacitor first end is coupled to low-frequency oscillator second output.

Images