CN201230306Y - Dual phase-locked loop frequency synthesizer - Google Patents
Dual phase-locked loop frequency synthesizer Download PDFInfo
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- CN201230306Y CN201230306Y CNU2008200135901U CN200820013590U CN201230306Y CN 201230306 Y CN201230306 Y CN 201230306Y CN U2008200135901 U CNU2008200135901 U CN U2008200135901U CN 200820013590 U CN200820013590 U CN 200820013590U CN 201230306 Y CN201230306 Y CN 201230306Y
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- locked loop
- frequency synthesizer
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Abstract
The utility model relates to a frequency synthesizer with two phase-locked loops. The frequency synthesizer comprises a phase-locked loop (PLL1), a phase-locked loop (PLL2), an amplifier (AMP), a reference source (Fr) and a select switch (K1) of the reference source, wherein, the output of the reference source (Fr) is connected with the phase-locked loop (PLL1) and the phase-locked loop (PLL2) through the select switch (K1); the output of the phase-locked loop (PLL1) is connected with the amplifier (AMP). Compared with a PLL frequency synthesizer, the frequency synthesizer adopts the same reference signal source, the same PD and the same VCO under the condition of the same loop exponent number. The phase noise of the output signals of the frequency synthesizer with two phase-locked loops is reduced by 5 to 10 dBc.
Description
Technical field
The utility model relates to a kind of frequency synthesizer in the wireless telecommunication system structure, particularly relates to a kind of two phase-locked loop frequency synthesizer.
Background technology
Local oscillator is one of critical component in the radio and television transmitter, and local oscillator adopts " crystal double frequency " mode more in the early stage equipment, and along with development of semiconductor, integrated phase lock (PLL) technology is able to extensive use in this field.At present, in simple phase-locked loop (PLL) frequency synthesizer system, VCO output frequency Fo=N.Fr; Wherein N is system's frequency dividing ratio.
Phase noise is one of frequency synthesizer important technology index, and an ideal sinusoidal (or cosine) signal can be represented with following mathematical formulae:
f(t)＝A?cos(ωt+φ)
The frequency spectrum of this signal can be represented with straight line, but this ideal signal is non-existent, and actual sine (or cosine) signal can be represented with following formula:
F (t)=A[1+ ε (t)] cos[ω t+ φ (t)], wherein φ (t) comprises DC component φ.And noise component(s) φ
n(t), that is: φ (t)=φ
0+ φ
n(t), so, grass was formed about the frequency spectrum of actual signal was reached by straight line, saw Fig. 2
Adopt the frequency synthesizer of PLL technology, the system phase noise is relevant with following factor: reference source phase noise (Nr), VCO phase noise (Nv), the noise that loop frequency-dividing ratio N, system responses cause (Ns); Each parts noise is big more, and system's output noise is big more, and frequency dividing ratio N is big more, and system's output noise is big more.
According to last surface analysis, we can take several different methods to reduce the phase noise of system, for example: select the low phase noise crystal to do reference source, design or select low phase noise VCO, appropriate design system parameters to suppress system noise, reduce method such as loop frequency-dividing ratio N.Which kind of method no matter all can only reduce system noise and can not thoroughly eliminate.
In the real system, can not infinitely improve the phase noise of reference crystal and VCO, this will greatly increase system cost; Adopt system shown in Figure 1 in addition, because Fo is known, behind selected Fr, frequency dividing ratio N=Fo/Fr determines, therefore can only suppress system noise by selective system parameter, raising system " exponent number ", and we know, after system's " exponent number " improves, not only design is complicated, and the stability of a system is relatively poor, and this is the shortcoming place of single PLL just.
Summary of the invention
The utility model has overcome deficiency of the prior art, a kind of two phase-locked loop frequency synthesizer is provided, and this synthesizer is simple in structure, stability is strong, by choose reasonable parametric frequency divider R1, R2 value, effectively reduce loop frequency-dividing ratio N, thereby reached the purpose that reduces the phase of output signal noise.
In order to address the above problem, the utility model by the following technical solutions:
The two phase-locked loop frequency synthesizer, comprise phase-locked loop pll 1, phase-locked loop pll 2, amplifier AMP, reference source Fr and reference source selector switch K1, reference source Fr output is connected with phase-locked loop pll 2 with phase-locked loop pll 1 by selector switch K1, and phase-locked loop pll 1 output connects amplifier AMP.
Phase-locked loop pll 1 connects to form loop successively by phase discriminator PD1, loop filter LPF1, voltage controlled oscillator VC01; Phase-locked loop pll 2 connects to form loop successively by phase discriminator PD2, loop filter LPF2, voltage controlled oscillator VC02; Be provided with frequency mixer MX1 between two loops, frequency mixer MX1 mixed frequency signal is taken from the difference of phase-locked loop pll 1 and phase-locked loop pll 2, sends among the phase discriminator PD1.
Compared with prior art, the beneficial effects of the utility model are: system configuration is simple, by reasonable adjustment parametric frequency divider R1, R2, can effectively reduce the phase of output signal noise, needn't increase extra cost, thereby improve productivity effect.
Description of drawings
Fig. 1 is a typical phase locked loop frequency synthesizer frame principle figure
Fig. 2 is the sinusoidal signal spectrogram
Fig. 3 is a two phase-locked loop frequency synthesizer frame principle figure
Embodiment
See Fig. 3, the two phase-locked loop frequency synthesizer, comprise phase-locked loop pll 1, phase-locked loop pll 2, amplifier AMP, reference source Fr and reference source selector switch K1, reference source Fr comprises internal reference source and external reference source, switches by selector switch K1 and selects, reference source Fr output is connected with phase-locked loop pll 2 with phase-locked loop pll 1 by selector switch K1, and phase-locked loop pll 1 output connects amplifier AMP.
Phase-locked loop pll 1 connects to form loop successively by phase discriminator PD1, loop filter LPF1, voltage controlled oscillator VC01; Phase-locked loop pll 2 connects to form loop successively by phase discriminator PD2, loop filter LPF2, voltage controlled oscillator VC02; Be provided with frequency mixer MX1 between two loops, frequency mixer MX1 mixed frequency signal is taken from the difference of phase-locked loop pll 1 and phase-locked loop pll 2, sends among the phase discriminator PD1.Phase discriminator PD1 inside comprises parametric frequency divider R1 and loop divider N1 able to programme.Phase discriminator PD2 inside comprises parametric frequency divider R2 and loop divider N2 able to programme.
The output signal frequency scope 50MHz～1000MHz of this frequency synthesizer, frequency step can be selected, representative value 250KHz, 50KHz, 5KHz, 1KHz etc., signal output level can be adjusted the AMP gain according to actual needs.
Claims (2)
1, two phase-locked loop frequency synthesizer, it is characterized in that, comprise phase-locked loop (PLL1), phase-locked loop (PLL2), amplifier (AMP), reference source (Fr) and reference source selector switch (K1), reference source (Fr) output is connected with phase-locked loop (PLL2) with phase-locked loop (PLL1) by selector switch (K1), and phase-locked loop (PLL1) output connects amplifier (AMP).
2, two phase-locked loop frequency synthesizer according to claim 1 is characterized in that, phase-locked loop (PLL1) connects to form loop successively by phase discriminator (PD1), loop filter (LPF1), voltage controlled oscillator (VCO1); Phase-locked loop (PLL2) connects to form loop successively by phase discriminator (PD2), loop filter (LPF2), voltage controlled oscillator (VCO2); Be provided with frequency mixer (MX1) between two loops, frequency mixer (MX1) mixed frequency signal is taken from the difference of phase-locked loop (PLL1) and phase-locked loop (PLL2), sends in the phase discriminator (PD1).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2008200135901U CN201230306Y (en) | 2008-06-20 | 2008-06-20 | Dual phase-locked loop frequency synthesizer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2008200135901U CN201230306Y (en) | 2008-06-20 | 2008-06-20 | Dual phase-locked loop frequency synthesizer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201230306Y true CN201230306Y (en) | 2009-04-29 |
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| CNU2008200135901U Expired - Fee Related CN201230306Y (en) | 2008-06-20 | 2008-06-20 | Dual phase-locked loop frequency synthesizer |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103279777A (en) * | 2013-05-06 | 2013-09-04 | 西南交通大学 | Wireless surface acoustic wave temperature measurement system reader-writer |
| CN104836576A (en) * | 2015-04-30 | 2015-08-12 | 华南理工大学 | Phase-locked loop improving high-frequency distorted waveform phase detection |
| CN105027471A (en) * | 2012-12-28 | 2015-11-04 | 协同微波公司 | Self-injection-locked phase-locked loop optoelectronic oscillator |
| CN105024692A (en) * | 2014-04-15 | 2015-11-04 | 特里奎恩特半导体公司 | Clock generation circuit with dual phase-locked loops |
| CN106533439A (en) * | 2017-01-09 | 2017-03-22 | 成都西蒙电子技术有限公司 | Low-phase noise frequency synthesizer |
| CN108055035A (en) * | 2017-12-26 | 2018-05-18 | 北京无线电计量测试研究所 | A kind of wideband frequency expanding unit of optical-electronic oscillator |
| CN109981100A (en) * | 2019-03-08 | 2019-07-05 | 电子科技大学 | A kind of Low Phase Noise Phase-Locked Loop structure being embedded in frequency mixer |
-
2008
- 2008-06-20 CN CNU2008200135901U patent/CN201230306Y/en not_active Expired - Fee Related
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105027471A (en) * | 2012-12-28 | 2015-11-04 | 协同微波公司 | Self-injection-locked phase-locked loop optoelectronic oscillator |
| CN103279777A (en) * | 2013-05-06 | 2013-09-04 | 西南交通大学 | Wireless surface acoustic wave temperature measurement system reader-writer |
| CN105024692A (en) * | 2014-04-15 | 2015-11-04 | 特里奎恩特半导体公司 | Clock generation circuit with dual phase-locked loops |
| CN105024692B (en) * | 2014-04-15 | 2020-03-31 | Qorvo美国公司 | Clock generation circuit with double phase-locked loop |
| CN104836576A (en) * | 2015-04-30 | 2015-08-12 | 华南理工大学 | Phase-locked loop improving high-frequency distorted waveform phase detection |
| CN104836576B (en) * | 2015-04-30 | 2018-11-02 | 华南理工大学 | A kind of phaselocked loop improving the detection of high frequency distortion waveform phase |
| CN106533439A (en) * | 2017-01-09 | 2017-03-22 | 成都西蒙电子技术有限公司 | Low-phase noise frequency synthesizer |
| CN108055035A (en) * | 2017-12-26 | 2018-05-18 | 北京无线电计量测试研究所 | A kind of wideband frequency expanding unit of optical-electronic oscillator |
| CN108055035B (en) * | 2017-12-26 | 2022-03-04 | 北京无线电计量测试研究所 | Broadband frequency extension device of photoelectric oscillator |
| CN109981100A (en) * | 2019-03-08 | 2019-07-05 | 电子科技大学 | A kind of Low Phase Noise Phase-Locked Loop structure being embedded in frequency mixer |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090429 Termination date: 20110620 |