CN201237488Y - Electronic detonator control chip - Google Patents
Electronic detonator control chip Download PDFInfo
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- CN201237488Y CN201237488Y CNU200820115927XU CN200820115927U CN201237488Y CN 201237488 Y CN201237488 Y CN 201237488Y CN U200820115927X U CNU200820115927X U CN U200820115927XU CN 200820115927 U CN200820115927 U CN 200820115927U CN 201237488 Y CN201237488 Y CN 201237488Y
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- 239000000758 substrate Substances 0.000 claims description 36
- 238000004891 communication Methods 0.000 claims description 13
- 238000010304 firing Methods 0.000 abstract 6
- 238000005474 detonation Methods 0.000 abstract 1
- 238000004146 energy storage Methods 0.000 description 8
- 239000004065 semiconductor Substances 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 5
- 230000005611 electricity Effects 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000000306 component Substances 0.000 description 1
- 239000008358 core component Substances 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000000977 initiatory effect Effects 0.000 description 1
- 230000037452 priming Effects 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
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Abstract
The utility model provides an electronic detonator control chip which comprises a power supply management circuit, a firing control circuit, a logic control circuit, a safety discharge circuit and the like, in particular a firing drive circuit. One end of the firing drive circuit is connected with a first pin, one end is connected with the logic control circuit, one end is led to the rest end of the firing control circuit, and the other end is grounded. One end of the firing drive circuit can also be connected with a second pin on the output end of a power supply. The firing drive circuit can comprise a PMOS pipe, an NMOS pipe and two resistors, or a PMOS pipe, a resistor and two NMOS pipes, or an inverter, two PMOS pipes and two NMOS pipes, or an inverter, two PMOS pipes and three NMOS pipes. The technical proposal improves the utilization rate of the detonation energy of an energy saving device of an electronic detonator, and the ignition time precision of the electronic detonator.
Description
Technical field
The utility model relates to the priming system field, relates in particular to a kind of electronic detonator control chip that possesses the ignition driving force.
Background technology
The eighties in 20th century, developed countries such as Japan, Australia, the Europe electric detonator technology that begins one's study.Along with electronic technology, microelectric technique, fast development of information technology, the electric detonator technology has obtained great progress.Late 1990s, electric detonator begins to be dropped into application test and marketing.
As the core component of electric detonator, the performance of electronic detonator control chip directly affects the performance of electric detonator.The electronic detonator control chip of announcing among patent ZL03156912.9 and patent application document 200820111269.7 or the 200820111270.X, realized the nonpolarity connection of two-wire, the electric detonator of electric detonator and basic function such as the two-way communication between the equipment of detonating, built-in detonator identity code, initiation process are controlled, electronics extension, more traditional detonator has had qualitative leap.Above-mentioned electronic detonator control chip adopts the metal-oxide-semiconductor of chip internal to constitute the ignition control circuit, and the ignition process of electric detonator is controlled, and its control signal directly comes from the output of logic control circuit.Patent ZL200420034635.5 and ZL98210324.7 have provided the electric detonator that adopts electronic timing circuit and external discrete electronic component to realize.These two parts of patents adopt IGCT to constitute the circuit that the ignition process of detonator is controlled, and similarly, its control signal comes from the output of logic control circuit.In the above-mentioned background file, because the conducting resistance of metal-oxide-semiconductor or IGCT is closely related with the input voltage of its control end, therefore, the control signal of the low voltage of logic control circuit output will cause the conducting resistance of metal-oxide-semiconductor and IGCT bigger.Therefore,, will consume the energy that electric capacity stored up that detonates in the energy storage device significantly, thereby reduce the effective rate of utilization of the electric capacity that detonates for making above-mentioned metal-oxide-semiconductor or IGCT conducting.In addition, the bigger metal-oxide-semiconductor and the conducting resistance of IGCT are also detonated prolongation the capacitance discharges time, thereby prolong the duration of ignition, the reduction precision duration of ignition of detonator, and then reduce the defer time precision of electric detonator.
Summary of the invention
The purpose of this utility model is to solve the defective of above-mentioned prior art, a kind of electronic detonator control chip that possesses the ignition driving force is provided, be intended to improve the energy utilization ratio of detonating in the energy storage device to electric detonator, and improve the precision duration of ignition of electric detonator simultaneously.
The utility model is realized above-mentioned electronic detonator control chip by the following technical solutions:
First aspect, described electronic detonator control chip comprises communication interface circuit, rectifier circuit bridge, charging circuit, electric power management circuit, ignition control circuit, logic control circuit, nonvolatile memory, reset circuit, safe discharge circuit and clock circuit.Described safe discharge circuit, the one end is connected to described logic control circuit, other end ground connection, a remaining end leads to described chip exterior to constitute a set of pins one.Described electric power management circuit, one end constitute the power output end pin two of described chip, and lead to outside the described chip, and other has an end ground connection.Described ignition control circuit, one end ground connection, other has an end to lead to outside the described chip to constitute a set of pins three.Described logic control circuit, the one end is connected to described clock circuit, and an end connects described pin two, one end ground connection, an end connects described nonvolatile memory, and an end connects described communication interface circuit, one end connects described reset circuit, and an end connects described safe discharge circuit.Described ignition control circuit comprises a NMOS pipe one, the source electrode and the substrate ground connection of described NMOS pipe one, and drain electrode is led to described chip exterior and is constituted described pin three.
Especially, described chip also comprises the ignition drive circuit, and described ignition drive circuit one end connects described pin one, one end and connects described logic control circuit, and an end leads to the remaining end of described ignition control circuit, all the other end ground connection.
Second aspect, described electronic detonator control chip comprises communication interface circuit, rectifier circuit bridge, charging circuit, electric power management circuit, ignition control circuit, logic control circuit, nonvolatile memory, reset circuit, safe discharge circuit and clock circuit.Described safe discharge circuit, the one end is connected to described logic control circuit, other end ground connection, a remaining end leads to described chip exterior to constitute a set of pins one.Described electric power management circuit, one end constitute the power output end pin two of described chip, and lead to outside the described chip, and other has an end ground connection.Described ignition control circuit, one end ground connection, other has an end to lead to outside the described chip to constitute a set of pins three.Described logic control circuit, the one end is connected to described clock circuit, and an end connects described pin two, one end ground connection, an end connects described nonvolatile memory, and an end connects described communication interface circuit, one end connects described reset circuit, and an end connects described safe discharge circuit.Described ignition control circuit comprises a NMOS pipe one, the source electrode and the substrate ground connection of described NMOS pipe one, and drain electrode is led to described chip exterior and is constituted described pin three.
Especially, described chip also comprises the ignition drive circuit, and described ignition drive circuit one end connects described pin one, one end connects described logic control circuit, one end leads to the remaining end of described ignition control circuit, and an end connects described power output end pin two, all the other end ground connection.
Above-mentioned two aspect technical schemes, on the basis of the electronic detonator control chip of in patent ZL03156912.9 and patent application document 200820111269.7 or 200820111270.X, announcing, between former logic control circuit and former ignition control circuit, added the ignition drive circuit, make the low level control signal of logic control circuit output via described ignition drive circuit, be converted to high-level control signal, and then exported to the ignition control circuit by described ignition drive circuit.Its beneficial effect is: improved the metal-oxide-semiconductor in the described ignition control circuit of conducting or the driving voltage of IGCT, thereby reduced the conducting resistance of described metal-oxide-semiconductor and described IGCT.Thereby, on the one hand, improved the energy utilization ratio of detonating in the energy storage device; On the other hand, the capacitance discharges time that reduced to detonate, improved the precision duration of ignition of electric detonator.
As first kind of embodiment of the utility model first aspect technical scheme, described ignition drive circuit comprises two and two resistance of one, NMOS pipe of a PMOS pipe, is respectively resistance one and resistance two.The source electrode of described PMOS pipe one and an end of substrate and described resistance one link together, and are connected to described pin one jointly, lead to described chip exterior.The drain electrode of the grid of described PMOS pipe one, the other end of described resistance one and described NMOS pipe two links together.The drain electrode of described PMOS pipe one and an end of described resistance two link together, and are connected to the grid of described NMOS pipe one jointly.The other end ground connection of described resistance two.The source electrode and the substrate ground connection of described NMOS pipe two, its grid is connected to described logic control circuit.The resistance of described resistance one, resistance two is not less than 100 kilo-ohms.
This embodiment has been finished the basic function of ignition drive circuit.In addition, because during above-mentioned ignition drive circuit works, above-mentioned PMOS pipe one, NMOS pipe one and the two equal conductings of NMOS pipe, thus resistance one, resistance two, igniter are connected in parallel.Therefore, the resistance of above-mentioned resistance one and resistance two is taken as is not less than 100 kilo-ohms, then when getting angry drive circuit works, can be in the capacitor discharge time that reduces to detonate, reduce the loss of the work of ignition drive circuit to stored energy in the electric capacity that detonates, the resistance of above-mentioned resistance is big more, and energy loss is more little.
As second kind of embodiment of the utility model first aspect technical scheme, described ignition drive circuit comprises two, resistance three of PMOS pipe and two NMOS pipes, is respectively NMOS pipe three and NMOS pipe four.The source electrode of described PMOS pipe two and an end of substrate and described resistance three link together, and are connected to described pin one jointly, lead to described chip exterior; The grid of the drain electrode of the grid of the other end of described resistance three, described PMOS pipe two, described NMOS pipe three and described NMOS pipe four links together; The drain electrode of the drain electrode of described PMOS pipe two and described NMOS pipe four links together, and is connected to the grid of described NMOS pipe one jointly; The source electrode and the substrate ground connection of the source electrode of described NMOS pipe three and substrate, described NMOS pipe four; The grid of described NMOS pipe three is connected to described logic control circuit.The resistance of described resistance three is not less than 100 kilo-ohms.
Ignition drive circuit in the present embodiment replaces aforementioned resistance two with NMOS pipe four on the basis of first kind of embodiment.The manner is utilized the little characteristics of NMOS pipe conducting resistance, makes and gets angry control circuit under non-fired state, and is drop-down more reliable; Simultaneously, utilize the big characteristics of NMOS pipe off-resistances, reduce the leakage current that exists in first kind of embodiment.Simultaneously, in IC design, the big shared area of resistance is managed area occupied much larger than NMOS, therefore, adopts the NMOS pipe can also reduce to get angry drive circuit area occupied when integrated.
As first kind of embodiment of the utility model second aspect technical scheme, described ignition drive circuit comprises a phase inverter, two PMOS pipes and two NMOS pipes, is respectively PMOS pipe three, PMOS pipe four, NMOS pipe five and NMOS pipe six.The source electrode and the substrate of the source electrode of described PMOS pipe three and substrate, described PMOS pipe four link together, and are connected to described pin one jointly, lead to described chip exterior; The drain electrode of the grid of the drain electrode of described PMOS pipe three, described PMOS pipe four and described NMOS pipe five links together; The drain electrode of the drain electrode of the grid of described PMOS pipe three, described PMOS pipe four and described NMOS pipe six links together, and is connected to the grid of described NMOS pipe one jointly.The source electrode and the substrate ground connection of the source electrode of described NMOS pipe five and substrate, described NMOS pipe six; The grid of described NMOS pipe five and the input of described phase inverter link together, and are connected to described logic control circuit jointly; The grid of described NMOS pipe six links to each other with the output of described phase inverter.The power input of described phase inverter is connected to described pin two, by described electric power management circuit power supply; Remaining end ground connection of described phase inverter.
Present embodiment is on the basis of second kind of embodiment of first aspect, substitute with PMOS pipe and to be used for the resistance three that draws, make which kind of state no matter the ignition drive circuit be in, in the branch road that constitutes by PMOS pipe and NMOS pipe its each, always there is a metal-oxide-semiconductor to be in cut-off state, thereby avoided the existence of leakage current in the ignition drive circuit.Simultaneously, present embodiment has further reduced to get angry drive circuit shared area when integrated.
As second kind of embodiment of the utility model second aspect technical scheme, on the basis of above-mentioned first kind of embodiment, described ignition drive circuit also comprises a NMOS pipe seven.The drain electrode of described NMOS pipe seven, the power input of described phase inverter link together, and connect described pin two and described electric power management circuit jointly.The drain electrode of the drain electrode of the grid of the source electrode of described NMOS pipe seven, described PMOS pipe three, described PMOS pipe four, described NMOS pipe six links together, and is connected to the grid of described NMOS pipe one jointly.The grid of the grid of described NMOS pipe seven, described NMOS pipe five, the input of described phase inverter link together, and are connected to described logic control circuit jointly.The substrate ground connection of described NMOS pipe seven.
The advantage of this technical scheme is: because the driving power of above-mentioned ignition drive circuit comes from the electric capacity that detonates, therefore, when detonator is lighted a fire, when the voltage of the electric capacity that detonates drops near the turn-on threshold voltage of PMOS pipe four, the equiva lent impedance of PMOS pipe four sharply increases, this moment, PMOS managed the four driving effects that lost substantially the ignition control circuit, thereby the energy in the electric capacity that detonates can't fully be discharged.And since the driving power of NMOS pipe seven from the operating voltage of logic control circuit, therefore NMOS pipe seven still can continue to get angry driving to getting angry control circuit in this case, thereby can fully discharge the ignition energy in the electric capacity that detonates, further improve the utilization rate of the electric capacity stored energy that detonates.
Description of drawings
Fig. 1 need not to connect the embodiment of electric ignition drive circuit for the utility model single capacitor chip includes;
Fig. 2 need connect the embodiment of the ignition drive circuit of electricity for the utility model single capacitor chip includes;
Fig. 3 includes the embodiment that need not to connect electric ignition drive circuit for the two electric capacity chips of the utility model;
Fig. 4 includes the embodiment of the ignition drive circuit that need connect electricity for the two electric capacity chips of the utility model;
Fig. 5 adopts a kind of embodiment that need not to connect electric ignition drive circuit for the utility model;
Fig. 6 adopts the another kind of embodiment that need not to connect electric ignition drive circuit for the utility model;
Fig. 7 adopts a kind of embodiment of the ignition drive circuit that need connect electricity for the utility model;
Fig. 8 adopts the another kind of embodiment of the ignition drive circuit that need connect electricity for the utility model.
The specific embodiment
Below in conjunction with the drawings and specific embodiments the technical solution of the utility model is described in further detail.
A kind of electronic detonator control chip 100, part shown in the empty frame of Fig. 1, Fig. 2 comprises communication interface circuit 101, rectifier circuit bridge 102, charging circuit 103, electric power management circuit 104, ignition control circuit 105, logic control circuit 106, nonvolatile memory 107, reset circuit 110, safe discharge circuit 108 and clock circuit 202.Wherein, safe discharge circuit 108, the one end is connected to logic control circuit 106, other end ground connection 109, a remaining end leads to chip 100 outsides to constitute pin one.Electric power management circuit 104, the one end constitutes the power output end pin two of chip 100, and leads to outside the chip 100, and other has an end ground connection 109.Ignition control circuit 105, one end ground connection 109, other has an end to lead to outside the chip 100 to constitute pin 3.Logic control circuit 106, one end are connected to clock circuit 202, one ends and connect pin two, one end ground connection, 109, one ends connect nonvolatile memory 107, one ends and connect communication interface circuit 101, one end connects reset circuit 110, one ends and connects safe discharge circuit 108.Wherein, the control circuit 105 of getting angry comprises NMOS pipe 151 (referring to Fig. 5), the source electrode and the substrate ground connection 109 of this NMOS pipe 151, and drain electrode is led to chip 100 outsides and is constituted pin 3.
Above-mentioned electronic detonator control chip 100 has kept the design of the electronic detonator control chip of announcing among patent ZL03156912.9 and the patent application document 200820111270.X.
On the one hand, on the basis of above-mentioned patent document, electronic detonator control chip 100 also comprises ignition drive circuit 120, one end of this ignition drive circuit 120 is connected internally to safe discharge circuit 108, electric power management circuit 104, charging circuit 103, ignition control circuit 105 and pin one at chip 100, and being connected to the positive pole of electric capacity in the energy storage device 203 of chip 100 outsides and an end of igniter 204 by pin one, this end of drive circuit 120 of getting angry provides the high drive power supply for getting angry drive circuit 120; The other end of ignition drive circuit 120 connects logic control circuit 106, is used for the ignition control signal of the low voltage of RL control circuit 106 outputs; The drive circuit 120 of getting angry also has an end to lead to ignition control circuit 105 remaining ends, is used for the ignition control signal to ignition control circuit 105 output high voltages; Ignition drive circuit 120 all the other end ground connection 109 are as Fig. 1.
On the other hand, on the basis of above-mentioned patent document, said chip 100 also comprises ignition drive circuit 130, one end of this ignition drive circuit 130 is connected to safe discharge circuit 108, electric power management circuit 104, charging circuit 103, ignition control circuit 105 and is connected pin one at chip internal, and being connected to the positive pole of electric capacity in the energy storage device 203 of chip 100 outsides and an end of igniter 204 by pin one, this end of drive circuit 130 of getting angry provides the high drive power supply for getting angry drive circuit 130; The other end of ignition drive circuit 130 connects logic control circuit 106, is used for the ignition control signal of the low voltage of RL control circuit 106 outputs; An end again of ignition drive circuit 130 leads to ignition control circuit 105 remaining ends, is used for the ignition control signal to ignition control circuit 105 output high voltages; The drive circuit 130 of getting angry also has an end to connect power output end pin two and electric power management circuit 104 simultaneously in chip 100 inside, is used to provide the working power of ignition drive circuit 130; Ignition drive circuit 130 remaining end ground connection 109 are as Fig. 2.
A kind of electronic detonator control chip 800, part shown in the empty frame of Fig. 3, Fig. 4 comprises communication interface circuit 101, rectifier circuit bridge 102, charging circuit 103, electric power management circuit 104, ignition control circuit 105, logic control circuit 106, nonvolatile memory 107, reset circuit 110, safe discharge circuit 108, clock circuit 202 and charging control circuit 180.Wherein, safe discharge circuit 108, the one end is connected to logic control circuit 106, other end ground connection 109, a remaining end leads to chip 800 outsides to constitute pin one.Electric power management circuit 104, the one end constitutes the power output end pin two of chip 800, and leads to outside the chip 800, and other has an end ground connection 109.Ignition control circuit 105, one end ground connection 109, other has an end to lead to outside the chip 800 to constitute pin 3.One end of charging control circuit 180 is connected internally to pin one and safe discharge circuit at chip 800, and leads to chip 800 outsides and be connected to detonate in the energy storage device 203 positive pole of electric capacity and an end of igniter 204; The other end of charging control circuit 180 is connected to rectifier circuit bridge 102, and all the other ends are connected to logic control circuit 106.Logic control circuit 106, one end are connected to clock circuit 202, one ends and connect pin two, one end ground connection, 109, one ends connect nonvolatile memory 107, one ends and connect communication interface circuit 101, one end connects reset circuit 110, one ends and connects safe discharge circuit 108.Wherein, the control circuit 105 of getting angry comprises NMOS pipe 151 (referring to Fig. 5), the source electrode and the substrate ground connection 109 of this NMOS pipe 151, and drain electrode is led to chip 800 outsides and is constituted pin 3.
Above-mentioned electronic detonator control chip 800 has kept the design of the electronic detonator control chip of announcing in patent ZL03156912.9 and the patent application document 200820111269.7.
On the one hand, on the basis of above-mentioned patent document, above-mentioned electronic detonator control chip 800 also comprises ignition drive circuit 120, this end of getting angry drive circuit 120 connects safe discharge circuit 108, charging control circuit 180 and pin ones in chip 800 inside, and being connected to detonate in the chip 800 outside energy storage devices 203 positive pole of electric capacity and an end of igniter 204 by pin one, this end of drive circuit 120 of getting angry provides the high drive power supply for getting angry drive circuit 120; The other end of ignition drive circuit 120 connects logic control circuit 106, is used for the ignition control signal of the low voltage of RL control circuit 106 outputs; The drive circuit 120 of getting angry also has an end to lead to ignition control circuit 105 remaining ends, is used to the ignition control signal of ignition control circuit 105 output high voltages; Ignition drive circuit 120 remaining end ground connection 109 are as Fig. 3.
On the other hand, on the basis of above-mentioned patent document, said chip 800 also comprises ignition drive circuit 130.One end of ignition drive circuit 130 is at chip 800 inner safe discharge circuit 108, charging control circuit 180 and the pin ones of connecting, and being connected to detonate in the chip 800 outside energy storage devices 203 positive pole of electric capacity and an end of igniter 204 by pin one, this end of drive circuit 130 of getting angry provides the high drive power supply for getting angry drive circuit 130; The other end of ignition drive circuit 130 connects logic control circuit 106, is used for the ignition control signal of the low voltage of RL control circuit 106 outputs; An end again of ignition drive circuit 130 leads to ignition control circuit 105 remaining ends, is used to the ignition control signal of ignition control circuit 105 output high voltages; The drive circuit 130 of getting angry also has an end to be connected internally to power output end pin two and electric power management circuit 104 at chip 800, is used to provide the working power of ignition drive circuit 130; Ignition drive circuit 130 remaining end ground connection 109 are as Fig. 4.
As Fig. 5, the ignition drive circuit 120 of said chip 100 or said chip 800 inside comprises 152 and two resistance of 161, NMOS pipes of a PMOS pipe, is respectively resistance 171 and resistance 172.The source electrode of PMOS pipe 161 and an end of substrate and resistance 171 link together, and are connected to pin one jointly, lead to chip exterior, constitute the driving power input of ignition drive circuit 120.The drain electrode of the grid of PMOS pipe 161, the other end of resistance 171 and NMOS pipe 152 links together.The drain electrode of PMOS pipe 161 and an end of resistance 172 link together, and constitute the control signal output of ignition drive circuit 120, and this output is connected to the control signal input of ignition control circuit 105, that is the grid of NMOS pipe 151.The other end ground connection 109 of resistance 172.The source electrode and the substrate ground connection 109 of NMOS pipe 152, its grid is connected to logic control circuit 106, constitutes the control signal input of ignition drive circuit 120.The resistance of resistance 171, resistance 172 is not less than 100 kilo-ohms.
The operation principle of embodiment shown in Figure 5 can be described as: when the grid at NMOS pipe 152 adds the logic-high signal of the low voltage that logic control circuit 106 is exported, NMOS manages 152 conductings, thereby the grid level of PMOS pipe 161 is dragged down, and then makes PMOS manage 161 conductings.Because the conducting resistance of PMOS pipe 161 is extremely low, therefore, getting angry drive circuit 120 will be identical with voltage on the pin one to getting angry the voltage of control signal of control circuit 105 outputs.
As Fig. 6, the ignition drive circuit 120 of said chip 100 or said chip 800 inside comprises 162, resistance 173 of PMOS pipe and two NMOS pipes, is respectively NMOS pipe 153 and NMOS pipe 154.The source electrode of PMOS pipe 162 and an end of substrate and resistance 173 link together, and are connected to pin one jointly, lead to chip exterior, constitute the driving power input of ignition drive circuit 120.The grid of the drain electrode of the grid of the other end of resistance 173, PMOS pipe 162, NMOS pipe 153 and NMOS pipe 154 links together.The drain electrode of the drain electrode of PMOS pipe 162 and NMOS pipe 154 links together, and constitutes the control signal output of ignition drive circuit 120, and this output is connected to the control signal input of ignition control circuit 105, that is the grid of NMOS pipe 151.The source electrode and the substrate ground connection 109 of the source electrode of NMOS pipe 153 and substrate, NMOS pipe 154.The grid of NMOS pipe 153 is connected to logic control circuit 106, constitutes the control signal input of ignition drive circuit 120.The resistance of resistance 173 is not less than 100 kilo-ohms.
The operation principle of embodiment shown in Figure 6 can be described as: when logic control circuit 106 is output as low level, NMOS pipe 153 ends, the grid of PMOS pipe 162 and NMOS pipe 154 is drawn high a little less than by resistance 173, thereby make that PMOS pipe 162 ends, NMOS manages 154 conductings, and then the control signal input end of feasible ignition control circuit 105 is in strong pull-down state.When logic control circuit is output as high level, NMOS manages 153 conductings, the grid of PMOS pipe 162 and NMOS pipe 154 is drop-down by NMOS pipe the last 153, thereby making PMOS manage 162 conductings, NMOS pipe 154 ends, and then the drive circuit 120 of make getting angry is identical with voltage on the pin one to getting angry the voltage of control signal of control circuit 105 outputs.
As Fig. 7, the ignition drive circuit 130 of said chip 100 or said chip 800 inside comprises a phase inverter 181, two PMOS pipes and two NMOS pipes, is respectively PMOS pipe 163, PMOS pipe 164, NMOS pipe 155 and NMOS pipe 156.The source electrode and the substrate of the source electrode of PMOS pipe 163 and substrate, PMOS pipe 164 link together, and are connected to pin one jointly, lead to chip exterior, constitute the driving power input of ignition drive circuit 130; The drain electrode of the grid of the drain electrode of PMOS pipe 163, PMOS pipe 164 and NMOS pipe 155 links together.The drain electrode of the drain electrode of the grid of PMOS pipe 163, PMOS pipe 164 and NMOS pipe 156 links together, constitute the control signal output of ignition drive circuit 130, this output is connected to the control signal input of ignition control circuit 105, that is the grid of NMOS pipe 151.The source electrode and the substrate ground connection 109 of the source electrode of NMOS pipe 155 and substrate, NMOS pipe 156.The grid of NMOS pipe 155 and the input of phase inverter 181 link together, and are connected to logic control circuit 106 jointly, constitute the control signal input of ignition drive circuit 130.The grid of NMOS pipe 156 links to each other with the output of phase inverter 181.The power input of phase inverter 181 is connected to pin two, by electric power management circuit 104 power supplies.Phase inverter 181 remaining end ground connection 109.
The operation principle of embodiment shown in Figure 7 can be described as: when logic control circuit 106 is output as low level, NMOS pipe 155 ends, the logic level that phase inverter 181 is exported to NMOS pipe 156 is a high level, then NMOS manages 156 conductings, thereby make the control signal input of ignition control circuit 105 and the grid of PMOS pipe 163 be in strong pull-down state, PMOS pipe 163 is in conducting state, and the grid and the source electrode of PMOS pipe 164 are in short-circuit condition, and then PMOS pipe 164 is in cut-off state.When logic control circuit was output as high level, NMOS managed 155 conductings, and then the grid of PMOS pipe 164 is a low level state, and PMOS manages 164 conductings; Simultaneously, the logic level that phase inverter 181 is exported to NMOS pipe 156 is a low level, then NMOS pipe 156 ends, thereby the grid and the voltage on the pin one of the control signal input of feasible ignition control circuit 105, PMOS pipe 163 are identical, and PMOS pipe 163 is in cut-off state.
As Fig. 8, the ignition drive circuit 130 of said chip 100 or said chip 800 inside on the basis of embodiment shown in Figure 7, also comprises a NMOS pipe 157.The drain electrode of NMOS pipe 157 and the power input of phase inverter 181 link together, and connect pin two and electric power management circuit 104 jointly.The drain electrode of the drain electrode of the grid of the source electrode of NMOS pipe 157, PMOS pipe 163, PMOS pipe 164, NMOS pipe 156 links together, and is connected to the grid of NMOS pipe 151 jointly.The grid of the grid of NMOS pipe 157, NMOS pipe 155, the input of phase inverter 181 link together, and are connected to logic control circuit 106 jointly.The substrate ground connection 109 of NMOS pipe 157.
The operation principle of embodiment shown in Figure 8 can be described as: when logic control circuit 106 was output as high level, the control circuit 105 of getting angry was in fired state.At the igniting initial stage, the voltage on the pin one is greater than the voltage on the pin two, and NMOS pipe 157 is in cut-off state.Along with the capacitance discharges of detonating, when the voltage on the pin one is reduced near the turn-on threshold voltage of PMOS pipe 164 gradually, the conducting resistance of PMOS pipe 164 will become bigger, simultaneously, the source voltage of NMOS pipe 157 also drops near this turn-on threshold voltage, then NMOS manages 157 conductings, thereby is utilized power supply pipeline circuit 104 to continue the control signal of ignition control circuit 105 is driven.
Claims (7)
1. an electronic detonator control chip comprises communication interface circuit, rectifier circuit bridge, charging circuit, electric power management circuit, ignition control circuit, logic control circuit, nonvolatile memory, reset circuit, safe discharge circuit, clock circuit,
Described safe discharge circuit, the one end is connected to described logic control circuit, other end ground connection, a remaining end leads to described chip exterior to constitute a set of pins one;
Described electric power management circuit, one end constitute the power output end pin two of described chip, and lead to outside the described chip, and other has an end ground connection;
Described ignition control circuit, one end ground connection, other has an end to lead to outside the described chip to constitute a set of pins three;
Described logic control circuit, the one end is connected to described clock circuit, and an end connects described pin two, one end ground connection, an end connects described nonvolatile memory, and an end connects described communication interface circuit, one end connects described reset circuit, and an end connects described safe discharge circuit;
Described ignition control circuit comprises a NMOS pipe one, the source electrode and the substrate ground connection of described NMOS pipe one, and drain electrode is led to described chip exterior and is constituted described pin three;
It is characterized in that:
Described chip also comprises the ignition drive circuit, and described ignition drive circuit one end connects described pin one, one end and connects described logic control circuit, and an end leads to the remaining end of described ignition control circuit, all the other end ground connection.
2. according to the described electronic detonator control chip of claim 1, it is characterized in that:
Described ignition drive circuit comprises two and two resistance of one, NMOS pipe of a PMOS pipe, is respectively resistance one and resistance two,
The source electrode of described PMOS pipe one and an end of substrate and described resistance one link together, and are connected to described pin one jointly, lead to described chip exterior; The drain electrode of the grid of described PMOS pipe one, the other end of described resistance one and described NMOS pipe two links together; The drain electrode of described PMOS pipe one and an end of described resistance two link together, and are connected to the grid of described NMOS pipe one jointly; The other end ground connection of described resistance two; The source electrode and the substrate ground connection of described NMOS pipe two, its grid is connected to described logic control circuit.
3. according to the described electronic detonator control chip of claim 1, it is characterized in that:
Described ignition drive circuit comprises two, resistance three of PMOS pipe and two NMOS pipes, is respectively NMOS pipe three and NMOS pipe four,
The source electrode of described PMOS pipe two and an end of substrate and described resistance three link together, and are connected to described pin one jointly, lead to described chip exterior; The grid of the drain electrode of the grid of the other end of described resistance three, described PMOS pipe two, described NMOS pipe three and described NMOS pipe four links together; The drain electrode of the drain electrode of described PMOS pipe two and described NMOS pipe four links together, and is connected to the grid of described NMOS pipe one jointly; The source electrode and the substrate ground connection of the source electrode of described NMOS pipe three and substrate, described NMOS pipe four; The grid of described NMOS pipe three is connected to described logic control circuit.
4. according to claim 2 or 3 described electronic detonator control chips, it is characterized in that:
The resistance of described resistance one, resistance two and resistance three is not less than 100 kilo-ohms.
5. an electronic detonator control chip comprises communication interface circuit, rectifier circuit bridge, charging circuit, electric power management circuit, ignition control circuit, logic control circuit, nonvolatile memory, reset circuit, safe discharge circuit, clock circuit,
Described safe discharge circuit, the one end is connected to described logic control circuit, other end ground connection, a remaining end leads to described chip exterior to constitute a set of pins one;
Described electric power management circuit, one end constitute the power output end pin two of described chip, and lead to outside the described chip, and other has an end ground connection;
Described ignition control circuit, one end ground connection, other has an end to lead to outside the described chip to constitute a set of pins three;
Described logic control circuit, the one end is connected to described clock circuit, and an end connects described pin two, one end ground connection, an end connects described nonvolatile memory, and an end connects described communication interface circuit, one end connects described reset circuit, and an end connects described safe discharge circuit;
Described ignition control circuit comprises a NMOS pipe one, the source electrode and the substrate ground connection of described NMOS pipe one, and drain electrode is led to described chip exterior and is constituted described pin three;
It is characterized in that:
Described chip also comprises the ignition drive circuit, described ignition drive circuit one end connects described pin one, one end and connects described logic control circuit, and an end leads to the remaining end of described ignition control circuit, one end connects described power output end pin two, all the other end ground connection.
6. according to the described electronic detonator control chip of claim 5, it is characterized in that:
Described ignition drive circuit comprises a phase inverter, two PMOS pipes and two NMOS pipes, is respectively PMOS pipe three, PMOS pipe four, NMOS pipe five and NMOS pipe six,
The source electrode and the substrate of the source electrode of described PMOS pipe three and substrate, described PMOS pipe four link together, and are connected to described pin one jointly, lead to described chip exterior; The drain electrode of the grid of the drain electrode of described PMOS pipe three, described PMOS pipe four and described NMOS pipe five links together; The drain electrode of the drain electrode of the grid of described PMOS pipe three, described PMOS pipe four and described NMOS pipe six links together, and is connected to the grid of described NMOS pipe one jointly;
The source electrode and the substrate ground connection of the source electrode of described NMOS pipe five and substrate, described NMOS pipe six; The grid of described NMOS pipe five and the input of described phase inverter link together, and are connected to described logic control circuit jointly; The grid of described NMOS pipe six links to each other with the output of described phase inverter;
The power input of described phase inverter is connected to described pin two, by described electric power management circuit power supply; Remaining end ground connection of described phase inverter.
7. according to the described electronic detonator control chip of claim 6, it is characterized in that:
Described ignition drive circuit also comprises a NMOS pipe seven,
The drain electrode of described NMOS pipe seven, the power input of described phase inverter link together, and connect described pin two and described electric power management circuit jointly;
The drain electrode of the drain electrode of the grid of the source electrode of described NMOS pipe seven, described PMOS pipe three, described PMOS pipe four, described NMOS pipe six links together, and is connected to the grid of described NMOS pipe one jointly;
The grid of the grid of described NMOS pipe seven, described NMOS pipe five, the input of described phase inverter link together, and are connected to described logic control circuit jointly;
The substrate ground connection of described NMOS pipe seven.
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU200820115927XU CN201237488Y (en) | 2008-06-04 | 2008-06-04 | Electronic detonator control chip |
| PCT/CN2009/071504 WO2009132573A1 (en) | 2008-04-28 | 2009-04-27 | An electronic detonator control chip |
| AU2009242842A AU2009242842B9 (en) | 2008-04-28 | 2009-04-27 | An electronic detonator control chip |
| US12/913,669 US8582275B2 (en) | 2008-04-28 | 2010-10-27 | Electronic detonator control chip |
| ZA2010/08500A ZA201008500B (en) | 2008-04-28 | 2010-11-26 | An electronic detonator control chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU200820115927XU CN201237488Y (en) | 2008-06-04 | 2008-06-04 | Electronic detonator control chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201237488Y true CN201237488Y (en) | 2009-05-13 |
Family
ID=40650222
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNU200820115927XU Expired - Lifetime CN201237488Y (en) | 2008-04-28 | 2008-06-04 | Electronic detonator control chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN201237488Y (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101666595B (en) * | 2009-09-08 | 2012-08-29 | 北京维深数码科技有限公司 | Control chip of digital electronic detonator |
| CN103225994A (en) * | 2013-02-08 | 2013-07-31 | 前进民爆股份有限公司 | Controller and control method of digital electronic detonator |
| CN103869729A (en) * | 2012-12-18 | 2014-06-18 | 北京全安密灵科技股份公司 | Electronic detonator control chip and processing method for correctly restoring host computer communication signal |
| CN105043178A (en) * | 2015-06-08 | 2015-11-11 | 北京丹芯灵创科技有限公司 | Secure network device for electronic detonator initiation system and use method of secure network device |
| WO2018090231A1 (en) * | 2016-11-16 | 2018-05-24 | 南通迅翔自动化设备有限公司 | Electronic delay detonator control circuit |
| CN111412801A (en) * | 2020-04-27 | 2020-07-14 | 湖北航天化学技术研究所 | A kind of electric explosion device ignition circuit |
| CN111595212A (en) * | 2020-05-07 | 2020-08-28 | 上海微符尔半导体有限公司 | Communication demodulation circuit of electronic detonator, electronic detonator chip and electronic detonator system |
| CN112414236A (en) * | 2020-10-15 | 2021-02-26 | 上海芯跳科技有限公司 | Electronic detonator for improving communication reliability |
| CN114884163A (en) * | 2022-05-06 | 2022-08-09 | 上海芯飏科技有限公司 | Charging circuit for electronic detonator and charging calibration method |
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- 2008-06-04 CN CNU200820115927XU patent/CN201237488Y/en not_active Expired - Lifetime
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101666595B (en) * | 2009-09-08 | 2012-08-29 | 北京维深数码科技有限公司 | Control chip of digital electronic detonator |
| CN103869729A (en) * | 2012-12-18 | 2014-06-18 | 北京全安密灵科技股份公司 | Electronic detonator control chip and processing method for correctly restoring host computer communication signal |
| CN103869729B (en) * | 2012-12-18 | 2016-12-28 | 北京全安密灵科技股份公司 | Electronic detonator control chip and the processing method of correct reduction host communication signal |
| CN103225994A (en) * | 2013-02-08 | 2013-07-31 | 前进民爆股份有限公司 | Controller and control method of digital electronic detonator |
| CN105043178A (en) * | 2015-06-08 | 2015-11-11 | 北京丹芯灵创科技有限公司 | Secure network device for electronic detonator initiation system and use method of secure network device |
| WO2018090231A1 (en) * | 2016-11-16 | 2018-05-24 | 南通迅翔自动化设备有限公司 | Electronic delay detonator control circuit |
| CN111412801A (en) * | 2020-04-27 | 2020-07-14 | 湖北航天化学技术研究所 | A kind of electric explosion device ignition circuit |
| CN111595212A (en) * | 2020-05-07 | 2020-08-28 | 上海微符尔半导体有限公司 | Communication demodulation circuit of electronic detonator, electronic detonator chip and electronic detonator system |
| CN112414236A (en) * | 2020-10-15 | 2021-02-26 | 上海芯跳科技有限公司 | Electronic detonator for improving communication reliability |
| CN114884163A (en) * | 2022-05-06 | 2022-08-09 | 上海芯飏科技有限公司 | Charging circuit for electronic detonator and charging calibration method |
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