CN201229937Y - Flip chip packaging structure with non-array bumps - Google Patents

Abstract

The utility model relates to a flip chip packaging structure with non-array lug mainly contains the base plate that is formed with the bonding pad, sets up the encapsulation body of chip, interval adhesion piece and sealed chip on the base plate. In one embodiment, the spacer adhesive member includes spacer balls and adhesive glue. The bumps of the chip are arranged in a non-array and are bonded to the bonding pads. The interval adhesive piece is arranged between the substrate and the chip and supports the periphery of the active surface of the chip. Therefore, the chip can be parallel to the substrate, so that the problem of chip inclination in the process of flip chip bonding and sealing is avoided, and the quality of the flip chip packaging structure is improved.

Description

Flip Chip Package Structure with Non-Array Bumps

technical field

The utility model relates to a semiconductor device, in particular to a flip-chip packaging structure with non-array bumps.

Background technique

At present, the electrical connection methods from the chip to the substrate in the past semiconductor packaging structure can be divided into two categories: Flip Chip Bond and Wire Bond. Wire bonding is to set the chip on the substrate in the form of the active face up (away from the substrate), and to connect the chip to the substrate electrically through the bonding wire. The array configuration, for example, is located in the peripheral area or the central area of the active surface of the chip. The chip used in the known window ball grid array (wBGA) package structure has an electrode located in the center of the active surface of the chip. On the other hand, in flip-chip bonding, bumps are provided on the active surface of the chip in advance, and the active surface of the chip is turned over (towards the substrate) and placed on the substrate, and are electrically connected to the substrate through the bumps. Since the bump provides a short electrical connection path between the chip and the substrate, the integrated circuit with a higher operating frequency in the chip can have good high-frequency signal transmission quality. Therefore, flip-chip bonding is an inevitable development trend of advanced semiconductor devices. Chips with higher and higher operating frequencies will not be limited by the packaging bottleneck of the length of the bonding wire, and can achieve faster processing speed and higher performance.

During the flip-chip soldering process, the bumps must be arranged in an array, otherwise the chip cannot be supported evenly and well, resulting in chip tilting problems. Therefore, even though the electrical function of the chip is the same, such as memory, the chip will be different according to the purpose of wire bonding and flip chip bonding. In other words, known wire-bonded chips cannot be flip-chip-bonded, and conventionally-known flip-chip-bonded chips need additional redistribution line (RDL) process to generate an array configuration and provide an under-bump metal socket (UBM) for setting bumps. pad). However, in the conversion process from wire bonding to flip chip bonding, some people try to use the known wire bonding chip to make a flip chip package, that is, a flip chip package structure with non-array bumps, so as to make the chip common. If wire-bonded chips can be used, the time and material costs of the redistribution line (RDL) process can be omitted, product development time can be shortened, and there is great potential to reduce manufacturing costs.

Please refer to FIG. 1 , a conventional flip-chip packaging structure 100 with non-array bumps includes a substrate 110 , a wire-bonded chip 120 , an encapsulant 150 and two or more external terminals 170 . The substrate 110 has an upper surface 111 , a lower surface 112 and two or more bonding pads 113 formed on the upper surface 111 . The chip 120 is arranged on the upper surface 111 of the substrate 110 and has two or more stud bumps (Stud Bump) 122 formed by wire bonding. (SBB, Stud Bump Bonding) mode is bonded to the bonding pad 113. For example, when the chip 120 is originally suitable for the application of the window type ball grid array package, the bump 122 is located in the central area of the chip 120 . The encapsulant 150 is molded on the upper surface 111 of the substrate 110 and seals the chip 120 . The external terminal 170 is disposed on the lower surface 112 of the substrate 110 . Please refer to FIG. 2 , the manufacturing method of the flip-chip packaging structure 100 includes the following steps: step 1, providing a substrate; step 2, flip-chip welding; step 3, sealing glue; and step 4, setting external terminals. In step 2, the chip 120 has no supporting point, and only the bump 122 in the central area of the chip 120 is bonded to the bonding pad 113 of the substrate 110 , and the parallelism and gap between the chip 120 and the substrate 110 cannot be controlled. In step 3 of "encapsulation", the mold flow pressure forming the encapsulant 150 impacts the chip 120 and tends to swing up and down like a seesaw (as shown in FIG. 1 ), causing the chip 120 to tilt and press against the substrate. The circuit of 110 or the solder joint of the bump 122 is broken, thereby affecting the quality of the electrical connection. Moreover, in step 3, the chip 120 lacking peripheral supporting force is also prone to inclination due to the influence of mold flow. The external terminal 170 is set in step 4 .

Utility model content

In view of this, the main purpose of the present invention is to provide a flip-chip packaging structure with non-array bumps, which can control the parallelism and gap between the chip and the substrate, and avoid chip tilt and bump solder joint breakage.

The purpose of this utility model and its technical solution are to adopt the following technical solutions to achieve. A flip-chip packaging structure with non-array bumps according to the present invention mainly includes a substrate, a chip, two or more spaced adhesive parts, and an encapsulant. The substrate has an upper surface and a lower surface, and two or more bonding pads are formed on the upper surface. The chip is disposed on the upper surface of the substrate, and the active surface of the chip is provided with two or more bumps, wherein the bumps are arranged in a non-array and bonded to the bonding pad. The spacer adhesive is disposed on the upper surface of the substrate to be interposed between the substrate and the chip, and is used to support the periphery of the active surface of the chip. The encapsulant is formed on the upper surface of the substrate and seals the chip.

The purpose of this utility model and the solution to its technical problems can also be further realized by adopting the following technical measures.

In the aforementioned flip-chip packaging structure, the spacer adhesive can be composed of two or more spacer balls and two or more sections of adhesive, the adhesive is arranged on the upper surface of the substrate and adheres to the spacer. ball.

In the aforementioned flip-chip package structure, the substrate may have two or more circuits formed on the upper surface of the substrate, and the spacer balls may not be directly pressed down to the circuits.

In the aforementioned flip-chip packaging structure, an underfill glue may be additionally included to fill the gap between the substrate and the chip to seal the bump.

In the aforementioned flip-chip packaging structure, the underfill glue can cover the circuit and adhere to the active surface of the chip.

In the aforementioned flip-chip packaging structure, the bump can be a wiring bump, and the spacer ball is not attached to the chip, and is only used to control the parallelism and the gap between the chip and the substrate. Bonded to the substrate by bump bonding (SBB), the chip vibrates and slides in a plane parallel to its active face.

In the aforementioned flip-chip packaging structure, the spacer adhesive can be an electrically insulating adhesive.

In the aforementioned flip-chip packaging structure, the encapsulant can cover the circuit.

In the aforementioned flip chip package structure, the spacer adhesive may have a surface soft property.

In the aforementioned flip-chip package structure, the spacer adhesive can be away from the bump without contacting it.

In the aforementioned flip-chip packaging structure, two or more external terminals may be further included, which are disposed on the lower surface of the substrate.

In the aforementioned flip-chip packaging structure, the chip can be a mid-high frequency memory chip in a cross-package form, which is selected from the second-generation double data rate synchronous dynamic random access memory (DDR2 DRAM) chip of 533MHz to 1600MHz.

From the above technical solutions, it can be seen that the flip-chip packaging structure with non-array bumps of the present invention has the following advantages and effects:

1. The placement of spacer balls or spacer adhesives can provide support around the chip, so that there will be no problem of chip tilt during flip-chip soldering or/and sealing. Therefore, the wire-bonded chip has commonality and can be packaged into a flip-chip package structure with non-array bumps.

2. The spacer balls are bonded on the substrate by adhesive or the surface softness of the spacer adhesive parts is used to ensure the supporting effect. Therefore, only the parallelism and the gap between the chip and the substrate can be controlled, so that the chip can be oscillatingly slid in the XY plane for flip-chip soldering in the form of stud bump bonding (SBB) to improve flip-chip packaging with non-array bumps the quality of the structure.

3. The use of spacer adhesives has the characteristics of electrical insulation, which can avoid the phenomenon of electrical short circuit.

4. Since the spacer balls do not directly press down on the circuit of the substrate, the circuit can be prevented from being squeezed and damaged.

5. Fill the flip-chip gap with underfill or encapsulant to cover the circuit and protect the circuit, so that the substrate does not need to be additionally formed with a solder mask, thereby reducing the manufacturing cost.

Description of drawings

1 is a schematic cross-sectional view of a known flip-chip packaging structure with non-array bumps;

Fig. 2 is a flow block diagram of a known manufacturing method of a flip-chip packaging structure with non-array bumps;

3 is a schematic diagram of a flip-chip packaging structure with non-array bumps according to the first specific embodiment of the present invention;

4 is a schematic diagram of components in the manufacturing process of the flip-chip packaging structure according to the first specific embodiment of the present invention;

5 is a schematic diagram of another flip-chip packaging structure with non-array bumps according to the second specific embodiment of the present invention;

FIG. 6 is a flow chart of manufacturing the flip-chip packaging structure according to the second embodiment of the present invention.

Explanation of reference signs

S1 Clearance S2 Clearance

1 Substrate Provided 2 Flip Chip Soldering

3 Sealing glue 4 Setting external terminals

10 Dispensing needles 20 Dispensing needles

30 Dispensing needles 100 Flip-chip package structure

110 Substrate 111 Upper surface

112 Lower Surface 113 Engagement Pad

120 chip 122 bump

150 Sealant 170 External terminal

200 Flip Chip Package Structure 210 Substrate

211 upper surface 212 lower surface

213 Bonding Pad 214 Line

220 chip 221 active surface

222 bump 230 spacer ball

240 Adhesive 250 Sealant

260 Underfill 270 External terminal

300 Flip Chip Package Structure 310 Substrate

311 upper surface 312 lower surface

313 Bonding Pad 314 Line

320 Chip 321 Active Surface

322 bump 340 spacer adhesive

350 Sealant 370 External terminal

Detailed ways

According to the first embodiment of the present invention, a flip-chip packaging structure with non-array bumps is illustrated in the schematic diagram of FIG. 3 . FIG. 4 is a schematic diagram of components in the manufacturing process of the flip-chip packaging structure.

The flip-chip packaging structure 200 mainly includes a substrate 210 , a chip 220 , two or more spaced adhesive members, and an encapsulant 250 . The spacer adhesive piece is composed of two or more spacer balls 230 and two or more sections of adhesive glue 240 . The substrate 210 has an upper surface 211 and a lower surface 212 , and two or more bonding pads 213 are formed on the upper surface 211 . The substrate 210 can be a printed circuit board, a ceramic substrate or a glass substrate. In this embodiment, the bonding pads 213 can be arranged in a straight line or a plurality of parallel straight lines on the central area of the upper surface 211 (as shown in Figure A of FIG. 4 ).

Please refer to FIG. 3 , the chip 220 is disposed on the upper surface 211 of the substrate 210 . The chip 220 can be a memory chip, more specifically, the chip 220 can be a second-generation double data rate (DDR2) memory chip or a third-generation double data rate (DDR3) memory chip. Moreover, the active surface 221 of the chip 220 is provided with two or more than two bumps 222 , wherein the bumps 222 are arranged in a non-array and bonded to the bonding pads 213 . "Non-array arrangement" means not arranged in a matrix of N rows multiplied by M columns, where N and M are positive integers greater than two, and the bump arrangement area is much smaller than the active surface 221 of the chip 220, at least Below one-half. In other words, the bumps 222 are concentrated on a certain area of the active surface of the chip without being distributed and adjusted by the reconfiguration line (RDL) process. In this embodiment, the bumps 222 can be located in the central area of the active surface 221 and can be arranged linearly, wherein the bumps 222 and the bonding pads 213 correspond to each other (as shown in B of FIG. 4 ). The bumps 222 can be gold bumps, copper bumps or composite bumps made of other conductive materials. In this embodiment, the bump 222 is a stud bump (StudBump) formed by wire bonding, and is bonded to the bonding pad 213 by stud bump bonding (SBB). More specifically, the stud bump bonding (SBB) generates gold-gold bonding or other metal bonding between the bump 222 and the bonding pad 213 by ultrasonic vibration friction. Wherein, the ultrasonic vibration is to perform rapid reciprocating micro-movement on the XY plane (ie, the plane parallel to the active surface 221 of the chip), so as to achieve low-temperature metal bonding. Preferably, the reciprocating micro-movement direction should be perpendicular to the linear arrangement direction of the bumps 222 , so as to avoid short-circuit bonding of the bumps 222 during the ultrasonic vibration process. A specific function of the utility model is to use the bonding relationship between the spacer ball 230 and the adhesive 240 to control the parallelism and the gap between the chip 220 and the substrate 210, so as to maintain the supporting effect of the chip and achieve nail head protrusion. Spot bonding (SBB) method of flip-chip bonding, the reason is described in the following two paragraphs.

Please refer to FIG. 3, the spacer ball 230 is arranged on the upper surface 211 of the substrate 210 to be interposed between the substrate 210 and the chip 220, and the spacer ball 230 supports the active surface 221 of the chip 220. around. With such a combination, during the flip-chip bonding step, the active surface 221 of the chip 220 is not adhered by the spacer balls 230 , and can be slid by ultrasonic oscillation in the XY plane. Specifically, the spacer ball 230 is away from the bump 222 of the chip 220 and adjacent to the periphery of the active surface 221 of the chip 220 to provide a better chip slidable support effect. More specifically, the ball diameter of the spacer ball 230 may not be greater than the height of the bump 222 of the chip 220 to ensure the bonding between the chip 220 and the substrate 210 . Please refer to FIG. 3, the ball diameter of the spacer ball 230 is used to define the gap S1 between the substrate 210 and the chip 220, which is approximately equal to the distance from the active surface 221 of the chip 220 to the upper surface 211 of the substrate 210. vertical distance. Wherein, the spacer balls 230 should have the same ball diameter.

Please refer to FIG. 3 , the adhesive 240 is disposed on the upper surface 211 of the substrate 210 and adheres to the spacer ball 230 . Therefore, the adhesive 240 is used to constrain the spacer ball 230 on the upper surface 211 of the substrate 210 to avoid displacement of the spacer ball 230 . In this embodiment, the adhesive 240 does not bond the active surface 221 of the chip 220 . The curing of the adhesive 240 enables the spacer ball 230 to be firmly disposed on the substrate 210, and the curing of the adhesive 240 can be performed after the flip-chip soldering step, so that the spacer ball 230 can be used to define the above-mentioned flip chip. Solder gap S1, and, even if the adhesive 240 adheres to the active surface 221 of the chip 220, it will not stick to the chip 220 before it is cured, so that the chip 220 can be used as an XY plane in the flip-chip welding step ultrasonic vibration. Preferably, the adhesive 240 is kept away from the bonding pad 213 of the substrate 210 to avoid contamination of the bonding pad 213 . In this embodiment, the material of the adhesive 240 may be epoxy resin (Epoxy).

In this embodiment, please refer to FIG. 3 , the substrate 210 may have two or more lines 214 formed on the upper surface 211 of the substrate 210 . Preferably, as shown in Figure A of FIG. 4 , the spacer ball 230 does not directly press down on the circuit 214 , so that the circuit 214 is prevented from being damaged due to extrusion stress, thereby affecting the quality of electrical transmission. In this embodiment, please refer to FIG. 3 , the circuit 214 and the bonding pad 213 may be in the same circuit layer. In this embodiment, the circuit 214 can be a bare wire design, and may not be covered by a solder mask layer, because the chip 220 has good parallelism and good parallelism between the chip 220 and the substrate 210 under the support of the spacer ball 230. Precise flip-chip soldering gap.

Please refer to FIG. 3 , the encapsulant 250 is formed on the upper surface 211 of the substrate 210 and seals the chip 220 , providing proper package protection and preventing dust pollution. The encapsulant 250 can be formed by compression molding or transfer molding.

In this embodiment, please refer to FIG. 3 , the flip-chip packaging structure 200 may additionally include an underfill 260, which fills the gap S1 between the substrate 210 and the chip 220 to seal the bump 222, In order to prevent the stress from concentrating on the specific bump 222 and causing it to break. The underfill 260 can cover the circuit 214 and adhere to the active surface 221 of the chip 220 . Specifically, the underfill glue 260 can seal the adhesive glue 240 , wherein the underfill glue 260 also covers a part of the side of the chip 220 , helping to fix the chip 220 to avoid displacement of the chip 220 . Since the gap S1 can be accurately controlled at a fixed value, the underfill 260 can successfully fill the gap S1 by capillary action without trapping air bubbles.

In this embodiment, as shown in FIG. 3 , the flip-chip packaging structure 200 may additionally include two or more external terminals 270 disposed on the lower surface 212 of the substrate 210 for use as input terminals. And/or the output end so that the flip-chip package structure 200 can be surface-bonded to an external device, such as a printed circuit board (not shown in the figure). The external terminals 270 can be solder balls, solder paste, metal contact pads or pins.

Therefore, the placement of the spacer ball 230 and the adhesive 240 can provide a better supporting effect for the periphery of the chip 220, so that the chip 220 can be balanced during flip-chip soldering without swinging up and down. And it can prevent the chip 220 from being tilted due to the influence of mold flow pressure during sealing, so the flip-chip packaging structure 200 will not have the problem of chip tilting, and the electrical property between the chip 220 and the substrate 210 can be ensured. Connection quality. Moreover, the adhesive 240 adheres the spacer balls 230 , so that the problem that the chip 220 cannot be effectively supported due to the displacement of the spacer balls 230 can be prevented. In addition, the underfill 260 can be used to make the chip 220 more firmly placed on the substrate 210, so as to prevent the chip 220 from being tilted under the influence of mold flow pressure, and to prevent the solder joints of the bump 222 from breaking due to stress concentration. The problem. In addition, the underfill 260 covers the circuit 214 to protect the circuit 214 , so the substrate 210 does not need to form a solder resist layer to save manufacturing cost.

The present invention further illustrates the manufacturing method of the non-array bump flip-chip packaging structure 200 , and an example is shown in the schematic diagram of components in the manufacturing process of FIG. 4 .

First, please refer to Figure A in FIG. 4, the substrate 210 is provided, which has the bonding pad 213, and the adhesive 240 is partially coated on the upper surface 211 by the dispensing needle 10 using a dispensing technique, so as to The line 214 is partially covered. And the spacer ball 230 is arranged on the upper surface 211 of the substrate 210 and in the coating area of the adhesive 240 , wherein the spacer ball 230 is not directly pressed down to the circuit 214 and the spacer ball 230 is away from the bonding pad 213 . The adhesive 240 adheres to the spacer ball 230 to avoid displacement of the spacer ball 230 .

Next, a flip chip bonding step is performed. 4, the chip 220 is disposed on the substrate 210 with the active surface 221 facing the upper surface 211, and the bump 222 of the chip 220 is bonded to the bonding pad 213. (as shown in FIG. 3 ), so as to achieve the electrical interconnection between the chip 220 and the substrate 210 . Wherein, the bump 222 can be a wiring bump, and the bonding method between the bump 222 and the bonding pad 213 can be stud bump bonding (SBB, Stud Bump Bonding). During the flip-chip bonding process, the Z-axis (longitudinal) supporting force around the chip 220 is provided by the spacer ball 230 to avoid the chip 220 from tilting (as shown in FIG. 3 ), but it does not limit the chip 220 in XY Plane (horizontal) slippage.

Next, please refer to Figure C in FIG. 4 , using the dispensing needle 20 to dispense the underfill 260 with high fluidity on the upper surface 211 of the substrate 210 . The underfill glue 260 is first drawn on the side of the chip 220 or the two sides of the L shape, and fills the gap S1 between the chip 220 and the substrate 210 by capillary phenomenon, so as to seal the bump 222 (as shown in FIG. 3).

Referring to FIG. 4 as shown in FIG. 4 , the underfill 260 is baked and cured so that the underfill 260 fills the gap S1 between the substrate 210 and the chip 220 (as shown in FIG. 3 ). Please refer to diagram D in FIG. 4 , the underfill 260 can cover a part of the side of the chip 220 , and the chip 220 can be fixed on the substrate 210 after the underfill 260 is cured. Wherein, after the flip-chip soldering step, the curing of the adhesive 240 may be performed simultaneously with the curing of the underfill 260 , or may be performed before the underfill 260 is formed by dispensing.

Afterwards, please refer to Fig. 4 shown in the E diagram, form this encapsulant 250 on this substrate 210 by compression molding method, to seal this chip 220, in order to protect this chip 220 from being polluted by external dust and moisture (such as Figure 3). Finally, as shown in FIG. 4 , the external terminals 270 are disposed on the lower surface 212 of the substrate 210 , wherein the external terminals 270 are arranged in an array. In this embodiment, the external terminals 270 include solder balls.

Therefore, the utility model can increase the commonality of the wire-bonded chip 220, especially the wire-bonded chip originally suitable for the window-type ball grid array can be used and packaged into a flip-chip packaging structure 200 with non-array bumps, without There will be problems of chip tilt and bump solder joint breakage. Wire-bonded chips do not require reconfiguration line (RDL) process and under-bump metal socket (UBM pad), and the same type of chip has the convenience of process adjustment. In the specific application of the second-generation double data transfer rate synchronous dynamic random access memory (DDR2 DRAM, Double-Data-Rate Two Synchronous Dynamic Random Access Memory) semiconductor package, a wafer containing two or more chips does not It needs to be pre-fabricated in the form of wire bonding or flip-chip bonding. It can be tested first to determine the operable memory frequency of the chip, and after wafer dicing, it can be classified according to the operable memory frequency. Package the DDR2 memory chips that can operate at 553MHz, 667MHz, and 800MHz into a window-type ball grid array packaging structure; package the DDR2 memory chips that can operate at 1066MHz, 1333MHz, and 1600MHz. The utility model flip chip with non-array bumps package structure. The application method of the DDR3 memory chip is also the same as above. Therefore, memory frequency chips in different classification sections can be selectively packaged into suitable packaging forms, and there will be no low memory frequency chips made into chips with array bumps, resulting in the inability to be packaged into a window-type ball grid array package structure or lower The packaging structure of frequency calculation; there will be no high memory frequency chips that are still wire-bonded chips, which can only be packaged into a window-type ball grid array packaging structure for low-frequency calculations, so it has deep industrial application value and obvious The effect of reducing the number of unsuitable chips and increasing process flexibility.

According to the second embodiment of the present invention, another flip-chip packaging structure with non-array bumps is illustrated in the schematic diagram of FIG. 5 . The flip-chip packaging structure 300 mainly includes a substrate 310 , a chip 320 , two or more spaced adhesive members 340 and an encapsulant 350 . The substrate 310 has an upper surface 311 and a lower surface 312 , and the upper surface 311 is provided with two or more bonding pads 313 . In this embodiment, the bonding pad 313 may be located at a central area of the upper surface 311 . Please refer to FIG. 5, the chip 320 is disposed on the upper surface 311 of the substrate 310, and the active surface 321 of the chip 320 is provided with two or more bumps 322, wherein the bumps 322 are arranged in a non-array. bonded to the bonding pad 313 . In this embodiment, the bump 322 may be a gold bump, for example, a wire bonding bump formed by bonding. The bonding method of the bump 322 to the bonding pad 313 can utilize stud bump bonding (SBB) or solder paste bonding. The chip 320 can be a memory chip, specifically a medium-high frequency memory chip in a cross-package form, such as a second-generation double data rate synchronous dynamic random access memory (DDR2 DRAM) chip from 533MHz to 1600MHz.

Please refer to FIG. 5 again, the spacer adhesive 340 is disposed on the upper surface 311 of the substrate 310 to be interposed between the substrate 310 and the chip 320, and the spacer adhesive 340 adheres to the active part of the chip 320. The perimeter of face 321 . The spacer adhesive 340 can move away from the protrusion 322 without contacting it. The spacer adhesive 340 can be an electrical insulating resin to avoid electrical short circuit. In this embodiment, the spacer adhesive 340 can be a double-sided adhesive tape or a B-stage adhesive block, so the active surface 321 of the chip 320 and the upper surface 311 of the substrate 310 can be bonded to make the chip 320 is fixed on the substrate 310 . Preferably, the spacer adhesive 340 has a soft surface. That is to say, the material used by the spacer adhesive 340 to adhere the chip 320 is low modulus, so that the chip 220 can be used for ultrasonic vibration sliding or fine adjustment in the XY plane (horizontal plane) during the flip-chip bonding step.

5, the encapsulant 350 is formed on the upper surface 311 of the substrate 310 and seals the chip 320, and the encapsulant 350 fills the gap S2 between the substrate 310 and the chip 320 to seal the bump. Block 322. In this embodiment, the substrate 310 may have two or more lines 314 formed on the upper surface 311 of the substrate 310 . Preferably, the encapsulant 350 can cover the circuit 314 to prevent the circuit 314 from being polluted, so the substrate 310 does not need to form a solder resist layer to reduce the manufacturing cost. Please refer to FIG. 5 again, the flip chip packaging structure 300 may additionally include two or more external terminals 370 disposed on the lower surface 312 of the substrate 310 for bonding to the outer surface.

Therefore, by means of the spacer adhesive 340, the spacer adhesive 340 can provide a supporting force around the chip 320 during the process of flip-chip soldering or/and encapsulation, thereby preventing the chip 320 from tilting and bumping. 322 produces the problem of solder joint fracture.

The present invention further illustrates the manufacturing method of the aforementioned non-array bump flip-chip packaging structure as illustrated in the flow chart of FIG. 6 .

First, please refer to Figure A in FIG. 6, provide the substrate 310 with the bonding pad 313, and use the dispensing technology to partially apply the spacer adhesive 340 on the substrate 310 through the dispensing needle 30. The upper surface 311 , wherein the spacer adhesive 340 is away from the bonding pad 313 . The spacer adhesive 340 can partially cover the circuit 314 of the substrate 310 . Since the spacer adhesive 340 is electrically insulating, even if the circuit 314 is a bare wire, it will not cause an electrical short circuit.

Next, please refer to FIG. 6 shown in the B diagram, carry out the flip-chip welding step, with the mode that the active surface 321 of the chip 320 faces the substrate 310 is arranged on the substrate 310, and make the bump of the chip 320 322 are bonded to the corresponding bonding pads 313 (as shown in FIG. 5 ), so as to achieve the electrical interconnection between the chip 320 and the substrate 310 . During the flip-chip process, the periphery of the chip 320 can be supported by the spacer adhesive 340 , so there is no problem of chip tilting (as shown in FIG. 5 ).

Next, please refer to Figure C in FIG. 6, bake the spacer adhesive 340, so that the spacer adhesive 340 is cured to adhere the substrate 310 and the chip 320, and provide the chip 320 in the subsequent molding process. Better supporting and fixing effect around.

Afterwards, as shown in Figure D in FIG. 6, the encapsulant 350 is formed on the substrate 310 by a compression molding method and fills the gap S2 between the substrate 310 and the chip 320, so as to seal the chip 320 and the chip 320. The bump 322 (shown in FIG. 5 ). Finally, please refer to diagram E in FIG. 6 , the external terminal 370 is disposed on the lower surface 312 of the substrate 310 .

The above descriptions are only preferred embodiments of the present utility model, and do not limit the utility model in any form. Although the utility model has been disclosed as above with preferred embodiments, it is not used to limit the utility model. Any Any simple modifications, equivalent changes and modifications made by those skilled in the art without departing from the scope of the claims of the present utility model are covered by the technical scope of the present utility model.

Claims (12)

1. A flip-chip packaging structure with non-array bumps, characterized in that it comprises: The substrate has an upper surface and a lower surface, and the upper surface is provided with two or more bonding pads; A chip is disposed on the upper surface of the substrate, and the active surface of the chip is provided with two or more bumps, wherein the bumps are arranged in a non-array and bonded to the bonding pad; Two or more spacer adhesives used to support the periphery of the active surface of the chip are arranged on the upper surface of the substrate and interposed between the substrate and the chip; and The encapsulant is formed on the upper surface of the substrate and seals the chip. 2. The flip-chip packaging structure with non-array bumps according to claim 1, wherein the spacer adhesive is composed of two or more spacer balls and two or more sections of adhesive , the adhesive is disposed on the upper surface of the substrate and adheres to the spacer balls. 3. The flip-chip packaging structure with non-array bumps according to claim 2, wherein the substrate has two or more lines formed on the upper surface of the substrate, and The spacer balls do not press down directly to the line. 4. The flip-chip packaging structure with non-array bumps according to claim 1, characterized in that, the flip-chip packaging structure additionally comprises underfill glue, which fills the gap between the substrate and the chip gap and seal the bumps. 5. The flip-chip packaging structure with non-array bumps according to claim 3, characterized in that, the flip-chip packaging structure additionally comprises underfill glue, which fills the gap between the substrate and the chip gaps and seal the bumps, the underfill glue covers the lines and adheres to the active surface of the chip. 6. The flip-chip packaging structure with non-array bumps according to claim 2, wherein the bumps are wiring bumps, and the parallelism between the control chip and the substrate and the interval between the gaps The balls do not adhere to the chip, and when the chip is bonded to the substrate by stud bump welding, the chip oscillates and slides in a plane parallel to its active surface. 7. The flip-chip packaging structure with non-array bumps according to claim 1, wherein the spacer adhesive is an electrically insulating adhesive. 8. The flip-chip packaging structure with non-array bumps according to claim 1 or 7, wherein the substrate has two or more lines, and the encapsulant covers the lines. 9. The flip-chip packaging structure with non-array bumps according to claim 7, wherein the spacer adhesive is a spacer adhesive with a soft surface. 10. The flip-chip package structure with non-array bumps as claimed in claim 1, wherein the spacer adhesive is away from and does not contact the bumps. 11. The flip-chip packaging structure with non-array bumps according to claim 1, characterized in that, the flip-chip packaging structure additionally includes two or more external terminals, which are arranged on the substrate the lower surface. 12. The flip-chip packaging structure with non-array bumps according to claim 1, wherein the chip is a mid-high frequency memory chip in a cross-package form, which is selected from the second-generation dual Double the data transfer rate synchronous dynamic random access memory chip.

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