CN201163400Y - Novel reconfigurable circuit - Google Patents

Abstract

The utility model relates to the electronic information field, in particular to a reconfigurable circuit, which comprises a microprocessor and reconfigurable hardware. The reconfigurable circuit is characterized in that: the reconfigurable hardware comprises a programmable chip which is formed by a FPGA and is taken as an independent element, a plurality of configuration devices used to configure programs for the programmable chip, and a plurality of OR gate logic circuits; one input end of each OR gate logic circuit is connected with the microprocessor, the other input end of the OR gate logic circuit is connected with the programmable chip, and an output end of the OR gate logic circuit is connected with the configuration devices. The reconfigurable circuit has the advantages that: the configuration starting process of the FPGA and chip selection signals of a data configuration chip are controlled through the microprocessor to realize multifunctional on-line reconfigurability; and the reconfigurable circuit is simple in structure, low in cost, convenient, practical, and suitable for being promoted and applied.

Description

A kind of novel reconfigurable circuit

(1) technical field

The utility model relates to electronic information technical field, particularly a kind of novel reconfigurable circuit.

(2) background technology

Early stage circuit design is switched cost height, equipment complexity to the general two cover circuit that adopt of function reconstruct.In recent years, along with the development of FPGA technology and CPU technology, made the designer can utilize unified hardware platform to carry out the realization of difference in functionality.But in the ordinary course of things, all be to adopt the mode that software is reshuffled and need be re-powered to carry out, this kind mode has the following disadvantages: require outage, and downloaded software will take into full account the work characteristics of system, the design complexity 1.; 2. CPU is required height, setup time is long, debug difficulties.

(3) summary of the invention

The technical problems to be solved in the utility model has provided a kind of novel reconfigurable circuit, by the configuration start-up course of microprocessor control FPGA and the chip selection signal of data configuration chip, realizes the on-line reconfiguration of a plurality of functions.

In order to solve the problems of the technologies described above, the utility model is realized by following measure: a kind of novel reconfigurable circuit, comprise microprocessor and reconfigurable hardware, it is characterized in that: described reconfigurable hardware comprises the programmable chip and a plurality of configuration devices and a plurality of or gate logic that are used for to the programmable chip configurator as independent component that is made of FPGA; Or an input end of door connects above-mentioned microprocessor, or another input end of door connects programmable chip, or gate output terminal connects configuration device.

FPGA described in the utility model is main string pattern configuration.

The beneficial effects of the utility model:

1. by the configuration start-up course of microprocessor control FPGA and the chip selection signal of data configuration chip, realize the on-line reconfiguration of a plurality of functions;

2. simple in structure, with low cost, convenient and practical, suitable applying.

(4) description of drawings

Below in conjunction with the drawings and specific embodiments the utility model is described in further detail.

Fig. 1 is a structural representation of the present utility model.

Fig. 2 is a configuration sequential chart of the present utility model.

(5) embodiment

Accompanying drawing is a specific embodiment of the present utility model, a kind of as shown in Figure 1 novel reconfigurable circuit, comprise microprocessor and reconfigurable hardware, described reconfigurable hardware comprises the programmable chip and a plurality of configuration devices and a plurality of or gate logic that are used for to the programmable chip configurator as independent component that is made of FPGA; Or an input end of door connects above-mentioned microprocessor, or another input end of door connects programmable chip, or gate output terminal connects configuration device.

The utility model FPGA adopts main string pattern configuration mode, and its configuration pin is as follows as shown in Figure 2:

NSTATUS: the state output that under the coomand mode is device.After powering up, FPGA drives this pin immediately to electronegative potential, discharges it then in 100ms.NSTATUS is through moving Vcc on the 10k Ω resistance, if make a mistake in the configuration, FPGA drags down it.When configuration or initialization, if configuration circuit drags down nSTATUS, FPGA enters error condition.

NCONFIG: configuration control input.Electronegative potential resets device, and jump in potential from low to high starts configuration.

CONF_DONF: two-way open-drain; Be state output before configuration and during the configuration, FPGA is driven to low.After all configuration data inerrancy receptions and initialization clock period began, FPGA was changed to three-state with it, because pull-up resistor is arranged, it was become high level, the expression configuration successful.Finish and initialization when beginning in configuration, CONF_DONE is the state input: if configuration circuit drives this pin to low, then postpone initial work; Input noble potential then guide device is carried out the initialization procedure access customer state of going forward side by side.

The output clock that the DCLK:FPGA internal oscillator produces for the series arrangement device provides clock, is controlled whole configuration cycle.

ASDO: serial data output, read the configuration data of series arrangement device with DCLK one same-action.

NCSO: the sheet choosing, during disposing, FPGA is driven to low, chooses series arrangement device to be configured.

The nCE:FPGA device enables input.When nCE is low, enable layoutprocedure.During the monolithic configuration, it is low that nCE must be always.

NCEO: output (being exclusively used in multichip devices).After the FPGA configuration is finished, be output as low.When the multi-disc cascade configuration, drive the nCE end of a slice down.

DATAO: data input, a configuration data on the DATAO pin.

In order to begin configuration, the essential power supply of VCCINT, the VCCIO at configuration pin and JTAG pin place.After powering on, FPGA enters reset mode.NCONFIG is changed to low level, makes FPGA enter reset mode; NCONFIG jump in potential from low to high starts layoutprocedure.Whole configuration comprises three phases: reset, configuration and initialization.When nSTATUS or nCONFIG were low level, device broke away from reset mode, and discharged the nSTATUS pin of open-drain.After nSTATUS discharges, drawn high by non-essential resistance, at this moment nSTATUS and nCONFIG are high level simultaneously, and FPGA prepares to receive configuration data, and configuration phase begins.In the series arrangement process, FPGA latchs data on the DATAO pin at the DCLK rising edge.After successfully receiving all data, discharge the CONF_DONE pin, and drawn high by non-essential resistance.CONF_DONE transition mark configuration from low to high finishes, and initialization begins.After this, DCLK must provide the clock (concrete cycle data is relevant with the frequency of DCLK) in several cycles, guarantees that objective chip is by correct initialization.After initialization was finished, FPGA entered the user job pattern.If used optional INIT_DONE signal, after initialization finished, INIT_DONE was released, and is drawn high by non-essential resistance, at this moment enters user model.

In layoutprocedure, in case mistake occurs, FPGA drags down nSTATUS.System can monitor in real time, after recognizing this signal, restarts layoutprocedure.NCONFIG is uprised and can be configured again by high step-down.In case it is low that nCONFIG is put, nSTATUS and CONF_DONE also will be put low by FPGA.When nSTATUS and nCONFIG are high level simultaneously, the configuration beginning.

Layoutprocedure is shown in Fig. 1 .2: system is put nCONFIG by the OUTPUT1 of microprocessor and lowly puts height again and come initial configuration at the back that powers on, put OUTPUT2 or OUTPUT3 low simultaneously, behind the nCSO of cyclone FPGA step-down, choose configuration device 1 or configuration device 2, under DCLK and ASDO acting in conjunction, the configuration data of the series arrangement device chosen is delivered to the DATAO pin.

In layoutprocedure, microprocessor is monitored the nSTATUS signal in real time, in case the nSTATUS step-down.Illustrate that mistake appears in configuration, restarts layoutprocedure.After configuration was finished, whether microprocessor detected CONF_DONE and uprises, if uprise, configuration successful was described; If do not uprise, configuration failure is described, should restart layoutprocedure.

Claims (2)

1. reconfigurable circuit, comprise microprocessor and reconfigurable hardware, it is characterized in that: described reconfigurable hardware comprises the programmable chip and a plurality of configuration devices and a plurality of or gate logic that are used for to the programmable chip configurator as independent component that is made of FPGA; Or an input end of door connects above-mentioned microprocessor, or another input end of door connects programmable chip, or gate output terminal connects configuration device.

2. according to the described reconfigurable circuit of claim 1, it is characterized in that: described FPGA is main string pattern configuration.

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