CN201146465Y - Frequency conversion circuit with compensation mechanism - Google Patents

Abstract

The utility model relates to a frequency conversion circuit with compensation mechanism, including a load judgement unit, a frequency removal unit and a level modulation unit, be applied to the power supply that has the frequency removal mode, this power supply has a feedback unit at least, produce a feedback signal, this load judgement unit passes through this feedback signal size decision mode of operation, produce a reference frequency signal by this frequency removal unit again, this level modulation unit produces a reference level signal in addition, and produce this reference level signal of compensating current adjustment when the frequency variation, make this power supply's pulse wave modulation unit pass through this reference frequency signal, reference level signal and this feedback signal adjustment this power supply's duty cycle.

Description

Frequency conversion circuit with compensation mechanism

technical field

The utility model relates to a frequency conversion circuit with a compensation mechanism, which is applied to a power supply with a frequency conversion mode, detects the timing of its frequency change and provides a compensation circuit for compensating output power fluctuations.

Background technique

Due to the increasingly stringent environmental regulations around the world, there are also strict standards for the energy consumption of electrical equipment, and the power supply also has an energy-saving circuit to control its output mode so that the output can be adjusted when the load changes, and the circuit switching loss can be reduced to a minimum. At least achieve the purpose of energy saving; as shown in Figure 1, a general power supply includes a primary side rectifier unit 11, a transformer 12, a pulse modulation unit 15, a switch unit 13 and a secondary side output terminal connected The feedback unit, the feedback unit can also be divided into a current feedback unit 141 and a voltage feedback unit 142, the primary side rectification unit 11 receives external power and sends it to the transformer 12 for preliminary conversion, and the transformer 12 converts the power After being converted from the primary side to the secondary side, it is rectified and converted into a stable DC output, and the duty cycle signal provided by the pulse modulation unit 15 enables the switch unit 13 to control whether the primary side of the transformer 12 is turned on or not, and the pulse The wave modulation unit 15 can adjust the duty cycle (dutycycle ratio) of the duty cycle signal according to the feedback signals provided by the current feedback unit 141 and the voltage feedback unit 142, but there is a bottom limit for reducing the duty cycle, so it is To further save energy, the industry has developed frequency conversion and cycle-skipping energy-saving circuits. However, the frequency conversion or cycle-skipping cycle often causes fluctuations in the output voltage (as shown in Figure 2). High or low, the voltage fluctuates up or down, affecting the stability of power output; frequency conversion energy-saving control, such as "Method and apparatus for improving efficiency in a switching regulator at light loads" of US Patent No. 6212079, this utility model can be adjusted The operating frequency of the switching unit, so when the load changes, not only the duty ratio of the duty cycle signal of the switching unit can be adjusted, but also the frequency of the duty cycle signal can be adjusted to reduce the loss generated when the switching unit is switched, so as to further reduce the output However, because the frequency of the frequency conversion circuit changes with the load, the frequency may change at any time, and it is difficult to synchronize with the power factor correction circuit or the pulse modulation circuit of the power supply. If it is not synchronized, the difference frequency will be generated. Noise, even the human ear can hear the sound when the frequency changes, and the frequency conversion energy-saving circuit is difficult to integrate with the power factor correction circuit and the pulse modulation circuit; another type of skip cycle energy-saving circuit such as the "Switched -mode power supply supporting burst-mode operation", this utility model is to divide the cycle of the voltage conversion of the transformer into a normal mode (normal mode) and a burst mode (burst mode), under the general condition of heavy load, the utility model The output power sensing unit (output power sensing unit) adjusts the pulse width according to the change of the output load. When the load is reduced to a certain extent, the utility model will maintain the original pulse width and skip some cycles. The control circuit achieves the purpose of reducing the loss by reducing the pulse width or increasing the length of the shielding cycle, but the technology of the pulse mode has obvious disadvantages, that is, the switching frequency noise generated by the low-frequency interference during the shielding cycle will decrease with the The reduction of the frequency becomes more and more obvious, and the user can clearly hear the switching noise of the light-load operation, and the sudden change of the load will cause a sudden drop in the output voltage and a wavy voltage waveform generated by excessive circuit response (such as the utility model Figure 6 and Figure 8); thus the above-mentioned known utility model has disadvantages such as asynchronous, obvious low-frequency or difference-frequency noise, etc., must improve the above-mentioned problems, in order to further integrate with other circuits and reduce the use of patient's discomfort.

Utility model content

In view of the problems of frequency out-of-synchronization and voltage overcompensation caused by the known frequency conversion method, the primary purpose of this utility model is to provide a circuit that can change frequency according to load changes, and has a compensation mechanism to adjust pulse modulation when frequency changes. The duty cycle signal output by the variable unit can significantly reduce the impact on the output voltage during frequency conversion.

The utility model relates to a frequency conversion circuit with a compensation mechanism, which is applied to a power supply with a frequency division mode. The power supply has at least one feedback unit, which generates a feedback signal, so that a pulse wave modulation unit changes its The output duty cycle signal, thereby adjusting the output power of a transformer secondary side, and the pulse modulation unit generates the duty cycle signal through a reference level signal, a reference frequency signal and the feedback signal, when the load increases Or when reducing, the frequency conversion circuit with compensation mechanism can adjust the reference level signal and reference frequency signal to achieve the effect of adjusting the operating frequency with the load and stabilizing the output during frequency conversion; wherein the frequency conversion circuit with compensation mechanism includes a load judging unit , a frequency division unit and a level modulation unit, the load judging unit determines whether to output a frequency conversion signal according to the magnitude of the feedback signal to determine whether the frequency conversion circuit operates in a normal mode or a frequency division mode, and the frequency division unit obtains A first clock signal, and output a reference frequency signal with the same frequency as the first clock signal in the normal mode, and in the frequency division mode, the frequency division unit divides the frequency of the first frequency signal by an integer Then generate a second clock signal, and output a reference frequency signal with the same frequency as the second frequency signal, and the level modulation unit outputs the reference level signal, and defines a normal level of the reference level signal , wherein the level modulation unit includes a compensation unit and a slope generator, the slope generator makes the compensation unit generate a compensation current to change the reference level signal when receiving the frequency conversion signal, and makes the reference level The signal returns to the normal level within a buffer time, so as to achieve the effects of transient compensation and stable output during frequency conversion.

Description of drawings

Fig. 1 is a known circuit structure diagram.

Figure 2 is a known circuit waveform diagram.

Fig. 3 is an application circuit architecture diagram of the utility model.

Fig. 4 is a block diagram of the structure of the frequency conversion circuit of the present invention.

Fig. 5 is the implementation circuit diagram of the utility model.

Fig. 6 is a node waveform diagram of the implementation circuit of the utility model.

Detailed ways

Relevant detailed description and technical content of the present utility model, now just explain as follows with respect to coordinating schematic diagram:

Please refer to FIG. 3 , the utility model is a frequency conversion circuit 2 with a compensation mechanism, which is used to adjust the duty cycle signal VG output by a pulse wave modulation unit 15 of a power supply. The pulse wave modulation unit 15 utilizes a reference The duty cycle signal VG is generated by the level signal VR, a reference frequency signal VF and a feedback signal VFB. The power supply includes a primary side rectification unit 11 , a transformer 12 , a switch unit 13 and a feedback unit 14 And the pulse modulation unit 15, and the frequency conversion circuit 2 with compensation mechanism is connected to the feedback unit 14 to obtain the feedback signal VFB, and output a reference level signal VR, a reference frequency signal VF to the pulse modulation Transformer unit 15; an input power Vin is converted from the primary side of the transformer 12 to the secondary side output after passing through the primary side rectification unit 11, and the power converted to the secondary side of the transformer 12 is controlled by the switch unit 13, and the The duty cycle of the switching unit 13 is controlled by the duty cycle signal VG output by the pulse modulation unit 15, and the output terminal of the secondary side of the transformer 12 is connected to a feedback unit 14 to generate the feedback signal VFB to adjust the The output of the pulse modulation unit 15; the frequency conversion circuit 2 with compensation mechanism includes a load judging unit 21, a frequency dividing unit 23 and a level modulating unit 22, the load judging unit 21 according to the feedback signal VFB Select to operate in normal mode or frequency division mode, the frequency division unit 23 obtains a first clock signal CLK1, and outputs a reference frequency signal VF with the same frequency as the first clock signal CLK1 in the normal mode, and In the frequency division mode, the frequency division unit 23 divides the frequency of the first clock signal CLK1 by an integer to generate a second clock signal CLK2, and outputs a reference frequency signal having the same frequency as the second frequency signal CLK2 VF, and the level modulation unit 22 outputs the reference level signal VR, and defines a normal level of the reference level signal VR, wherein the level modulation unit 22 switches between the normal mode and the frequency division mode A compensating current is generated to adjust the reference level signal VR, so that the pulse modulation unit 15 adjusts the duty cycle signal VG accordingly to compensate for the change of the voltage output when the normal mode and the frequency division mode are converted.

Please refer to FIG. 4 and FIG. 5, these schematic diagrams show the structure block diagram and implementation circuit diagram of the present invention, the frequency conversion circuit 2 with compensation mechanism is composed of the load judging unit 21, the level modulation unit 22 and the divider frequency unit 23, wherein the level modulation unit 22 includes a slope generator 221 and a compensation unit 222, the load judging unit 21 outputs a frequency conversion signal Vs during frequency conversion, and the slope generator of the level modulation unit 22 221 is triggered by the frequency conversion signal Vs even if the compensation unit 222 generates a compensation current to change the reference level signal VR, and makes the reference level signal VR return to the setting of the level modulation unit 22 within a buffer time normal level, to achieve the effect of transient compensation and stable output during frequency conversion; the preferred implementation circuit of the utility model is shown in Figure 5, the load judging unit 21 includes a comparator A 211, a D-type flip-flop 212 , a changeover switch 213, a first constant voltage source 214, a second constant voltage source 215 and a plurality of logic gates, the comparator A 211 has a positive input terminal, a negative input terminal and an output terminal, the comparator The positive input terminal of A 211 receives the feedback signal VFB, the negative input terminal of the comparator A 211 is connected to the switch 213, the output terminal of the comparator A 211 is connected to a data terminal of the D-type flip-flop 212, the The D-type flip-flop 212 also has a frequency control terminal (CLK), a positive output terminal (Q) and a negative output terminal, wherein the frequency control terminal (CLK) of the D-type flip-flop 212 receives the reference frequency signal VF , the negative output end of the D-type flip-flop 212 is connected to and controls the switching action of the switch 213, one end of the switch 213 is connected to the negative output end of the comparator A 211, and the other end is controlled by the D-type flip-flop. The negative output terminal of device 212 controls and switches and connects this first constant voltage source 214 and a second constant voltage source 215, and this first constant voltage source 214 defines a first reference voltage, and this second constant voltage source 215 Define a second reference voltage, use the feedback signal VFB to compare with the first reference voltage or the second reference voltage, when the frequency conversion circuit 2 with compensation mechanism operates in the normal mode, if the feedback signal VFB is smaller than the first reference voltage A reference voltage, the frequency conversion circuit 2 with a compensation mechanism is converted from the normal mode to the frequency division mode. In the frequency division mode, if the feedback signal VFB is greater than the second reference voltage, the frequency division mode is converted to the normal mode. , the operation logic of the D-type flip-flop 212 is known to those skilled in the art, and will not be repeated here. The positive input terminal of the D-type flip-flop 212 outputs a state signal VL, and the D-type flip-flop 212 The output of the frequency conversion signal Vs is formed after a plurality of logic gate operations; the frequency division unit 23 includes a T-type flip-flop 231 and a plurality of logic gates, and the T-type flip-flop 231 also has a trigger terminal (T), A clock control terminal (CLK), a positive output terminal (Q) and a negative output terminal, wherein the trigger terminal (T) is connected to the positive output terminal of the D-type flip-flop 212 in the load judging unit 21 to obtain the state signal VL , the clock control terminal (CLK) receives the first clock signal CLK1, and the operation logic of the T-type flip-flop 231 is also known to those skilled in the art, and will not be described in detail. The plurality of logic gates are connected to The negative output terminal of the D-type flip-flop 212 in the load judging unit 21 and the positive output terminal (Q) of the T-type flip-flop 231 receive the first clock signal CLK1 to generate the reference frequency signal VF; The quasi-modulation unit 22 includes a slope generator 221, and a compensation unit 222 including a first compensation loop and a second compensation loop, wherein the first compensation loop is composed of a first current source X1 and a first bias power supply Composed of Vref1, the second compensation circuit is composed of a second current source X2, a second bias power supply Vref2 and a resistor R4, wherein the first current source X1 and the second current source X2 are current control current sources, the A switch element SW1 and a diode D1 are also included between the first compensation loop and the second compensation loop, wherein the switch element SW1 is controlled by the negative output terminal of the D-type flip-flop 212, and the slope generator 221 can be a A digital counter, each output end of the digital counter is connected to a resistor, and the digital counter also has a clock input end to receive a third clock signal CLK3, so that the digital counter can use the frequency of the third clock signal CLK3 Count down and output pulses from multiple output terminals, and the pulses output by the digital counter control the action of the compensation unit 222 .

Please refer to FIG. 5 and FIG. 6 together. When the load is light load, it operates in a frequency division mode with a lower frequency in order to reduce loss. In the frequency division mode, one end of the switch 213 of the load judging unit 21 is connected to the first A certain voltage source 214 (this embodiment is set to 0.2V), when the feedback signal VFB is greater than the first constant voltage source 214, the output of the comparator A 211 is a high level, and the D-type flip-flop 212 outputs The state signal VL of the frequency division unit 23 is at a high level. At this time, the T-type flip-flop 231 of the frequency dividing unit 23 generates a second clock signal CLK2. Through the output characteristics of the T-type flip-flop 231, the first clock signal CLK2 The second clock signal CLK2 is generated after the frequency of the signal CLK1 is divided by 2, and a plurality of logic gates are connected to the negative output terminal of the D-type flip-flop 212 in the load judging unit 21, the second clock signal CLK2 and the first clock signal. The pulse signal CLK1 is then calculated to generate the reference frequency signal VF, and the frequency of the reference frequency signal VF is the same as the frequency of the second frequency signal CLK2. At this time, the level modulation unit 22 is powered by the second bias power of the compensation unit 222 Vref2 provides a fixed voltage as the reference level signal VR, and since the voltages of the first compensation loop and the second compensation loop are fixed at this time, a normal level of the reference level signal VR is formed; when the load becomes larger, Make the feedback signal VFB drop to a voltage lower than the first constant voltage source 214, then the output of the comparator A 211 is at a low level, and the output of the D-type flip-flop 212 is reversed, and the switch 213 is due to the The output of the negative output terminal of the D-type flip-flop 212 is reversed and switched to the second constant voltage source 215, and the moment the positive output terminal of the D-type flip-flop 212 and the output of the negative output terminal are reversed, after the positive output terminal An inverter at the end produces a delay, so that the two input terminals of the back-end exclusive OR gate (XOR gate) are different and output a high-level short-term pulse wave to form a frequency-variable signal Vs. At this time, the frequency-dividing unit 23 The T-type flip-flop 231 does not operate, so that multiple logic gates at the back end output the reference frequency signal VF with the same frequency as the first clock signal CLK1, that is, return to the normal mode, and the slope generator in the level modulation unit 22 The digital counter of 221 is triggered by the variable frequency signal Vs, and the digital counter also has a frequency input terminal to receive the third clock sequence number CLK3, and make the slope generator 221 start from the frequency of the third clock signal CLK3. The highest digit counts down and outputs the pulse wave to form a gradually weakening ramp waveform. The voltage difference between the output terminal of the digital counter and the first bias power supply Vref1 forms a current, so that the first current source of the first compensation loop X1 outputs a corresponding current, and the switching element SW1 between the first current source X1 and the second current source X2 is turned on because the negative output terminal of the D-type flip-flop 212 is at a high level, so that the second current Source X2 also generates current along with the first current source X1, and the current generated by the second current source X2 passes through the resistor R4 to the output terminal to form a negative compensation current that changes the reference level signal VR; becomes smaller, so that the feedback signal VFB rises to a voltage higher than the second constant voltage source 215 (this embodiment is set to 0.55V), then the output of the D-type flip-flop 212 is reversed again, and the switch 213 switches To the first constant voltage source 214, the T-type flip-flop 231 and a plurality of logic gates of the frequency dividing unit 23 receive the state signal VL output by the D-type flip-flop 212 and the first clock signal CLK1, the T Type flip-flop 231 generates the second clock signal CLK2, and outputs a reference frequency signal VF with the same frequency as the second clock signal CLK2 through a plurality of logic gates. At this time, the slope generator of the level modulation unit 22 221 is again triggered by the variable frequency signal Vs to count down and output pulse waves, and the first current source X1 also generates a corresponding current according to the voltage difference between the output terminal of the digital counter and the first bias power supply Vref1, because the D-type positive The negative output terminal of the inverter 212 is at a low level, and the switching element SW1 is turned off, so the current of the first current source X1 passes through a diode D1 to form a positive compensation current to the output terminal, thereby adjusting the reference level signal VR .

The slope generator 221 of the present utility model can be a digital counter, which counts down the frequency of the third clock signal CLK3 and outputs a pulse wave, so that the first compensation loop and the second compensation loop form a step-up or down compensation current, And the slope generator 221 can also be a charge-discharge circuit comprising at least one capacitor, and the voltage change of the capacitor charge-discharge period controls the current output size of the first compensation circuit; the utility model has the function of frequency division to make the power supply The device can work at different frequencies under light load or heavy load, and the frequency dividing unit 23 can also be set to divide the first clock signal CLK1 by an integer (such as 2 or 3 or 4, etc.), so as to generate the The frequency of the second clock signal CLK2 is used to reduce the operating loss, and the reference level signal VR has a fixed average slope in the transient state of the conversion mode to return to the normal level through the positive compensation current or the negative compensation current, and The buffer time is formed during the period from the beginning of the transient state to the return to the normal state level, so that the output voltage fluctuation of the power supply is minimized, and the effects of transient compensation and stable output are achieved during frequency conversion, and the utility model utilizes the method of frequency division The frequency is changed, and the second clock signal CLK2 with a lower frequency is generated by dividing the first clock signal CLK1, so that the frequency after frequency conversion can still be synchronized with the original frequency, so that it can be integrated with other circuits. Advantages of an integrated circuit.

Although the present utility model has been disclosed above with preferred embodiments, it is not intended to limit the present utility model. Anyone skilled in the art, without departing from the spirit and scope of the present utility model, should make some changes and modifications. Covered in the utility model, so the scope of protection of the utility model should be defined by the scope of the appended patent application.

Claims (11)

1. A frequency conversion circuit with a compensation mechanism, which is applied to a power supply with a frequency division mode, and the power supply has the ability to generate a feedback signal so that the pulse modulation unit (15) changes the duty cycle signal of its output A feedback unit (14), and the pulse wave modulation unit (15), the pulse wave modulation unit (15) generates the duty cycle signal through a reference level signal, a reference frequency signal and the feedback signal , it is characterized in that, described frequency conversion circuit (2) with compensation mechanism comprises: A load judging unit (21), which determines whether to output a variable frequency signal corresponding to the magnitude of the feedback signal; The frequency division unit (23) obtains the first clock signal, and outputs a reference frequency signal having the same frequency as the first clock signal to the pulse modulation unit (15) when the frequency conversion circuit operates in a normal mode. When the frequency conversion circuit operates in the frequency division mode, the frequency division unit (23) divides the frequency of the first clock signal by an integer to generate a second clock signal, and the output frequency is the same as that of the second clock signal the reference frequency signal to the pulse modulation unit (15); and A level modulation unit (22), outputting the reference level signal to the pulse wave modulation unit (15), and defining a normal level of the reference level signal, wherein the level modulation unit ( 22) Including a compensation unit (222) and a slope generator (221), one end of the slope generator (221) is connected to the load judgment unit (21) and the frequency division unit (23) and the other end is connected to the The compensation unit (222), the slope generator (221) receives the frequency conversion signal, the compensation unit (222) generates a compensation current that changes the reference level signal, and the reference level signal is in the buffer time Return to normal level. 2. The frequency conversion circuit with a compensation mechanism according to claim 1, wherein the compensation unit (222) of the level modulation unit (22) generates a negative compensation current when the frequency division mode changes to a normal mode, A positive compensation current is generated when the normal mode is changed to the frequency division mode. 3. The frequency conversion circuit with compensation mechanism according to claim 2, characterized in that, the level modulation unit (22) includes a slope generator (221), and includes a first compensation loop and a second compensation loop The compensation unit (222), after the slope generator (221) receives the frequency conversion signal in the normal mode, even if the first compensation loop generates a positive compensation current, the slope generator (221) in the frequency division mode receives the After the frequency conversion signal, even if the second compensation circuit generates a negative compensation current, the reference level signal has a fixed average slope in the transient state of the conversion mode and returns to the normal level through the positive compensation current or negative compensation current, And the buffer time is formed during the period from the beginning of the transient state to returning to the normal state level. 4. The frequency conversion circuit with compensation mechanism according to claim 3, characterized in that, the first compensation circuit is composed of a first current source and a first bias power supply, and the second compensation circuit is composed of a second current source , a second bias power supply and a resistor, a switch element and a diode are also included between the first compensation loop and the second compensation loop, and the switch element is turned on in normal mode to make the second power supply work. 5. The frequency conversion circuit with compensation mechanism according to claim 3, characterized in that, the slope generator (221) is a digital counter with multiple output terminals, and each output terminal is connected to a resistor, and the The digital counter also has a clock input terminal to receive a third frequency signal, so that the digital counter counts down at the frequency of the third clock signal and outputs a pulse wave, thereby making the first compensation loop and the second compensation loop form a step Rising or falling compensation current. 6. The frequency conversion circuit with a compensation mechanism according to claim 3, characterized in that, the slope generator (221) includes at least one capacitor charging and discharging loop, and the voltage change during the charging and discharging period of the capacitor controls the The output size of the first compensation loop. 7. The frequency conversion circuit with compensation mechanism according to claim 1, characterized in that, the load judging unit (21) has a first reference voltage and a second reference voltage, and compares them with the feedback signal to determine the The frequency conversion circuit (2) with compensation mechanism operates in normal mode or frequency division mode. 8. The frequency conversion circuit with compensation mechanism according to claim 7, characterized in that, when the frequency conversion circuit (2) with compensation mechanism operates in normal mode, if the feedback signal is smaller than the first reference voltage, the frequency conversion circuit (2) with a compensation mechanism is converted from the normal mode to the frequency division mode. In the frequency division mode, if the feedback signal is greater than the second reference voltage, the frequency division mode is converted to normal mode. 9. The frequency conversion circuit with compensation mechanism according to claim 8, characterized in that, the load judging unit (21) includes a comparator A (211), a D-type flip-flop (212), a switch (213 ), the first constant voltage source (214), the second constant voltage source (215) and a plurality of logic gates, the comparator A (211) has a positive input terminal, a negative input terminal and an output terminal, and the comparator A The positive input terminal of (211) receives the feedback signal, the negative input terminal of the comparator A (211) is connected to the switch (213), and the output terminal of the comparator A (211) is connected to the D The data terminal of the D-type flip-flop (212), the D-type flip-flop (212) also has a clock control terminal, a positive output end and a negative output end, wherein the clock pulse of the D-type flip-flop (212) The control terminal receives the reference frequency signal, the negative output terminal of the D-type flip-flop (212) is connected to and controls the switching action of the switch (213), and one end of the switch (213) is connected to the The negative output terminal of the comparator A (211), and the other end is controlled by the negative output terminal of the D-type inverter (212) to switch and connect the first constant voltage source (214) and the second constant voltage source (215), the output of the positive input end and the negative input end of the D-type flip-flop (212) passes through the plurality of logic gates to output a frequency conversion signal. 10. The frequency conversion circuit with compensation mechanism according to claim 9, characterized in that, the frequency division unit (23) includes a T-type flip-flop (231) and a plurality of logic gates, and the T-type flip-flop (231) also has a trigger terminal, a clock control terminal, a positive output terminal and a negative output terminal, wherein the trigger terminal is connected to the positive output terminal of the D-type flip-flop (212) in the load judging unit (21), so The clock control terminal receives the first clock signal, and the plurality of logic gates are connected to the negative output terminal of the D-type flip-flop (212) in the load judging unit (21), the T-type positive The positive output terminal of the inverter (231), and receives the first clock signal to generate the reference frequency signal. 11. The frequency conversion circuit with a compensation mechanism according to claim 1, wherein the frequency of the second frequency signal is the frequency of the first frequency signal divided by an integer multiple.

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