CN201130309Y - Redundant switching control circuit - Google Patents

Abstract

The utility model relates to the field of automatic control, in particular to a redundant switch control circuit, which includes two symmetrical templates, each template includes a CPU and a switch control circuit, and the switch control circuit is used to send a fixed frequency signal in the main state. Switch to the slave state after receiving the fixed frequency signal; it is used to receive the fixed frequency signal in the slave state, and switch to the master state after the received fixed frequency signal disappears. The utility model sends a fixed frequency signal as a connection signal between redundant devices through the main template, which increases the reliability of the redundant switching control signal, and can immediately complete the redundant switching control no matter what causes the CPU failure of the main template . In addition, when the two redundant modules are working in the redundant state, when the master module is pulled out, the slave module will immediately switch to the master state if the square wave signal is not detected, so the live plugging and unplugging of the master and slave modules can be realized .

Description

Redundant switching control circuit

technical field

The utility model relates to the field of automatic control, in particular to a redundant switching control circuit.

technical background

In industrial control systems with high requirements, it is often necessary to adopt redundant configuration technology for key controllers and I/O modules, so that the system can continue to operate under fault conditions, and at the same time, the system can be maintained online to ensure the control of the object. safe operation. From the perspective of cost and practicability, usually the redundant system adopts dual-mode redundancy technology. When one device is in the active state, the other device is in the slave state.

In a dual-mode redundant structure, some status signal connections are required between redundant modules. These signals are connected to the control logic circuit, and then connected to their respective control CPUs. The CPU receives these status signals to determine whether the device is running in the master state or the slave state. Usually, various status signals between redundant modules directly affect the reliability of switching. How to design status signals between redundant devices becomes the basis for reliable switching.

In the previous traditional switching method, there is a switching component between redundant devices, which monitors and controls the two redundant devices, and can receive switching commands from the host computer at the same time. Later, in the patent with the publication number CN1275000A, the redundant state signal connection between the mutually redundant devices was developed, and the two mutually redundant devices use these state lines of the devices to determine whether they should run in the main status is still in use. This switching method uses a shared data memory for common data, so that the reliability of the memory is greatly reduced when a fault occurs for the memory. In this method, there are more status signals between redundant devices.

The publication number is CN 1591348A, which uses the combination of NAND logic and CPU to form the signal connection between redundant devices. In the switching method, the logical value is used to judge the fault level, and whether to switch is determined according to the different levels. At the same time, it can provide power-off and reset fast switching, and also provides a manual switching method.

These switching schemes all adopt the principle of binary logic. Due to the poor security of binary logic, if the state signal interface logic is locked at '1' or '0', especially the logic deadlock is in the normal state. , the fault will be difficult to judge.

Utility model content

In order to solve the above problems, the utility model provides a redundant switching control circuit with simple control, low failure rate and safer signal transmission.

The technical solution adopted by the utility model to solve the technical problem is: a redundant switching control circuit, each template includes a CPU and a switching control circuit, and the switching control circuit in the main state sends a signal with a fixed frequency signal The port is connected with the signal port receiving the state signal of the switching control circuit in the slave state.

The switching control circuit further includes a sending interface module and a receiving interface module, and also includes

A frequency signal output control module is connected to the CPU and the sending interface module respectively;

A state control module, connected between the frequency signal output control module and the frequency signal detection module;

The frequency signal detection module is also connected to the receiving interface module and the frequency signal detection timer respectively;

A signal switching command module, connected between the CPU and the state control module;

The frequency signal detection timer is connected with the frequency signal detection module.

It may also include a state comparison module connected between the state control module and the CPU.

It may also include a state transition delay timer connected to the state control module.

It may also include a bidirectional interface module connected with the state control module.

The CPU may include a serial data output port and a serial data input port, and the serial data output port of the CPU in the master state is connected to the serial data input port of the CPU in the slave state.

The utility model sends a fixed-frequency signal as a connection signal between redundant devices through the main template, that is, a time-varying signal is used to represent the active state of the active template, which increases the reliability of the redundant switching control signal, so regardless of Redundant switching control can be completed immediately if the CPU failure of the main module is caused by any reason (for example: reset, crystal oscillator stop, power failure, program runaway, control port failure, etc.). Moreover, the correct identification of the template address can be realized at startup, and the master and slave can be determined through electrical competition between the master and slave templates. The sampling synchronization and diagnosis information transmission can be realized through the serial data channel between the redundant modules, and the host can also receive The switching operation command of the computer is used to switch, which further increases the operability of the redundant switching control. In addition, when the two redundant modules are working in the redundant state, when the main module is pulled out, the slave module will immediately switch to the active state if the square wave signal is not detected. When the two redundant modules are working in the redundant state, the The main template should not be affected when the slave template is used. When the same existing template is working in the master state, the master template inserted into the slave template will not be disturbed, so the live plugging and unplugging of the master and slave templates can be realized.

Description of drawings

Fig. 1 is a control block diagram of the utility model;

Fig. 2 is the functional block diagram of signal control circuit in the utility model;

Fig. 3 is a schematic diagram of state transition of the state control module of the present invention;

Fig. 4 is the flowchart of the utility model control process.

Detailed ways

As shown in Figure 1, the redundant switching control circuit of the present invention is composed of two symmetrical templates A and B. The structure and working process of each template are the same. The A template on one side is taken as an example below, including CPU and Signal control circuit, the CPU has four signal ports A1, A5, A6, A7, wherein A1 and A5 are connected to the signal control circuit, and the signal control circuit also includes three signal ports A2, A3, A4.

The functions of each signal port are as follows:

A1 signal port: output fixed frequency signal (F) under the control of A template CPU.

A2 signal port: Send the fixed frequency signal from the A1 signal port to the B3 signal port of the B template.

A3 signal port: Receive the status signal from the B2 signal port of the B template, and input it to the signal control circuit of the A template through the capacitor CA1. The A3 signal port is used to monitor the status of the B module.

A4 signal port: It is a two-way signal interface. When the A module is the master, the A4 interface is the input interface to receive the status information sent by the B module; when the A module is the slave, the A4 interface is the output port, which is in a high-impedance state, and sends the status information of the A module to the B module, here The status information can also use a fixed frequency signal.

A5 signal port: the interrupt request signal sent by the signal control circuit to the CPU. When the master and slave state information of A and B templates change, an interrupt request is sent to the CPU, and the CPU changes the running state of the A template according to the interrupt request.

A6 signal port: It is the serial data output port of A module, used to send serial data signal to the B7 signal port of B module, and exchange more information with B module.

A7 signal port: It is the serial data input port of the A module, used to receive the serial data signal sent by the B6 signal port of the B module. The fault diagnosis information between redundant modules is sent to each other through signals A6 and A7, and the redundant modules compare the diagnostic information and determine whether to perform redundant switching control operation according to the fault information. At the same time, the status information of the redundant template is sent to the upper computer through the active template.

The signal control circuit is shown in Figure 2, including:

The frequency signal output control module, when the state control module is in the main state, sends the fixed frequency signal sent by the received CPU through the sending interface module (i.e. port A2); when the state control module is a slave state, the above fixed frequency signal Prohibited from sending.

The state control module is used to send the current template as master or slave state signal.

The frequency signal detection module, through the signal sent by another template received by the receiving interface module (ie port A3), detects that the frequency of the received signal is within the effective range according to the detection reference signal sent by the frequency signal detection timer , indicating that the frequency signal is valid, so that the state control module is in the slave state; if it exceeds the set range, it is considered that the frequency signal disappears, and the detection result is sent to the state control module, so that the state control module enters the master state, and then all The above state control module controls to send out a fixed frequency signal.

The signal switch command module receives the switch signal sent by the CPU, sends a switch pulse to the state control module, and controls the state control signal module to perform state conversion;

The frequency signal detection timer is used to provide the detection reference of the frequency signal;

The state comparison module is used to compare the current state of the state control module with the current state of the CPU, send a state synchronization interrupt request to the CPU when the states are inconsistent, and clear the interrupt if they are consistent.

The state transition delay timer provides the required delay time during the state transition process of the state control module or when a state synchronization interrupt request is issued.

The bidirectional interface module is used to receive the status information of the slave template through the interface A4 when the status control module is in the master state, as an auxiliary judgment for judging whether the redundant template is in the slave state.

There are 5 states in the state control module, as shown in FIG. 3 , they are states "SA, SB, SC, SD, SE" respectively.

State "SA" is the state after the template has started. After the template is started, the CPU initialization work is completed, and then the start-up signal is sent to the signal control circuit, and the signal control circuit enters the state "SB".

The state "SB" is a state where the template applies to the CPU for slave synchronization through the state comparison module before the template enters the slave state. When the CPU completes the slave synchronization and sends a completed slave synchronization signal to the state comparison module, the state control module will enter the state "SC" and clear the interrupt signal at the same time.

State "SC" is the slave state of the template. The slave state is locked by the received fixed frequency signal of the master template. When it is detected that the fixed frequency signal of the master template disappears, the slave state "SC" enters the state "SD".

State "SD" is the state in which the template applies to the CPU for master synchronization through the status comparison module before it enters the master state. When the CPU completes the master synchronization and sends a completed master synchronization signal to the state comparison module, the state control module changes to the state "SE" and clears the interrupt signal at the same time. In state "SD" if a master signal is detected, the state will transition to state "SB".

State "SE" is the active state of the template. The main state allows the frequency signal output control module to output the main frequency signal through the sending interface module. At the same time, monitor whether the receiving interface module is still active. If only this machine is in the active state, lock the active state of the machine. When other main frequency signals are detected, the main state "SE" changes to the state "SB".

Since the step of the square wave signal is obvious and the frequency is easy to judge, the fixed frequency signal mainly adopts a square wave signal of fixed frequency. In this way, when the A template is in the active state, when a fixed frequency signal is sent from the A2 port, it can indicate that the A template exists, and it can also indicate that the A template is working normally. When port A4 receives a fixed frequency square wave, it also indicates that the B template exists, and at the same time indicates that it is working normally. Especially when a clamp fault occurs at the redundant connection port, the signal between the modules stays in the state of '0, 1', at this time, the '0, 1' signal cannot pass through the capacitor device, and the signal control circuit cannot receive the square wave signal , the signal control circuit sends an interrupt request to the CPU through the A5 port, and the corresponding template will take a corresponding redundant switching control operation. The A3 signal receiving end adopts capacitive isolation input, and then obtains the internal signal of the signal control circuit through the internal demodulation circuit. When the B module enters the slave state, the B2 port is closed and no square wave signal is sent. If the slave module is normal, send a square wave signal from the B4 port to the master module, indicating that the slave module has been installed and is working normally. If the slave module fails, the square wave signal sent from B4 disappears, and the master module sends the slave fault information to the host computer after receiving the information. The module running in the master state will exchange synchronization signals with the slave module through the A6 and A7 ports, so that the input/output channel sequence and time of the slave module will be synchronized with the master module, so that the sampling value or output value difference between redundant modules Minimized, greatly reducing disturbances due to large differences in input/output values when fast switching occurs.

With reference to the templates of A and B two redundant configurations shown in Figure 1, the working process of this embodiment is as shown in Figure 4:

Step 1: Start and delay. After the two modules start, after several consecutive delay times, wait for the signal of each port to stabilize.

When two redundant templates are started at the same time and the redundant templates enter the initial running state, each template is initialized, self-inspected, and mutually checked. Use the state A2 port to send a fixed frequency signal to another module, and the other B module will enter the slave state after receiving the signal port through the B3 port. At this time, the A template in the active state enters the state of receiving signals through the A4 port.

Step 2: Check the interface and address of the redundant template, check whether the interface and address between redundant templates A and B are correct. If the address is correct, go to step 4 to check the main template; if not, go to step 3.

Step 3: Stop the operation of the template, if there is an error in the initialization check, stop the operation of templates A and B and issue a local alarm.

Step 4: Determine whether the master template exists, if so, go to step 5 to apply for the slave template, otherwise go to step 10 to apply for the master template.

Step 5: Apply for the slave module, and send an interrupt request signal for the local module to enter the slave module to the CPU of module B.

Step 6: Whether the template enters the slave state, after template B receives a response from the slave application, make the B template transfer to step 8, that is, enter the slave state; otherwise, if the application does not receive a response, then transfer to step 7 to detect redundancy Whether the primary user exists.

Step 7: Whether the redundant master exists, if the B module has not entered the slave state, then further judge whether the corresponding A module's master status signal exists or disappears, and if it exists, go to step 10 to make the B module enter Main template application process.

Step 8: Slave template state: After B template gets the response of the slave template application, it enters the slave state.

Step 9: Monitor whether the master of the redundant module exists, and monitor the signal of the master module through the B3 port of the B module in the slave state. If the master signal disappears, go to step 10, that is, the slave module enters the master module to apply .

Step 10: Apply for the master module. If there is no master module or the master signal of the original A module disappears, the B module sends an interrupt application signal to the CPU to enter the master.

Step 11: Whether the template enters the active state. After the main application of the B template is responded, it enters the active state. If there is no response, go to step 12 to check whether the redundant active use, that is, the A template, has been restored.

Step 12: Restoration of redundant primary use. If template B has not yet entered the active state and the corresponding active status signal of template A is restored, then go to step 5 to make template B enter the slave template application process.

Step 13, the active template state. After the active application of the B template is responded, it enters the active state.

Step 14, monitor the active status of the redundant template, and the B template that enters the active state monitors the signal of the A template, and if the signal of the A template reappears, re-enter the slave template application process as the master B template.

Because the utility model adopts the fixed frequency signal as the connection signal between redundant devices, the reliability of the redundant switching control signal is increased, so no matter what causes the CPU failure of the main template (for example: reset, crystal vibration stop, drop Power failure, program runaway, control port line failure, etc.), the redundant switching control can be completed immediately. Moreover, the correct identification of the template address can be realized at startup, and the master and slave can be determined through electrical competition between the master and slave templates. The sampling synchronization and diagnosis information transmission can be realized through the serial data channel between the redundant modules, and the host can also receive The switching operation command of the computer is used to switch, which further increases the operability of the redundant switching control. In addition, when the two redundant modules are working in the redundant state, when the main module is pulled out, the slave module will immediately switch to the active state if the square wave signal is not detected. When the two redundant modules are working in the redundant state, the The main template should not be affected when the slave template is used. When the same existing template is working in the master state, the master template inserted into the slave template will not be disturbed, so the live plugging and unplugging of the master and slave templates can be realized.

The redundant switching control circuit provided by the utility model has been introduced in detail above, and the principle and implementation of the utility model have been explained by using specific examples in this paper. The description of the above embodiments is only used to help understand the utility model. method and its core idea; at the same time, for those of ordinary skill in the art, according to the idea of the utility model, there will be changes in the specific implementation and application scope. In summary, the content of this specification should not be understood as Limitations on the Invention.

Claims (6)

1. A redundant switching control circuit, comprising two symmetrical templates, is characterized in that: each template comprises CPU and switching control circuit respectively, and the signal port of the said switching control circuit in active state sends fixed frequency signal , connected to the signal port of the switching control circuit in the slave state for receiving the state signal. 2. The redundant switching control circuit according to claim 1, characterized in that: the switching control circuit further includes a sending interface module and a receiving interface module, and also includes A frequency signal output control module is connected to the CPU and the sending interface module respectively; A state control module, connected between the frequency signal output control module and the frequency signal detection module; The frequency signal detection module is also connected to the receiving interface module and the frequency signal detection timer respectively; A signal switching command module, connected between the CPU and the state control module; The frequency signal detection timer is connected with the frequency signal detection module. 3. The redundant switching control circuit according to claim 2, further comprising a state comparison module connected between the state control module and the CPU. 4. The redundant switching control circuit according to claim 2, further comprising a state transition delay timer connected to the state control module. 5. The redundant switching control circuit according to claim 2, further comprising a bidirectional interface module connected to the state control module. 6. The redundant switching control circuit according to any one of claims 1 to 5, wherein the CPU includes a serial data output port and a serial data input port, and the serial port of the CPU in the active state The data output port is connected with the serial data input port of the CPU in slave state.

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