CN201110962Y - Hardware Interpolation Circuit Based on Programmable Logic Device - Google Patents

Abstract

The utility model discloses a hardware interpolation circuit based on a programmable logic device, which includes a microprocessor that sends control information to the programmable logic device, and the programmable logic device converts the control signal into a serial control signal for controlling the motor driver , the programmable logic device receives the control, data and address signals sent by the microprocessor, and returns the status flag, adopts two-level cache processing for the above signals, and sends out control pulses synchronously, within the specified time, to ensure the uniform movement of the motor, The above-mentioned control pulse is generated in the programmable logic device according to a specific algorithm to realize the control of the motor driver; the circuit can program or repeatedly program the programmable logic device in order to reconstruct the logic function without changing the system hardware. Make hardware as flexible and easy to modify and upgrade as software. The adoption of this circuit has the characteristics of simple circuit structure, no discrete components, convenient logic modification, strong anti-interference performance and the like.

Description

Hardware Interpolation Circuit Based on Programmable Logic Device

technical field

The utility model relates to a hardware interpolation method based on programmable logic devices.

Background technique

At present, many CNC systems use the modulated pulse and direction signals as control signals to control the stepper motor and servo motor driver to control the speed and direction of the motor, and realize the movement of the CNC machine tool. For example, a stepper motor driver generally has three control input terminals: a step pulse signal, a direction level signal, and an enable level signal. When the control circuit controls the three input terminals accordingly, the control of the speed and direction of the stepping motor can be realized. However, in the past, these pulse generating circuits were all made of small discrete components, which had defects such as relatively single pulse waveform mode, not steep enough rising and falling edges of the pulse, and difficulty in realizing the circuit when the pulse width was required to be very narrow.

Contents of the invention

The technical problem to be solved by the utility model is to provide a hardware interpolation circuit based on a programmable logic device, which can conveniently reconfigure the logic function of the circuit and realize the pulse control of the numerical control system without changing the system hardware.

In order to solve the above-mentioned technical problems, the hardware interpolation circuit based on the programmable logic device of the utility model includes a microprocessor, a crystal oscillator circuit and a programmable logic device for sending a clock signal, and the microprocessor is connected with the programmable logic device and is sent in a parallel transmission mode. The control information is sent to the programmable logic device, and the programmable logic device converts the control signal into a serial control signal for controlling the motor driver. The programmable logic device includes a multiplexer, which also includes several double-buffered synchronous circuit modules, several equal pulse width DDA algorithm module, three-state control logic module and interpolation cycle generation module; the double buffer synchronous circuit module is composed of a first buffer and a second buffer in series, the first buffer is connected to the multiplexer, The second buffer is connected to the equal pulse width DDA algorithm module, the tri-state control logic module is connected to the multiplexer, and the interpolation period generation module is connected to the equal pulse width DDA algorithm module.

In the above-mentioned circuit, there is at least one of the double-buffering synchronous circuit module and the equal pulse width DDA algorithm module;

In this circuit, the equal pulse width DDA algorithm module is a digital integration circuit, and its output frequency is uniform, and the control pulse of equal duty cycle; the interpolation period generation module is composed of a frequency divider and a counter connected to the frequency divider , the pulse period generated by it determines the interpolation period of the pulse width digital integration algorithm of the circuit, and the period and duty ratio of the interpolation pulse can be set by changing the number of digits of the counter data.

Because the hardware interpolation circuit based on the programmable logic device of the utility model adopts the above-mentioned technical scheme, promptly the control pulse that draws by specific algorithm occurs through the programmable logic device, realizes the control to the motor driver; This method can be changed without changing In the case of circuit system design or circuit board, the programmable logic device is programmed or reprogrammed to reconfigure the logic function, so that the hardware becomes as flexible as software and easy to modify and upgrade. The use of programmable logic devices to implement hardware interpolators has the characteristics of simple structure, no discrete components, convenient logic modification, and strong anti-interference performance.

Description of drawings

Below in conjunction with accompanying drawing and embodiment the utility model is described in further detail:

Fig. 1 is a logical block diagram of the hardware interpolation circuit based on the programmable logic device.

Detailed ways

As shown in Fig. 1, the hardware interpolation circuit based on the programmable logic device of the present invention comprises microprocessor 1, crystal oscillator circuit 9 and programmable logic device that send clock signal, and microprocessor 1 connects programmable logic device and adopts parallel The transmission mode sends the control information to the programmable logic device, and the programmable logic device converts the control signal into a serial control signal for controlling the motor driver. The programmable logic device includes a multiplexer 2, which also includes a number of double-buffered synchronous circuit modules, Several equal pulse width DDA algorithm modules 5 and 8, tri-state control logic module 12 and interpolation cycle generating module; the double-buffer synchronous circuit module is composed of the first buffer 3 and the second buffer 4 in series, the first The buffer 3 is connected to the multiplexer 2, the second buffer 4 is connected to the equal pulse width DDA algorithm module 5, the tri-state control logic module 12 is connected to the multiplexer 2, and the interpolation period The generating module is connected to the equal pulse width DDA algorithm module 5 .

In above-mentioned circuit, described double-buffer synchronous circuit module and equal pulse width DDA algorithm module 5 are at least one;

In this circuit, the equal pulse width DDA algorithm module 5 is a digital integration circuit, and its output frequency is uniform, and the control pulse of the equal duty cycle; the interpolation period generation module is composed of a frequency divider 10 and a frequency divider 10 connected Composed of a counter 11, the pulse period generated by it determines the interpolation period of the pulse width digital integration algorithm of the circuit, and the period and duty cycle of the interpolation pulse can be set by changing the number of bits of the counter data.

The utility model receives the feed amount of each axis in an interpolation cycle obtained by the microprocessor through rough interpolation calculation, converts it into a feed pulse with uniform frequency and equal duty cycle, and outputs it to the motor driver of each axis.

In order to achieve the above purpose, based on the Very High Speed Integrated Circuit Hardware Description Language, the hardware interpolator circuit is realized by using complex programmable logic device (CPLD) or field gate array (FPGA), and the interpolation function is designed as A standard module has strong portability, improves the processing speed, reduces the area of the hardware circuit, ensures the reliability of the system, and can be upgraded at the same time, so as to realize complete openness and reconfigurability.

As shown in Figure 1, taking two axes as an example, the X-axis and Y-axis data sent by the microprocessor 1 are sent to the respective X-axis first buffer 3 and Y-axis first buffer 6 through the multiplexer 2 , and set flags FLAGX='1' and FLAGY='1' at the same time (1 means that the buffer has data, '0' means empty), and judge whether the X-axis and Y-axis buffer flags FLAG_B are '0', which is ' 0', the data in the first buffers 3 and 6 of the X-axis and Y-axis are sent to the respective second buffers 4 and 7, and the flag bits FLAG_B='1', FLAGX='0', FLAGY= '0'. FLAG_B='1' is used for synchronous judgment, indicating that the data of each axis is ready, and the next step is to send the X and Y axis data to the respective equal pulse width DDA modules 5 and 8 at the rising edge of the interpolation cycle EN, and FLAG_B = '0'. The equal pulse width DDA module converts the data into feed pulses PULSEX and PULSEY with uniform frequency and equal duty ratio through interpolation calculation, and at the same time, the highest bit of the data bit is used as the direction signal DIRX and DIRY of the motor, and is output to the X axis and Motor driver for the Y axis. There is also a three-state control logic module and an interpolation period EN generation module in the programmable logic device. The role of the three-state control logic module is to transmit data and return status signals to the processor, and the status signals are used to determine whether the data has been sent to their respective buffers. The function of the interpolation period EN generation module is to generate a fixed interpolation period signal.

In Figure 1, there are input signals, output signals, bidirectional signals and internal signals, which are:

Input signal Clock signal: CLK

Global reset signal: RESET

Chip select signal: CS

Address selection signal 0: A0

Address selection signal 1: A1

Read signal: RD

Write signal: WR

Output signal X-axis pulse signal: PULSEX

The direction signal of the X axis: DIRX

Pulse signal of Y axis: PULSEY

Direction signal of the Y axis: DIRY

Bidirectional signal data input and output signal: DATA

Internal signal clock frequency division signal: CLK_SIG_OUT

Generate signal at fixed time: EN

Data input signal: DATAIN

The status flag of the X-axis after the first-level cache: FLAGX

The data sent to the X axis after being latched: D_SIGX

Status flag bit after L2 cache: FLAG_B

The data sent to the X-axis after the first-level cache: D_BUFX

The data sent to the X-axis after the second-level cache: D_OUTX

The status flag of the Y axis after the first-level cache: FLAGY

The data sent to the Y axis after being latched: D_SIGY

The data sent to the Y axis after the first-level cache: D_BUFY

The data sent to the Y axis after the second-level cache: D_OUTY

In the logical block diagram shown in Figure 1, taking the two axes as an example, set DATAIN to be an 8-bit binary number, where the highest bit DATAIN[7] is the direction bit, and DATAIN[6..0] is the data bit. The CLK signal is generated by an external crystal oscillator, and can also be sent by a microprocessor. EN is used to set a fixed time. Its pulse width is set by the counter. By changing the number of counter data bits, the period and duty cycle of EN can be flexibly changed. CS, A0 and A1 are given by the microprocessor. When "A1&A0"<="00", the input data "DATAIN" is sent to the X-axis buffer. When "A1&A0"<="01", the input data "DATAIN" Feed into the Y-axis buffer. At the beginning, the data sent to the X-axis buffer is "10010000", and the data sent to the Y-axis buffer is "00010100". Within the specified EN cycle time, the X-axis pulse outputs the number of pulses output by "PULSEX" It is "0010000", which is 16 in decimal, and the number of pulses output by the Y-axis pulse output "PULSEY" is "0010100", which is 20 in decimal, and the pulse output is uniform. Because the pulse direction bit is set as the highest bit of the data bit, "DIRX"<='1', "DIRY"<='0', "DIRX" is displayed as high level, and "DIRY" is displayed as low level. By changing the value of the input data "DATAIN", the number and direction of the output pulses of the X-axis and Y-axis can be changed. By setting the address bits "A1&A0"<="10" and "A1&A0"<="11", simultaneous linkage of 3 axes and 4 axes can be realized. If the number of controlled axes is more than 4, only the corresponding extended address bits are sufficient.

The utility model utilizes a programmable logic device to realize a hardware interpolator circuit, and the interpolation function is designed as a standard module. The utility model has the advantages of simple structure, no discrete components, convenient logic modification and strong anti-interference performance.

It adopts hardware equal-time interpolation, and the number of interpolated pulses is sent out in one interpolation cycle. Compared with the traditional hardware interpolator, the use of equal time interpolation has higher requirements for data continuity and synchronization, while the traditional hardware interpolator performs interpolation after receiving the speed, starting point and end point coordinates sent by the host computer software After the interpolation is completed, the host computer is notified to perform the next interpolation operation by means of interrupt or polling.

This circuit adopts a double buffer structure, the data transmission is continuous, reliable, fast, without interrupt control, which reduces the workload of the software. The synchronization function is used to judge whether the data of each axis has been received, and output to the motor driver together after receiving, so that the synchronous operation of multi-axis motors can be accurately controlled.

Using the equal pulse width DDA algorithm, the data is shifted first, and then the ×2 operation is performed, and then the pulse frequency with uniform frequency and equal duty cycle is output after the traditional DDA interpolation calculation. The realization is simple, and the truncation error of the pulse is eliminated.

Claims (4)

1. A hardware interpolation circuit based on a programmable logic device, including a microprocessor, a crystal oscillator circuit that sends a clock signal, and a programmable logic device. The microprocessor is connected to the programmable logic device and uses parallel transmission to send control information to the programmable logic device. Programmable logic device, the programmable logic device converts the control signal into a serial control signal for controlling the motor driver, the programmable logic device includes a multiplexer, and it is characterized in that: the programmable logic device also includes several double buffer synchronous circuit modules, several Equal pulse width DDA algorithm module, three-state control logic module and interpolation cycle generation module; the double buffer synchronous circuit module is composed of a first buffer and a second buffer connected in series, and the first buffer is connected to the multi-channel selector, the second buffer is connected to the equal-pulse width DDA algorithm module, the tri-state control logic module is connected to the multiplexer, and the interpolation cycle generation module is connected to the equal-pulse width DDA algorithm module . 2. The hardware interpolation circuit based on programmable logic device according to claim 1, characterized in that there is at least one double-buffer synchronous circuit module and equal pulse width DDA algorithm module. 3. The hardware interpolation circuit based on programmable logic devices according to claim 1, characterized in that: the equal pulse width DDA algorithm module is a digital integration circuit, which outputs control pulses with uniform frequency and equal duty cycle. 4. The hardware interpolation circuit based on programmable logic devices according to claim 1, characterized in that: the interpolation cycle generation module is composed of a frequency divider and a counter connected to the frequency divider, and the output cycle pulse input Equal pulse width DDA algorithm module.

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