CN201061129Y - Electric power abnormity protection circuit - Google Patents

Abstract

The utility model relates to an electric power abnormal protection circuit, it includes an electric power monitoring unit, a pressure Drop correction unit, a slump monitoring unit, a delay unit and a cover delay unit, this electric power abnormal protection circuit utilizes the input power average value of monitoring this power supply ware and judges whether take place the phenomenon of voltage sag (Brown out), in addition, whether take place slump (Drop out) phenomenon is judged to the voltage of an output capacitance's in the merit reason correction unit of monitoring this power supply ware, and each unit that makes this power supply ware when electric power is unusual can be according to the time of postponing according to the preface and close, reach the function of protection circuit subassembly and computer.

Description

Power abnormality protection circuit

technical field

The utility model relates to an electric power abnormality protection circuit, in particular to a protection circuit for monitoring the input power of a power supply and deciding to shut down the timing of the power supply when the input power is abnormal.

Background technique

As we all know, the power supply receives AC power and converts it into stable DC power for the stable operation of the computer, but ordinary users will inevitably encounter power outages or power trips, so today's power supplies will take into account the function of voltage abnormality protection; Abnormal conditions of AC power are mainly divided into two categories, one of which is voltage drop (Drop out). As a result, it cannot be used. Usually, the power equipment is damaged or a large load near the power end suddenly starts, causing the voltage to drop suddenly (such as a large-capacity motor suddenly starting). Another type of voltage abnormality is brown out. Slowly drop below the normal voltage, so that the output of the electrical appliance will drop to off (such as the light gradually dimming and extinguishing). In the above two abnormal voltage states, the power supply must generate corresponding delays and turn off timings. Protect the computer and the power supply itself, and the traditional utility model such as the "improved switching power supply" in Taiwan Patent Publication No. 501830, which has the ability to judge abnormal voltage, the previous patent set a The delay time of over-low voltage (set to 4 seconds in the patent), when the over-low voltage condition does not exceed 4 seconds, the delay unit will lengthen the switching element Q11 of the power correction unit in order to maintain the normal operation of the power supply The conduction time keeps the voltage of a capacitor C53 at the output end of the power correction circuit unchanged, achieving the effect of maintaining the output, but prolonging the conduction period of the switching element will cause the switching element Q11 to overheat and damage, so it is often too low voltage When the situation occurs, the circuit may be damaged within 4 seconds, and it is difficult to achieve the protective effect. In addition, because the previous patent did not consider the short-term voltage sag, because the voltage sag occurs quickly, the previous patent has no time to respond. The phenomenon of voltage bouncing will occur on the output, which will damage the working computer; therefore, the mechanism of the previous patents to deal with the phenomenon of voltage drop (Drop out) and voltage drop (Brown out) is still incomplete and needs to be further improved .

Utility model content

In view of the fact that the above-mentioned traditional utility model does not fully have a protection mechanism for various power abnormalities, the primary purpose of the utility model is to propose a protection circuit to avoid the phenomenon of voltage drop (Drop out) and voltage drop (Brown out) damage to the power supply or the computer.

The utility model relates to a power abnormality protection circuit, which is used to control the shutdown sequence of a power supply when the voltage is abnormal. The power supply includes a rectifier unit, a power factor correction unit, a transformer, a main power output unit and A standing power output unit, and also includes a power factor correction control unit, a pulse width modulation unit, a standing power control unit and the power abnormal protection circuit, the power abnormal protection circuit includes a power monitoring unit, a voltage drop correction unit, a voltage sag monitoring unit, a delay unit, and a coverage delay unit, by monitoring the average value of the input power of the power supply to determine whether a voltage drop (Brown out) phenomenon occurs; in addition, monitoring the power factor correction unit The voltage of an output capacitor judges whether a voltage drop (Drop out) phenomenon occurs, and the voltage drop correction unit makes the power factor correction control unit generate a signal for correcting the voltage output when the voltage drop occurs, and generates a delay time to make the power supply Maintain the work, and due to the downward correction of the voltage output, the working cycle of the switching element of the power factor correction unit is shortened, and the passing current is reduced to reduce the conduction loss. In addition, the voltage drop can reduce the switching loss of the switching element and protect the switch The components will not be damaged. In addition, when the voltage drops, the voltage drop monitoring unit directly shuts down the power factor correction control unit and the pulse width modulation unit, and delays shutting down the standing power control unit. If the component is damaged due to restarting too quickly, the overlay delay unit will ensure that the power correction control unit will not start within a certain period of time, so that the abnormal input voltage can maintain work or Closed to achieve the function of protecting circuit components and computers.

Description of drawings

Figure 1 is a circuit diagram of the power supply,

Fig. 2 is a block diagram of the first embodiment of the utility model,

Figure 3 is a timing waveform diagram of a voltage sag,

Figure 4 is a timing waveform diagram of a voltage drop,

Fig. 5 is a block diagram of the second embodiment of the present invention.

Detailed ways

Relevant detailed description and technical content of the present utility model, now with regard to coordinating accompanying drawing, explain as follows:

Please refer to Fig. 1, the utility model is a power abnormality protection circuit 7, which is used to control the shutdown sequence of a power supply when the voltage is abnormal, the power supply includes a rectifier unit 1, a power factor correction unit 2, a Transformer 3, a main power output unit 4 and a standing power output unit 5, the AC power is input into the rectification unit 1 and then rectified and converted into an input power Vac, the input power Vac is adjusted by the power factor correction unit 2 to adjust the voltage and current After the phase, the power is transmitted to the main power output unit 4 and the standing power output unit 5 through the transformer 3, wherein the power factor correction unit 2 has an output capacitor 21 for maintaining the output voltage of the power factor correction unit 2; The power factor correction unit 2, the main power output unit 4 and the standing power output unit 5 are respectively controlled by the power factor correction control unit 61, the pulse width modulation unit 62 and the standing power control unit 63. The power factor correction control unit 61. The pulse width modulation unit 62 and the standing power control unit 63 can be integrated into an integrated circuit 6 or implemented with a general circuit, and the power abnormality protection circuit 7 of the present invention can also be integrally integrated in the integrated circuit 6, The power abnormal protection circuit 7 includes a power monitoring unit 71, a voltage drop correction unit 72, a voltage drop monitoring unit 73, a delay unit 74 and a coverage delay unit 75; the power monitoring unit 71 is used to receive the input power Vac obtains an input power average value Vav by connecting a capacitor C3, and outputs a voltage drop signal to the voltage drop correction unit 72 when the input power average value Vav drops and is lower than an over-low voltage judgment value. The correction unit 72 outputs an average voltage normal signal to the enabling input terminal ENA1 of the power factor correction control unit 61 during normal startup and is connected to the power monitoring unit 71, and generates a reference voltage signal when receiving the voltage drop signal and sends it to to the power factor correction control unit 61, and generate a first delay time T1, and keep each unit continuously working within the first delay time T1, and stop if the voltage drop signal is continuously received beyond the first delay time T1 Outputting the average voltage normal signal makes the power factor correction control unit 61 shut down; the voltage sag monitoring unit 73 is used to obtain the voltage of the output capacitor 21 and set a cut-off voltage value, thereby judging whether the voltage of the output capacitor 21 is less than The cut-off voltage value, when the voltage of the output capacitor 21 is greater than the cut-off voltage value, an input voltage normal signal is output to the delay unit 74, the coverage delay unit 75 and the enable input terminal ENA2 of the pulse width modulation unit 62, Make the pulse width modulation unit 62 work normally, and the delay unit 74 and the coverage delay unit 75 respectively transmit the input voltage normal signal to the enable input terminal ENA3 of the standing power control unit 63 and the power factor correction control unit 61 The enabling input terminal ENA1 of the ENA1 makes it work normally, wherein the standing power control unit 63 is used to output a control signal of the standing power output unit 5 (such as the STBY waveform in Figure 3 and Figure 4), and the input voltage normal signal The power factor correction control unit 61 needs to be input to the power factor correction control unit 61 at the same time as the average voltage normal signal, which can be regarded as setting an AND gate at the front end of the enable input terminal ENA1 of the power factor correction control unit 61 (AND GATE), to receive the input voltage normal signal and the average voltage normal signal, if the voltage of the output capacitor 21 is less than the cut-off voltage value, the voltage sag monitoring unit 73 stops the input voltage normal signal, so that the pulse The wide modulation unit 62 stops working immediately, and the delay unit 74 makes the standing power control unit 63 turn off after a second delay time T2, and the coverage delay unit 75 makes the power factor correction control unit 61 turn off immediately and in a The third delay time T3 must not be activated, wherein the second delay time T2 is shorter than the third delay time T3, forming a shutdown protection sequence of the power supply during voltage drop and voltage dip.

Please refer to FIG. 2 , which shows the first embodiment of the utility model. The power monitoring unit 71 includes a buffer unit 711 and an over-low voltage detection unit 712. In addition, the voltage drop correction unit 72 includes a digital counter 721 and A digital/analog converter 722, the buffer unit 711 obtains the input power Vac, and the output terminal of the buffer unit 711 generates the input power average value Vav through an external capacitor C3, the over-low voltage detection unit 712 is set to have an overvoltage The low-voltage judgment value is compared with the over-low voltage judgment value by using the input power average value Vav, and when the input power average value Vav is lower than the over-low voltage judgment value, the voltage drop signal is output to the digital counter, and the digital counter 721 has An output terminal that outputs an average voltage normal signal during normal startup, and has a binary counting function of four output bits B0, B1, B2, B3. When receiving the voltage drop signal, the digital counter 721 is based on the first frequency signal clk1 The frequency starts counting up, so that the four output bits B0, B1, B2, and B3 are sequentially output according to the binary up counting, and the higher output bits B1, B2, and B3 are connected to the digital/analog converter 722, and the digital/analog The converter 722 receives the signals of the output bits B1, B2, B3 and converts them into analog reference voltage signals and sends them to the power factor correction control unit 61, so that the power factor correction control unit 61 can adjust the voltage of the output capacitor 21 , so as to reduce the output to prevent the switch element SW1 of the power correction unit 2 from being burnt due to overloading, wherein the output bit B0 of the lowest bit of the digital counter 721 is grounded to avoid over-sensitivity, when the output bits B0, B1, B2, and B3 are all When outputting a high potential, it means that the digital counter 721 has counted to the upper limit. At this time, the digital counter 721 stops outputting the average voltage normal signal so that the power factor correction control unit 61 is turned off, and the output bits B0, B1, B2, and B3 are counted from zero The time required to reach the upper limit forms a first delay time T1; if the over-low voltage detection unit 712 stops outputting the voltage drop signal when the digital counter 721 is counting up, then the digital counter 721 will be based on the second frequency signal clk2 The reciprocal frequency returns to zero, wherein the frequency of the second frequency signal clk2 is higher than the frequency of the first frequency signal clk1, so that the speed at which the digital counter 721 returns to zero is higher than the speed of counting up, so that the power factor correction control unit 61 can Quickly restore the normal output voltage of the power factor correction unit 2; the voltage drop monitoring unit 73 is connected to the power factor correction control unit 61, and detects the voltage of the output capacitor 21 through the power factor correction control unit 61, and A cut-off voltage value is set to determine whether the voltage of the output capacitor 21 is less than the cut-off voltage value, and when the voltage of the output capacitor 21 is greater than the cut-off voltage value, an input voltage normal signal is output to a delay unit 74, a coverage delay unit 75 and the pulse width modulation unit 62 to make the pulse width modulation unit 62 work normally, and the delay unit 74 and the coverage delay unit 75 respectively transmit the input voltage normal signal to the standing power control unit 63 and the power factor The correction control unit 61 makes it work normally. If the voltage of the output capacitor 21 is less than the cut-off voltage value, the voltage sag monitoring unit 73 stops the input voltage normal signal, so that the pulse width modulation unit 62 stops working, and the delay The unit 74 makes the standing power control unit 63 turn off after the second delay time T2, and the coverage delay unit 75 makes the power factor correction control unit 61 turn off immediately and cannot be started within the third delay time T3, forming the power supply The shutdown protection sequence of the supply during voltage drop and voltage sag.

Please refer to FIG. 2 and FIG. 3 at the same time. FIG. 3 is a timing waveform diagram of the utility model when the voltage drops sharply, wherein B+ represents the voltage of the output capacitor 21. When the input power Vac has a brief voltage drop during the Ta period, the The digital counter 721 starts counting and the reference voltage generated by the digital/analog converter 722 makes the power factor correction control unit 61 adjust the voltage of the output capacitor 21, and the counting speed of the digital counter 721 is determined by the first frequency signal The frequency of clk1 is determined. After the input power Vac is restored, the speed at which the digital counter 721 counts down to zero is determined by the frequency of the second frequency signal clk2; The cut-off voltage value set by the drop monitoring unit 73 (as shown in the timing point A in the figure) is determined to be a voltage sag. At this time, the voltage sag monitoring unit 73 stops outputting the input voltage normal signal to make the pulse width modulation unit 62 Stop immediately, and the delay unit 74 makes the standing power control unit 63 delay a second delay time T2 and then close (as shown in the timing sequence B point), the covering delay unit 75 then produces a shielding function to make the power factor The calibration control unit 61 cannot be activated within the third delay time T3, so that the integrated circuit 6 can be restarted only after the third delay time T3 passes.

Please refer to Fig. 2 and Fig. 4, Fig. 4 is a timing waveform diagram of the utility model when the voltage drops, when the input voltage average value Vav is lower than the over-low voltage judgment value Vu set by the over-low voltage detection unit 712, the digital counter 721 starts counting up, and the digital/analog converter 722 continues to revise the reference voltage value so that the power factor correction control unit 61 lowers the voltage of the output capacitor 21 until the digital counter 721 reaches the value after the first delay time T1. upper limit, so that the digital counter 721 stops outputting the average voltage normal signal to make the power factor correction control unit 61 shut down immediately (as shown in timing point C in the figure), after the power factor correction control unit 61 is turned off, the power factor correction unit 2 also Stop the action, make the voltage of the output capacitor 21 drop, and after a maintenance time Th, the voltage of the output capacitor 21 drops to the cut-off voltage value set by the voltage drop monitoring unit 73 (as shown in the timing point D in the figure), and then After the second delay time T2, the standing power control unit 63 is turned off (as shown in the timing point E); therefore, the utility model can generate enough buffer time to wait for the low voltage to rise without damaging the components, and can be used in After the buffer time, each unit is turned off sequentially, and is used to control the power factor correction control unit 61 not to start within the third delay time T3, so as to prevent the computer system from causing errors due to the power supply being turned on and off too quickly.

Please refer to FIG. 5 , the voltage drop correction unit 72 of the present invention can be formed by a ramp wave generator 723 and a voltage drop detection unit 724, wherein the ramp wave generator 723 includes a first current source and a second current source And an integrating capacitor Ct, the voltage drop signal is connected to the first current source and the second current source at the same time and controls the opening and closing of the first current source and the second current source, and besides the second current source is connected a non The gate (NOTGATE) staggers the startup timing of the first current source and the second current source, and the integrating capacitor Ct is connected between the first current source and the second current source. When the first current source is started, the The integrating capacitor Ct is charged, and the integrating capacitor Ct can be discharged when the second current source is started, and a slope-shaped reference voltage signal is formed through the charging and discharging of the integrating capacitor Ct, and the voltage drop detection unit 724 outputs the average voltage signal when starting normally. Voltage normal signal, and set a low-voltage monitoring value, when the over-low voltage detection unit 712 outputs the voltage drop signal to make the first current source work, the integration capacitor Ct is charged to form a ramp-shaped reference voltage signal, the reference voltage A first delay time T1 is formed between the signal rising and reaching the low-voltage monitoring value. When the reference voltage signal climbing reaches the low-voltage monitoring value, the voltage drop detection unit 724 stops outputting the average voltage normal signal, so that the power factor correction control unit 61 is turned off, and after the voltage drop signal disappears, the first current source is turned off and the second current source is started, and the second current source discharges the integrating capacitor Ct so that the ramp-shaped reference voltage signal slides back to zero, and the second The output of the current source is greater than the output of the first current source, so the discharge speed of the integrating capacitor Ct is faster than the charging speed, so that the power factor correction control unit 61 recovers the normal output of the power factor correction unit 2 at a faster speed. Voltage.

The above descriptions are only preferred embodiments of the present utility model, and are not intended to limit the present utility model. In the above embodiments, the present utility model can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present utility model shall be included in the protection scope of the present utility model.

Claims (10)

1. A power abnormality protection circuit, which is used to control the shutdown sequence of the power supply when the voltage is abnormal. After receiving the input power, the power supply passes through the rectification unit (1), the power factor correction unit (2), and passes through the transformer ( 3) transmitting power to the main power output unit (4) and the standing power output unit (5), wherein the power factor correction unit (2) has an output capacitor (21) to maintain the power factor correction unit (2) output voltage, and the power supply also includes a power factor correction control unit (61), a pulse width modulation unit (62), a standing power control unit (63) and a power abnormality protection circuit (7), the power factor The correction control unit (61) controls the work of the power factor correction unit (2), and the pulse width modulation unit (62) and the standing power control unit (63) respectively control the main power output unit (4) And the standing power output unit (5), characterized in that the power abnormality protection circuit (7) includes: A power monitoring unit (71), configured to receive the input power and obtain an average value of the input power, and output a voltage drop signal when the average value of the input power drops; A voltage drop correction unit (72), configured to output an average voltage normal signal to the power factor correction control unit (61) and connected to the power monitoring unit (71) when the average value of the input power is normal. When the average value drops, the reference voltage signal is generated by receiving the voltage drop signal and sent to the power factor correction control unit (61), and the output of the average voltage is stopped after receiving the voltage drop signal continuously for a first delay time A normal signal makes the power factor correction control unit (61) shut down; A voltage sag monitoring unit (73), configured to obtain the voltage of the output capacitor (21) and set a cut-off voltage value, thereby judging whether the voltage of the output capacitor (21) is less than the cut-off voltage value, when the When the voltage of the output capacitor (21) is greater than the cut-off voltage value, the input voltage normal signal is output to the delay unit (74), the coverage delay unit (75) and the pulse width modulation unit (62), so that the pulse width modulation The variable unit (62) works normally, and the delay unit (74) and the coverage delay unit (75) transmit the input voltage normal signal to the standing power control unit (63) and the power factor correction control unit respectively (61), and then make it work normally, if the voltage of the output capacitor (21) is less than the cut-off voltage value, the voltage sag monitoring unit (73) stops the input voltage normal signal, so that the pulse width The modulation unit (62) stops working, and the delay unit (74) makes the standing power control unit (63) turn off after a second delay time, and the covering delay unit (75) makes the power factor correction The control unit (61) is immediately shut down and cannot be started within the third delay time, forming a shutdown protection sequence of the power supply during voltage drop and voltage drop. 2. The power abnormality protection circuit according to claim 1, wherein the second delay time is shorter than the third delay time. 3. The power abnormality protection circuit according to claim 1, characterized in that, the power monitoring unit (71) includes a buffer unit (711) and an over-low voltage detection unit (712), and the buffer unit (711) is used for The input power is received and the average value of the input power is generated, and the over-low voltage detection unit (712) is configured to output a voltage drop signal when the average value of the input power drops. 4. The electric power abnormality protection circuit according to claim 3, characterized in that, the over-low voltage detection unit (712) is set with an over-low voltage judgment value, and the average value of the input power is compared with the over-low voltage judgment value , outputting the voltage drop signal when the average value of the input power is lower than the over-low voltage judgment value. 5. The power abnormality protection circuit according to claim 1, characterized in that, the voltage drop correction unit (72) includes a digital counter (721) and a digital/analog converter (722), and the digital counter (721) When starting normally, a high-level voltage is sent as the average voltage normal signal, and the digital counter (721) starts counting when it receives the voltage drop signal, and sends the count value to the digital/analog converter (722 ) and converted into the reference voltage signal, when the digital counter (721) has counted up to the upper limit, it stops outputting the average voltage normal signal, and after the voltage drop signal disappears, the digital counter (721) reverses Counts down to zero. 6. The electric power abnormality protection circuit according to claim 5, characterized in that, the counting speed of the digital counter (721) is determined by the frequency of the first frequency signal, and the speed of reverse reciprocal return to zero is determined by the second frequency The frequency of the signal is determined. 7. The power abnormality protection circuit according to claim 6, wherein the frequency of the second frequency signal is higher than that of the first frequency signal. 8. The power abnormality protection circuit according to claim 1, characterized in that, the voltage drop correction unit (72) comprises a ramp generator (723) and a voltage drop detection unit (724), the ramp generator (723) generating a ramp wave as the reference voltage signal after receiving the voltage drop signal, and the voltage drop detection unit (724) outputs the average voltage normal signal when starting normally, and sets a low voltage monitoring value, When the ramp-shaped reference voltage signal climbs to the low-voltage monitoring value, the voltage drop detection unit (724) stops outputting the average voltage normal signal, and after the voltage drop signal disappears, the ramp generator (723) Make the ramp down. 9. The power abnormal protection circuit according to claim 8, characterized in that, the ramp generator (723) includes a first current source, a second current source and an integrating capacitor, and the voltage drop signal is connected to the The first current source and the second current source control the opening and closing of the first current source and the second current source. In addition, the second current source is connected with a NOT gate and makes the first current source and the The starting sequence of the second current source is staggered, the integrating capacitor is connected between the first current source and the second current source, the integrating capacitor starts to charge when the first current source is started, and the second current When the source is started, the integral capacitor is discharged, and a ramp-shaped reference voltage signal is formed through the charge and discharge of the integral capacitor. 10. The power abnormality protection circuit according to claim 9, wherein the output of the second current source is greater than the output of the first current source.

Images