CN201036009Y - Error-correcting information processing apparatus in BCH error-correcting technique - Google Patents
Error-correcting information processing apparatus in BCH error-correcting technique Download PDFInfo
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- CN201036009Y CN201036009Y CNU200720006889XU CN200720006889U CN201036009Y CN 201036009 Y CN201036009 Y CN 201036009Y CN U200720006889X U CNU200720006889X U CN U200720006889XU CN 200720006889 U CN200720006889 U CN 200720006889U CN 201036009 Y CN201036009 Y CN 201036009Y
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Abstract
The utility model relates to a coder carrying out error detection or calibration with redundant codes expressed in data, in particular to an information processing device for error correction in BCH error correcting technique, and the coder is commonly used for a flash memory system. The utility model has the key point to provide an information processing device for error correction in the BCH error correcting technique, thus causing that information processing for the error correction and reading of information data can be conducted separately when data are read from the flash memory system. After a page of or a plurality of pages of data are read, the error correction for the read information data through the gained error correcting information is conducted at a time; thereby continuously reading the data from the flash memory system can be achieved, the operation can be simplified and the speed of reading the data from the flash memory system can be increased.
Description
Technical field
The utility model relates to a kind ofly makes the code device of error-detecting or correction with the redundanat code in the data representation, the error correction information treating apparatus in particularly a kind of BCH error correcting technique, and it generally is used for flash-memory storage system.
Background technology
BCH code is an important subclass of reflected code, and it has the ability of entangling a plurality of mistakes, and BCH code has tight algebraic process, is to study a most thorough class sign indicating number at present.Between its generator polynomial and the minimum distance confidential relation is arranged, people can be easy to construct BCH code according to desired error correcting capability, and their code translator is also realized easily, is to use a most general class sign indicating number in the linear block codes.
In the prior art, write flash memory in data and carry out Bose-Chaudhuri-Hocquenghem Code simultaneously, promptly after having write information bit, obtain one group of check bit, after information bit, form complete BCH code word, just a check code thereby follow.When reading the data that are stored on the flash memory, need be that check code is decoded to coded data, thereby obtain the corresponding error correction information of information data, in the time of reading of data from flash-memory storage system, this error correction information can be corrected in the data of the mistake in the error correcting capability scope.
Yet, when reading of data from flash-memory storage system, whenever run through the information bit of 512 bytes, and then wanting the address substitute pointer to read the corresponding check sign indicating number decodes, to obtain error correction information, therefore during the reading of every page data, to change repeatedly constantly conversion on information bit and check bit to the address pointer of flash-memory storage system operation; And when carrying out correction process, it also is one side reading of data, utilize the resulting error correction information of BCH demoder that data are carried out correction process on one side, complicated operation, reading and writing data speed is slow, particularly in the SOC system, carries out reading of data with DMA mostly, the reading destination address and need influence the efficient and the transmission speed of bus especially of conversion flash memory from new preparation DMA register.
Utility model constitutes
The purpose of this utility model is that providing a kind of according to the deficiencies in the prior art part can carry out disposable operation respectively to information code and error correction information, makes the error correction information treating apparatus in the fast BCH error correcting technique of data reading speed.
The utility model is realized by following approach:
Error correction information treating apparatus in the BCH error correcting technique, include flash interface control device and BCH demoder, a reading control of flash interface control device is connected with flash-memory storage system, another drive controlling output terminal is connected with the transmission of BCH demoder, the input end of BCH demoder is connected with flash-memory storage system, and its structural feature is, also includes an error correction information storer, its drive controlling end connects the flash interface control device, and input end is connected with the output terminal of BCH demoder.
When reading of data in flash-memory storage system, storage system will begin to read information data corresponding check sign indicating number by flash interface control device triggering BCH demoder and decode, and with decoded results, it is error correction information, be kept in the error correction information storer, can carry out uninterruptedly just reading of flash memory system data like this, after the information data that has read some, the flash interface control device triggers the error correction information storer, error correction information in the error correction information storer is read out, pairing information data is carried out correction process.Like this, when flash-memory storage system was carried out read operation, reading of the processing of error correction information and information data can separate processes, can realize flash-memory storage system is read the continuity of information data, thereby simplify operation, has accelerated the reading speed of data.
Error correction information treating apparatus described in the utility model can further be specially:
Include data processor, counting assembly, comparison means and driving flip flop equipment that connects in regular turn and the standard apparatus that is connected with the reference edge of comparison means in the flash interface control device, wherein data processor connects flash-memory storage system and BCH demoder, drives flip flop equipment and then connects the error correction information storer.
The data processor of flash interface control device is being handled the data while of being read, data message is sent to counting assembly, counting assembly will calculate the information bit that writes, and result that comparison means is counted counting assembly and the reference value in the standard apparatus compare, after count results reaches reference value, comparison means is exported a control signal and is given the driving flip flop equipment, trigger the error correction information storer by driving flip flop equipment, the error correction information storer sends error correction information wherein to data processor, and the corresponding informance data that read are carried out correction process.
Like this can be as required the reference value of standard apparatus be provided with, thus the batch size that control is handled data, as a page data or two page datas, in addition more.What that is to say the counting assembly counting is the size of data volume, after a certain amount of data are whenever read in control, uses error correction information that the data that read are carried out correction process.
The utility model can also further be specially:
Also include a check code storer, the BCH demoder is connected with flash-memory storage system by this check code storer.
The check code storer is result---the check code of encoding by the Bose-Chaudhuri-Hocquenghem Code device when writing data toward flash-memory storage system before in order to storage, the BCH demoder just can directly read the calculating of decoding of corresponding check sign indicating number from the check code storer like this, and need not carry out read operation to flash-memory storage system, further simplified the step of whole read operation, made the speed that reads more quick, simple.
Check code storer and error correction information storer all are installed in the same storer, have two storage spaces in this storer, store check code and error correction information respectively.
Like this, two kinds of storeies are installed in the same storer, can save hardware cost and economize on hardware space.
Flash interface control device, BCH demoder, error correction information storer all are included in the chip that a model is RK435D.
Flash interface control device, BCH demoder, error correction information storer are integrated in the chip, and this chip has been realized above-mentioned three's purposes.The model of chip can have multiple, and it is as a reference a kind of that this instructions provides.
In sum, main points of the present utility model have been to provide the error correction information treating apparatus in a kind of BCH error correcting technique, make when reading of data in flash-memory storage system, the processing of error correction information and the branch that reads of information data can be come, after the information data of finishing one page or plural number page or leaf reads, again by resulting error correction information to the disposable correction process of carrying out of the information data that is read, thereby realize the continuity that flash-memory storage system reads data, make simple to operateization, and improved the speed that flash-memory storage system reads data.
Description of drawings
Figure 1 shows that the structural representation of error correction information treating apparatus in the BCH error correcting technique described in the utility model;
Figure 2 shows that the circuit structure diagram of error correction information treating apparatus in the BCH error correcting technique described in the utility model;
Below in conjunction with embodiment the utility model is described further.
Specific embodiment
Most preferred embodiment:
With reference to accompanying drawing 1, error correction information treating apparatus in the BCH error correcting technique, comprise flash interface control device, check code storer, error correction information storer and BCH demoder, a reading control of flash interface control device is connected with a flash-memory storage system, another drive controlling end is connected with the transmission of BCH demoder, and the output control terminal of error correction information storer connects the flash interface control device, input end is connected with the output terminal of BCH demoder, and the input end of BCH demoder is connected with flash-memory storage system by the check code storer; Include data processor, counting assembly, comparison means and driving flip flop equipment that connects in regular turn and the standard apparatus that is connected with the reference edge of comparison means in the flash interface control device, wherein the reading control of data processor connects flash-memory storage system, the drive controlling end connects the BCH demoder, drives the driving trigger end that flip flop equipment then connects the error correction information storer.
With reference to accompanying drawing 2, flash interface control device, Bose-Chaudhuri-Hocquenghem Code device and check code register all are integrated in the chip, and the model of this chip is RK435D.Flash-memory storage system then includes the storage chip that a model is HY27UF082G2M, its with the connection of chip RK435D as shown in Figure 2: 1,2,3,4,6,11,12,23,24 pin of RK435D are corresponding respectively to be connected with 7,8,18,19,1,9,10,17,16 pin of HY27UF082G2M, connect according to the title of the leg of two chips is corresponding, data terminal D0～D7 of RK435D in addition, promptly 36～43 pin are corresponding respectively is connected with 41～44 pin are corresponding with the data terminal 29～32 of flash chip HY27UF082G2M.
It is same as the prior art that the utility model is not stated part.
Claims (5)
1.BCH the error correction information treating apparatus in the error correcting technique, include flash interface control device and BCH demoder, a reading control of flash interface control device is connected with flash-memory storage system, another drive controlling output terminal is connected with the transmission of BCH demoder, the input end of BCH demoder is connected with flash-memory storage system, it is characterized in that, also includes an error correction information storer, its drive controlling end connects the flash interface control device, and input end is connected with the output terminal of BCH demoder.
2. the error correction information treating apparatus in the BCH error correcting technique according to claim 1, it is characterized in that, include data processor, counting assembly, comparison means and driving flip flop equipment that connects in regular turn and the standard apparatus that is connected with the reference edge of comparison means in the flash interface control device, wherein data processor connects flash-memory storage system and BCH demoder, drives flip flop equipment and then connects the error correction information storer.
3. the error correction information treating apparatus in the BCH error correcting technique according to claim 1 is characterized in that, also includes a check code storer, and the BCH demoder is connected with flash-memory storage system by this check code storer.
4. the error correction information treating apparatus in the BCH error correcting technique according to claim 3, it is characterized in that, check code storer and error correction information storer all are installed in the same storer, have two storage spaces in this storer, store check code and error correction information respectively.
5. the error correction information treating apparatus in the BCH error correcting technique according to claim 1 is characterized in that, flash interface control device, BCH demoder, error correction information storer all are included in the chip that a model is RK435D.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU200720006889XU CN201036009Y (en) | 2007-04-24 | 2007-04-24 | Error-correcting information processing apparatus in BCH error-correcting technique |
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| Application Number | Priority Date | Filing Date | Title |
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| CNU200720006889XU CN201036009Y (en) | 2007-04-24 | 2007-04-24 | Error-correcting information processing apparatus in BCH error-correcting technique |
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| CN201036009Y true CN201036009Y (en) | 2008-03-12 |
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| CNU200720006889XU Expired - Fee Related CN201036009Y (en) | 2007-04-24 | 2007-04-24 | Error-correcting information processing apparatus in BCH error-correcting technique |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114237969A (en) * | 2021-11-09 | 2022-03-25 | 珠海亿智电子科技有限公司 | Method and device for parallel BCH error correction decoding |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114237969A (en) * | 2021-11-09 | 2022-03-25 | 珠海亿智电子科技有限公司 | Method and device for parallel BCH error correction decoding |
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| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20080312 Termination date: 20130424 |