CN201001099Y - Oscillator - Google Patents
Oscillator Download PDFInfo
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- CN201001099Y CN201001099Y CNU200620133988XU CN200620133988U CN201001099Y CN 201001099 Y CN201001099 Y CN 201001099Y CN U200620133988X U CNU200620133988X U CN U200620133988XU CN 200620133988 U CN200620133988 U CN 200620133988U CN 201001099 Y CN201001099 Y CN 201001099Y
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Abstract
The utility model discloses an oscillator, which comprises a current supply module and a phase inverter chain; wherein the current output end of the current supply module is respectively outputted an N way current to provide a load current for the phase inverter chain, the N way current of the input end of the current supply module provides a discharging current for the phase inverter chain. The oscillator of the utility model has strong anti interference capacity, the oscillating frequency of the oscillator changes following the change of the power voltage, the applied circuit is simple and the cost is low.
Description
Technical Field
The utility model relates to an anti-interference frequency stability high oscillator belongs to electron technical field.
Background
At present, in a chip requiring an integrated oscillator, two schemes are adopted: 1. as shown in fig. 1, the oscillator externally connected with the oscillation resistor is divided into a chip inside a dotted line frame, and a resistor R is arranged outside the chip. The oscillation frequency of the oscillator can be changed by changing the external resistor, but in this way, a pin needs to be led out to the outside of the chip for connecting the external resistor, and in some application environments with serious interference, such as motor driving, high-static environment and the like, the external interference easily enters the chip through the pin, so that the oscillator output generates high-frequency noise, and the system is unstable in operation or crashed. 2. The ring oscillator, as shown in fig. 2, is integrated inside the chip, the frequency varies greatly with voltage, and the frequency cannot be changed.
SUMMERY OF THE UTILITY MODEL
In order to solve the above problems, the present invention provides an oscillator, which includes a current source module and a phase inverter chain; one end of the current source module is connected to a voltage source; the current output ends of the current source modules respectively output N paths of currents to provide load currents for the inverter chains; the N paths of currents at the current input end of the current source module provide discharge currents for the inverter chain.
Each load current Io1, Io2 and … … IoN at the current output end of the current source module is equal; each of the inverter chains at the current inputs provides the same current Ii1, Ii2, … … IiN.
N is greater than or equal to 3.
The current source module comprises a resistor REXTOne end of the NMOS tube M3 is connected to a voltage source VDD, the other end of the NMOS tube M3 is connected to the drain of the voltage source VDD, the other end of the NMOS tube M3 is connected to the drain of the NMOS tube M3, the gate of the NMOS tube M4 is connected to the gate of the NMOS tube M4, the source of the NMOS tube M4 is connected to the ground, the drain of the NMOS tube M4 is connected to the source of the M0 in the output circuit part of the current source module, the output circuit part of the current source module comprises PMOS tubes M1, M11, M21 and … … MN1, current mirrors are respectively formed by the PMOS tubes M0, and the drains; the source of the M1 is connected to the drain of an NMOS transistor M5 in the input circuit part of the current source module, and the drains of M11, M21, … … MN1 output currents Io1, Io2, … … IoN; the sources of the NMOS tubes M3 and M4 are connected with the input circuit part of the current source module, M12, M22, … … MN2 and M5 respectively form a current mirror, the sources of the current mirror are grounded, and the drains of the M12, M22 and … … MN2 are input with currents Ii1, Ii2 and … … IiN.
The width-to-length ratios of the NMOS transistors M3 and M4 are equal.
The output circuit parts M0, M1 and M11, M21, … … MN1 of the current source modules have equal width-to-length ratios.
The width-length ratio of the NMOS tubes M5 and M12, M22 and … … MN2 of the input circuit part of the current source module is equal to that of the NMOS tubes M3 and M4.
The current source module is an anti-interference current source module, and further comprises a protection resistor R0, a PMOS tube M2, and a capacitor C0: one end of the protection resistor R0 is connected to the resistor REXTThe other end is connected with the drain electrode of an NMOS tube M3; a PMOS tube M2 is added between the drain of the NMOS tube M4 and the output circuit part of the current source module, the source of the PMOS tube M2 is connected to the drain of the NMOS tube M4, the gate is connected with a power supply VDD, the drain is connected with the source of the M0 in the current source module, PMOS tubes M1, M11, M21, … … MN1 in the output circuit part of the current source module and M0 respectively form a current mirror, the drains of the PMOS tubes are connected to the power supply VDD, the source of the M1 is connected to the drain of the NMOS tube M5 in the input circuit part of the current source module, and the drains of the M11, M21 and … … MN1 output currents Io1, Io2 and … … IoN; the capacitor C0 is connected in parallel with the NMOS tube M4, one end of the capacitor C0 is connected with the drain electrode of the NMOS tube M4, the other end of the capacitor C0 is grounded, and the capacitor C0 is connected to the source electrodes of the NMOS tubes M3 and M4 and is connected with the input circuit part of the current source; the sources of the NMOS tubes M3 and M4 are connected with the input circuit part of the current source module, M12, M22, … … MN2 and M5 respectively form a current mirror, the sources of the current mirror are grounded, and the drains of the M12, M22 and … … MN2 are input with currents Ii1, Ii2 and … … IiN.
The inverter chain comprises N stages, in the 1 st stage, the drain electrode of a PMOS tube M13 is connected to a voltage source VDD, the source electrode of the PMOS tube M13 is connected with a current input end of a current source module, the input current is Io1, one path of current output end of the current source module is connected to the drain electrode of an NMOS tube M14, the current output is Ii1, the source electrode of the NMOS tube M14 is grounded, one end of a capacitor C1 is connected to the source electrode of the PMOS tube M13 and the grid electrode of the NMOS tube M14, the other end of the capacitor C1 is grounded, one end of an inverter IV1 is connected with the drain electrode of the NMOS tube M14, and the other end of the inverter IV; similarly, the 2 nd stage includes a PMOS transistor M23, an NMOS transistor M24, and a capacitor C2, the connection mode of each element is the same as that of the 1 st stage, and an inverter IV2 is connected to the gate of the PMOS transistor of the 3 rd stage; sequentially reaching the Nth stage, the Nth stage comprises a PMOS tube MN3, an NMOS tube MN4 and a capacitor CN, the connection mode of all elements is the same as that of the 1 st stage, the grid electrode of the PMOS tube M13 in the 1 st stage is connected to the output end of the phase inverter IVN of the Nth stage, and meanwhile, a clock signal is output through one phase inverter IVF.
The width-to-length ratios of the NMOS transistors M14, M24 and … … MN4 of the inverter chain are equal to the width-to-length ratios of the NMOS transistors M3 and M4 in the current source module.
The capacitances C1, C2 … … CN of the inverter chain are equal in capacitance value.
The utility model discloses the advantage is that the interference killing feature is strong, and oscillating frequency changes little RC oscillator along with mains voltage, and the application circuit is simple, and is with low costs. In addition, the local oscillator improves the frequency stability of the oscillation frequency changing along with the power supply, so that the oscillator can maintain the stable oscillation frequency when the power supply has interference and fluctuation
Other features, objects and effects of the present invention will become more apparent and understood from the following description of preferred embodiments of the invention taken in conjunction with the accompanying drawings.
Drawings
FIG. 1 is a commonly used RC oscillator;
FIG. 2 is a commonly used ring oscillator;
fig. 3 is a block diagram of an oscillator according to the present invention;
FIG. 4 is a schematic circuit diagram of a current source module in the block diagram of FIG. 3;
FIG. 5 is a schematic circuit diagram of a current source module that is an anti-jamming current source module;
FIG. 6 is a circuit schematic of the inverter chain of the schematic of FIG. 3;
throughout the above drawings, the same reference numerals indicate the same, similar or corresponding features or functions.
Detailed Description
Example one
The utility model provides a pair of oscillator, it includes current source module and phase inverter chain, as shown in fig. 3.
Current source module in oscillator As shown in FIG. 4, the current source module includes a resistor REXTOne end of the NMOS tube M3 is connected to a voltage source VDD, the other end of the NMOS tube M3 is connected to the drain of an NMOS tube M4, the source of the NMOS tube M4 is connected to the ground, the drain of the NMOS tube M4 is connected to the source of the NMOS tube M0 in the output circuit part of the current source module, PMOS tubes M1, M11, M21 and M … … MN1 in the output circuit part of the current source module and M0 respectively form a current mirror, the drains of the PMOS tubes are connected to the voltage source VDD, the source of the NMOS tube M1 is connected to the drain of an NMOS tube M5 in the input circuit part of the current source module, and the drains of the NMOS tubes M11, M21 and … … MN1 output currents Io1, Io2 and … … IoN; the sources of the NMOS tubes M3 and M4 are connected with the input circuit part of the current source module, M12, M22, … … MN2 and M5 respectively form a current mirror, the sources of the current mirror are grounded, and the drains of the M12, M22 and … … MN2 are input with currents Ii1, Ii2 and … … IiN. The width-to-length ratios of the NMOS transistors M3 and M4 are equal, and form a current mirror, so that the on-state current of M4 is IDS(M4)，IDS(M4)＝IREFIREFIs a resistance REXTThe current at (c); conduction current of M0 is IDS(M0)，IDS(M0)＝IREF。
Wherein,
IREF＝(VDD-VGS(M3))/REXT
wherein, VGS(M3)Is the cut-off voltage, V, of the NMOS transistor M3DDIs the voltage value of the voltage source VDD.
The output circuit part of the current source module comprises PMOS tubes M0, M1, M11, M12 and … … MN1, the width-length ratios of the PMOS tubes are the same, M0, M1, M11, M12 and M … … MN1 form a current mirror, and therefore the output current Io1, Io2, I … …, I IoNDS(M1)＝IDS(M0)＝IREF(IDS(M1)The conduction current of the PMOS transistor M1). The input circuit part of the current source module comprises NMOS transistors M5, M12, M22 and … … MN2, the width-length ratios of the NMOS transistors are the same, M5, M12, M22 and … … MN2 form a current mirror, and therefore, the input current Ii1, Ii2, Ii … …, I IiNDS(M5)＝IREF(IDS(M5)The on current of the NMOS transistor M5).
Fig. 6 is a circuit schematic of an inverter chain. The oscillation frequency of the inverter chain varies relatively little with the supply voltage. The width-length ratios of the NMOS transistors M14, M24 and … … MN4 are selected to be the same as those of the NMOS transistors M3, M4, M4, M12, M22 and … … MN2, so that M14 and Io1 are equivalent to an inverter, and the output of the inverter is VGS(M14)≈VGS(M4)＝VGS(M3)And is turned over. Similarly, M24 and Io2, … … MN4 and IoN are equivalent to inverters, respectively at VGS(M24)≈VGS(M4)＝VGS(M3)，……VGS(MN4)≈VGS(M4)＝VGS(M3)And is turned over. The width-length ratio of the PMOS transistors M13, M23 and … … MN3 is selected so that the charging time of the capacitors C1, C2 and … … CN is much shorter than the discharging time, and C1 ═ C2 ═ … … ═ CN. The oscillation period T of the inverter chain is thus the sum of the C1 discharge time, the C2 discharge time, … … and CN discharge time. The formula is as follows: t ═ N (V)DD-VGS(M3))×C1/IREF，
When I isREF＝(VDD-VGS(M3))/REXTWhen the temperature of the water is higher than the set temperature,
T＝NREXTC1
as can be seen from the above, the oscillation period T is related to the supply voltage VDDIs irrelevant. I.e. the oscillation frequency remains substantially constant with voltage fluctuations.
Example two
If the current source module is the circuit of fig. 4, then if the resistance R isEXTAt the input of voltage fluctuation and current IREFThe voltage fluctuation changes, so that the output current and the input current of the current source module change. In order to ensure stable output and input of the current source module, the current source module is improved to have an anti-interference function.
As shown in fig. 5, a protection resistor R0, a PMOS transistor M2, and a capacitor C0 are added to the current source module of fig. 4. One end of the protection resistor R0 is connected to the resistor REXTThe other end is connected with the drain electrode of an NMOS tube M3; a PMOS tube M2 is added between the drain of the NMOS tube M4 and the output circuit part of the current source module, the source of the PMOS tube M2 is connected to the drain of the NMOS tube M4, the gate is connected with a power supply VDD, the drain is connected with the source of the M0 in the current source module, PMOS tubes M1, M11, M21, … … MN1 in the output circuit part of the current source module and M0 respectively form a current mirror, the drains of the PMOS tubes are connected to the power supply VDD, the source of the M1 is connected to the drain of the NMOS tube M5 in the input circuit part of the current source module, and the drains of the M11, M21 and … … MN1 output currents Io1, Io2 and … … IoN; the capacitor C0 is connected in parallel with the NMOS tube M4, one end of the capacitor C0 is connected with the drain electrode of the NMOS tube M4, the other end of the capacitor C0 is grounded, and the capacitor C0 is connected to the source electrodes of the NMOS tubes M3 and M4 and is connected with the input circuit part of the current source; the sources of the NMOS tubes M3 and M4 are connected with the input circuit part of the current source module, M12, M22, … … MN2 and M5 respectively form a current mirror, the sources of the current mirror are grounded, and the drains of the M12, M22 and … … MN2 are input with currents Ii1, Ii2 and … … IiN. Resistance REXTAt a current of IREF：
IREF＝(VDD-VGS(M3))/(REXT+R0)。
Thus, when voltage fluctuation exists, the resistance R of the slave current source moduleEXTAfter entering, the interference amplitude is reduced through the voltage drop of the protective resistor R0; the NMOS transistor M4, the PMOS transistor M2 and the capacitor C0 form a T-shaped filter network, so that high-frequency interference is greatly filtered.
The inverter chain circuit is still shown in fig. 6, and is not described in detail.
When I isREF＝(VDD-VGS(M3))/(REXT+ R0) of the reaction mixture,
T＝N(REXT+R0)C1
as can be seen from the above, the oscillation period T is related to the supply voltage VDDIs irrelevant. I.e. the oscillation frequency remains substantially constant with voltage fluctuations.
The test shows that when the resistance R isEXTWhen a disturbance with 200V amplitude and 30ns rise time exists, the influence on the oscillation frequency is as follows:
1) the oscillation frequency of the oscillator without an anti-interference function is improved by 10 times, and the duration time is 5 mu s;
2) and if the oscillator has the anti-interference function, the oscillation frequency can be increased by 2 times, and the duration time is 1 mu s.
It can be seen that, to ensure stable oscillation frequency, the oscillator should preferably have good interference rejection.
Note that, the most preferred embodiment of the present invention is that N is 3, but when N > 3, the present invention can also realize a stable oscillation frequency.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that those skilled in the art can make various improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be construed as the protection scope of the present invention.
Claims (11)
1. An oscillator comprising a current source module and an inverter chain;
the method is characterized in that: one end of the current source module is connected to a voltage source; the current output ends of the current source modules respectively output N paths of currents to provide load currents for the inverter chains; the N paths of currents at the current input end of the current source module provide discharge currents for the inverter chain.
2. The oscillator of claim 1, wherein: each load current Io1, Io2 and … … IoN at the current output end of the current source module is equal; each of the inverter chains at the current inputs provides the same current Ii1, Ii2, … … IiN.
3. The oscillator as set forth in claim 1, wherein: n is greater than or equal to 3.
4. The oscillator as set forth in claim 1, wherein: the current source module comprises a resistor REXTOne end of the NMOS tube M3 is connected to a voltage source VDD, the other end of the NMOS tube M3 is connected to the drain of the voltage source VDD, the other end of the NMOS tube M3 is connected to the drain of the NMOS tube M3, the gate of the NMOS tube M4 is connected to the gate of the NMOS tube M4, the source of the NMOS tube M4 is connected to the ground, the drain of the NMOS tube M4 is connected to the source of the M0 in the output circuit part of the current source module, the output circuit part of the current source module comprises PMOS tubes M1, M11, M21 and … … MN1, current mirrors are respectively formed by the PMOS tubes M0, and the drains; the source of the M1 is connected to the drain of an NMOS transistor M5 in the input circuit part of the current source module, and the drains of M11, M21, … … MN1 output currents Io1, Io2, … … IoN; the sources of the NMOS tubes M3 and M4 are connected with the input circuit part of the current source module, M12, M22, … … MN2 and M5 respectively form a current mirror, the sources of the current mirror are grounded, and the drains of the M12, M22 and … … MN2 are input with currents Ii1, Ii2 and … … IiN.
5. The oscillator of claim 4, wherein: the width-to-length ratios of the NMOS transistors M3 and M4 are equal.
6. The oscillator of claim 4, wherein: the output circuit parts M0, M1, M11, M21 and … … MN1 of the current source modules have the same width-to-length ratio.
7. The oscillator of claim 4, wherein: the width-length ratio of the NMOS tubes M5 and M12, M22 and … … MN2 of the input circuit part of the current source module is equal to that of the NMOS tubes M3 and M4.
8. The oscillator according to claim 1 or 4, characterized in that: the current source module is an anti-interference current source module, and further comprises a protection resistor R0, a PMOS tube M2, and a capacitor C0: one end of the protection resistor R0 is connected to the resistor REXTThe other end is connected with the drain electrode of an NMOS tube M3; a PMOS tube M2 is added between the drain of the NMOS tube M4 and the output circuit part of the current source module, the source of the PMOS tube M2 is connected to the drain of the NMOS tube M4, the gate is connected with a power supply VDD, the drain is connected with the source of the M0 in the current source module, PMOS tubes M1, M11, M21, … … MN1 in the output circuit part of the current source module and M0 respectively form a current mirror, the drains of the PMOS tubes are connected to the power supply VDD, the source of the M1 is connected to the drain of the NMOS tube M5 in the input circuit part of the current source module, and the drains of the M11, M21 and … … MN1 output currents Io1, Io2 and … … IoN; the capacitor C0 is connected in parallel with the NMOS tube M4, one end of the capacitor C0 is connected with the drain electrode of the NMOS tube M4, the other end of the capacitor C0 is grounded, and the capacitor C0 is connected to the source electrodes of the NMOS tubes M3 and M4 and is connected with the input circuit part of the current source; the sources of the NMOS tubes M3 and M4 are connected with the input circuit part of the current source module, M12, M22, … … MN2 and M5 respectively form a current mirror, the sources of the current mirror are grounded, and the drains of the M12, M22 and … … MN2 are input with currents Ii1, Ii2 and … … IiN.
9. The RC oscillator of claim 1, wherein: the inverter chain comprises N stages, in the 1 st stage, the drain electrode of a PMOS tube M13 is connected to a voltage source VDD, the source electrode of the PMOS tube M13 is connected with a current input end of a current source module, the input current is Io1, one path of current output end of the current source module is connected to the drain electrode of an NMOS tube M14, the current output is Ii1, the source electrode of an NMOS tube M14 is grounded, one end of a capacitor C1 is connected to the source electrode of the PMOS tube M13 and the grid electrode of the NMOS tube M14, the other end of the capacitor C1 is grounded, one end of an inverter IV1 is connected with the drain electrode of the NMOS tube M14, and the other end of the inverter IV 1; similarly, the 2 nd stage includes a PMOS transistor M23, an NMOS transistor M24, and a capacitor C2, the connection mode of each element is the same as that of the 1 st stage, and an inverter IV2 is connected to the gate of the PMOS transistor of the 3 rd stage; sequentially reaching the Nth stage, the Nth stage comprises a PMOS tube MN3, an NMOS tube MN4 and a capacitor CN, the connection mode of all elements is the same as that of the 1 st stage, the grid electrode of the PMOS tube M13 in the 1 st stage is connected to the output end of the phase inverter IVN of the Nth stage, and meanwhile, a clock signal is output through one phase inverter IVF.
10. The oscillator as set forth in claim 9, wherein: the width-length ratio of the NMOS tubes M14, M24 and … … MN4 of the inverter chain is equal to that of the NMOS tubes M3 and M4 in the current source module.
11. The oscillator as set forth in claim 9, wherein: the capacitances of the capacitors C1 and C2 … … CN of the inverter chain are equal.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU200620133988XU CN201001099Y (en) | 2006-10-08 | 2006-10-08 | Oscillator |
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| CNU200620133988XU CN201001099Y (en) | 2006-10-08 | 2006-10-08 | Oscillator |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102237859A (en) * | 2010-05-07 | 2011-11-09 | 旺宏电子股份有限公司 | Oscillator with frequency determined by relative size of current source |
| CN102739197A (en) * | 2012-07-17 | 2012-10-17 | 杭州士兰微电子股份有限公司 | RC (remote control) annular oscillator and voltage regulating method thereof |
-
2006
- 2006-10-08 CN CNU200620133988XU patent/CN201001099Y/en not_active Expired - Lifetime
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102237859A (en) * | 2010-05-07 | 2011-11-09 | 旺宏电子股份有限公司 | Oscillator with frequency determined by relative size of current source |
| US8836435B2 (en) | 2010-05-07 | 2014-09-16 | Macronix International Co., Ltd. | Oscillator with frequency determined by relative magnitudes of current sources |
| CN102237859B (en) * | 2010-05-07 | 2015-04-15 | 旺宏电子股份有限公司 | Oscillators whose frequency is determined by the relative magnitudes of the current sources |
| CN102739197A (en) * | 2012-07-17 | 2012-10-17 | 杭州士兰微电子股份有限公司 | RC (remote control) annular oscillator and voltage regulating method thereof |
| CN102739197B (en) * | 2012-07-17 | 2015-08-19 | 杭州士兰微电子股份有限公司 | A kind of RC ring oscillator and voltage adjusting method thereof |
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