CN207303112U - Thin film transistor (TFT), array base palte and display device - Google Patents

Abstract

The utility model discloses a thin film transistor, an array substrate and a display device, belonging to the technical field of display. The thin film transistor includes: a gate pattern, an active layer pattern, and a gate insulating layer between the gate pattern and the active layer pattern; the thin film transistor also includes: a first conductive pattern, a second conductive pattern, and a first conductive pattern and The first intermediate insulating layer between the second conductive patterns; wherein, the first conductive pattern and the second conductive pattern are respectively a source pattern and a drain pattern; the first intermediate insulating layer is provided with a first via hole, and the second conductive pattern The pattern is connected with the active layer pattern through the first via hole. By arranging the first intermediate insulating layer between the source pattern and the drain pattern, the phenomenon of short circuit between the source electrode and the drain electrode is effectively avoided. The utility model is used in a display device.

Description

Thin film transistor, array substrate and display device

technical field

The utility model relates to the field of display technology, in particular to a thin film transistor, an array substrate and a display device.

Background technique

With the development of the field of display technology, various products with display functions appear in daily life, such as mobile phones, tablet computers, televisions, notebook computers, digital photo frames, navigators, virtual reality (English: Virtual Reality; abbreviation: VR ), etc., these products all need to be assembled with display panels without exception.

At present, most display panels can include an array substrate, a color filter substrate, and a liquid crystal layer between the array substrate and the color filter substrate. The array substrate includes a base substrate and a plurality of thin film transistors arranged in an array formed on the base substrate. (English: Thin Film Transistor; TFT for short). For VR products, in order not to affect the 3D (English: Three-Dimensional) display effect of VR, it is necessary to increase the number of pixels per inch (English: PixelsPer Inch; abbreviation: PPI) in the array substrate, which can be achieved by reducing the TFT The distance between the source and the drain is reduced, thereby reducing the size of the pixel, thereby improving the PPI of the array substrate.

However, if the distance between the source and the drain in the TFT is too small, the source and the drain are easily short-circuited when the source and the drain are formed, causing the corresponding TFT to be short-circuited, so the resulting TFT is prone to product failure. bad.

Utility model content

The present application provides a thin film transistor, an array substrate and a display device, which can solve the problem that existing TFTs are prone to defective products. Described technical scheme is as follows:

In a first aspect, a thin film transistor is provided, including:

a gate pattern, an active layer pattern, and a gate insulating layer located between the gate pattern and the active layer pattern;

The thin film transistor further includes: a first conductive pattern, a second conductive pattern, and a first intermediate insulating layer between the first conductive pattern and the second conductive pattern;

Wherein, the first conductive pattern and the second conductive pattern are respectively a source pattern and a drain pattern;

A first via hole is provided on the first intermediate insulating layer, and the second conductive pattern is connected to the active layer pattern through the first via hole.

Optionally, the thin film transistor further includes: a second intermediate insulating layer;

The active layer pattern, the gate insulating layer, the gate pattern, the second intermediate insulating layer, the first conductive pattern, the first intermediate insulating layer and the second conductive pattern are stacked in sequence set up;

The second intermediate insulating layer is provided with a second via hole and a third via hole, the first conductive pattern is connected to the active layer pattern through the second via hole, and the second conductive pattern passes through the The first via hole and the third via hole are connected to the active layer pattern.

Optionally, a fourth via hole and a fifth via hole are provided on the gate insulating layer,

The first conductive pattern is sequentially connected to the active layer pattern through the second via hole and the fourth via hole, and the second conductive pattern is sequentially passed through the first via hole, the third via hole The hole and the fifth via are connected with the active layer pattern.

Optionally, the gate pattern, the gate insulating layer, the active layer pattern, the first conductive pattern, the first intermediate insulating layer and the second conductive pattern are stacked in sequence.

In a second aspect, a method for manufacturing a thin film transistor is provided, the method comprising:

forming a gate pattern, an active layer pattern, a gate insulating layer, a first conductive pattern, a second conductive pattern and a first intermediate insulating layer on the base substrate;

Wherein, the gate insulating layer is located between the gate pattern and the active layer pattern, and the first intermediate insulating layer is located between the first conductive pattern and the second conductive pattern;

The first conductive pattern and the second conductive pattern are respectively a source pattern and a drain pattern;

A first via hole is provided on the first intermediate insulating layer, and the second conductive pattern is connected to the active layer pattern through the first via hole.

Optionally, forming a gate pattern, an active layer pattern, a gate insulating layer, a first conductive pattern, a second conductive pattern and a first intermediate insulating layer on the base substrate includes:

The active layer pattern, the gate insulating layer, the gate pattern, the second intermediate insulating layer, the first conductive pattern, the first intermediate insulating layer and the the second conductive pattern;

Wherein, a second via hole and a third via hole are provided on the second intermediate insulating layer, the first conductive pattern is connected to the active layer pattern through the second via hole, and the second conductive pattern connected to the active layer pattern sequentially through the first via hole and the third via hole;

Alternatively, the gate pattern, the gate insulating layer, the active layer pattern, the first conductive pattern, the first intermediate insulating layer and the second conductive pattern are sequentially formed on the base substrate. graphics.

In a third aspect, an array substrate is provided, including:

Substrate substrate;

Thin film transistors and pixel electrode patterns are sequentially arranged on the base substrate, and the thin film transistors are the thin film transistors described in the first aspect;

The pixel electrode pattern is electrically connected to one of the first conductive pattern and the second conductive pattern.

Optionally, the array substrate further includes: a flat layer disposed on the thin film transistor;

A sixth via hole is provided on the planar layer, and the pixel electrode pattern is electrically connected to one of the first conductive pattern and the second conductive pattern through the sixth via hole.

Optionally, the array substrate further includes: a light-shielding layer pattern and a buffer layer;

The pattern of the light-shielding layer, the buffer layer and the thin film transistor are sequentially stacked;

Wherein, the thin film transistor further includes: a second intermediate insulating layer, the active layer pattern, the gate insulating layer, the gate pattern, the second intermediate insulating layer, the first conductive pattern, the The first intermediate insulating layer and the second conductive pattern are stacked in sequence.

Optionally, the source pattern includes a source, and the drain pattern includes a drain,

The gap between the orthographic projection of the source on the substrate and the orthographic projection of the drain on the substrate is 0, and the orthographic projection of the source on the substrate is There is no overlapping area between the projection and the orthographic projection of the drain on the substrate.

Optionally, the array substrate further includes: a passivation layer and a common electrode pattern disposed on the pixel electrode pattern.

In a fourth aspect, a method for manufacturing an array substrate is provided, the method comprising:

forming thin film transistors on the base substrate;

forming a pixel electrode pattern on the thin film transistor;

Wherein, the thin film transistor includes:

a gate pattern, an active layer pattern, and a gate insulating layer located between the gate pattern and the active layer pattern;

The thin film transistor further includes: a first conductive pattern, a second conductive pattern, and a first intermediate insulating layer between the first conductive pattern and the second conductive pattern;

The first conductive pattern and the second conductive pattern are respectively a source pattern and a drain pattern;

A first via hole is provided on the first intermediate insulating layer, and the second conductive pattern is connected to the active layer pattern through the first via hole;

The pixel electrode pattern is electrically connected to one of the first conductive pattern and the second conductive pattern.

Optionally, the thin film transistor further includes: a second intermediate insulating layer, the active layer pattern, the gate insulating layer, the gate pattern, the second intermediate insulating layer, the first conductive pattern , the first intermediate insulating layer and the second conductive pattern are stacked in sequence,

Before forming the thin film transistor on the base substrate, the method also includes:

A light-shielding layer pattern and a buffer layer are sequentially formed on the base substrate.

Optionally, forming a pixel electrode pattern on the thin film transistor includes:

forming a flat layer on the thin film transistor;

forming a pixel electrode pattern on the planar layer;

Wherein, a sixth via hole is provided on the planar layer, and the pixel electrode pattern is electrically connected to one of the first conductive pattern and the second conductive pattern through the sixth via hole.

A fifth aspect provides a display device, including: the array substrate described in the third aspect.

The beneficial effects brought by the technical solution provided by the embodiment of the utility model are:

In the thin film transistor, array substrate and display device provided by the embodiments of the present invention, since the first intermediate insulating layer is provided between the first conductive pattern and the second conductive pattern, the first conductive pattern and the second conductive pattern are respectively source pattern and the drain pattern, so the source pattern and the drain pattern are formed by two patterning processes, thus avoiding the existing gap between the source and the drain when the source and the drain are formed by one patterning process The distance between the source and the drain is too small, resulting in a short-circuit phenomenon between the source and the drain, thereby effectively improving the product yield of the TFT. And under the premise of avoiding the short circuit between the source and the drain, the distance between the source and the drain can be effectively reduced, thereby improving the PPI of the array substrate, and at the same time effectively avoiding the appearance of the subsequent display device. dark spot phenomenon.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings that need to be used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some implementations of the present invention. For example, those of ordinary skill in the art can also obtain other drawings based on these drawings on the premise of not paying creative efforts.

FIG. 1 is a schematic structural view of an array substrate provided in the prior art;

Fig. 2-1 is a top view of a TFT provided by an embodiment of the present invention;

Figure 2-2 is a cross-sectional view at B-B' of Figure 2-1;

Fig. 3-1 is a top view of another TFT provided by the embodiment of the present invention;

Figure 3-2 is a cross-sectional view at C-C' of Figure 3-1;

Fig. 4-1 is a top view of another TFT provided by the embodiment of the present invention;

Figure 4-2 is a cross-sectional view of 4-1 at B-B';

Fig. 5 is a flow chart of a manufacturing method of a TFT provided by an embodiment of the present invention;

6 is a flow chart of another TFT manufacturing method provided by the embodiment of the present invention;

Fig. 7-1 is a top view of an array substrate provided by an embodiment of the present invention;

Figure 7-2 is a cross-sectional view at D-D' in Figure 7-1;

Fig. 8-1 is a top view of another array substrate provided by an embodiment of the present invention;

Figure 8-2 is a cross-sectional view at D-D' in Figure 8-1;

Figure 8-3 is a cross-sectional view at E-E' in Figure 8-1;

Fig. 9-1 is a top view of an array substrate provided in the prior art;

Figure 9-2 is a cross-sectional view at F-F' in Figure 9-1;

Fig. 9-3 is a top view of another array substrate provided by the prior art;

Figure 9-4 is a cross-sectional view at F-F' in Figure 9-3;

Figure 9-5 is an effect diagram of the phenomenon that the via hole does not penetrate through the via hole in the prior art;

Fig. 10 is a schematic structural diagram of another array substrate provided by the embodiment of the present invention;

Fig. 11 is a flow chart of a method for manufacturing an array substrate provided by an embodiment of the present invention;

FIG. 12 is a flow chart of another method for manufacturing an array substrate provided by an embodiment of the present invention.

Detailed ways

In order to make the purpose, technical solutions and advantages of the present utility model clearer, the implementation of the present utility model will be further described in detail below in conjunction with the accompanying drawings.

Please refer to FIG. 1. FIG. 1 is a schematic structural diagram of an array substrate provided in the prior art. The array substrate 00 may include: a glass substrate 01, a light-shielding layer pattern 02, a buffer layer 03, an Source layer pattern 04, gate insulating layer 05, gate pattern 06, intermediate insulating layer 07, source-drain pattern 08, flat layer 09, pixel electrode pattern 010, passivation layer 011 and common electrode pattern 012. When the PPI of the array substrate 00 needs to be increased, the distance d0 between the source 08a and the drain 08b in the source-drain pattern 08 can be reduced.

Usually, the source electrode 08a and the drain electrode 08b are formed by performing a patterning process on the source-drain film on the intermediate insulating layer 07. The patterning process may include photoresist coating, exposure, development, etching, etc. etch and photoresist stripping. Due to the influence of the existing process, if the distance d0 between the source 08a and the drain 08b is too small, since the source 08a and the drain 08b are made of metal materials, a patterning process is performed on the source-drain film There may be metal residue between the source 08a and the drain 08b formed after the treatment, so the source 08a and the drain 08b are easily shorted, resulting in a short circuit of the corresponding TFT, and the resulting TFT is prone to defective products.

The utility model provides a TFT, which can improve the product yield of the TFT, please refer to Figure 2-1 and Figure 2-2, Figure 2-1 is a top view of a TFT provided by the embodiment of the utility model, Figure 2- 2 is a cross-sectional view at BB' in Fig. 2-1.

The TFT 10 may include: a gate pattern 11 , an active layer pattern 12 and a gate insulating layer 13 between the gate pattern 11 and the active layer pattern 12 .

The TFT 10 may further include: a first conductive pattern 14 , a second conductive pattern 15 and a first intermediate insulating layer 16 located between the first conductive pattern 14 and the second conductive pattern 15 .

Wherein, the first conductive pattern 14 and the second conductive pattern 15 are source pattern and drain pattern respectively. That is, the first conductive pattern 14 is a source pattern, and the second conductive pattern 15 is a drain pattern; or, the first conductive pattern 14 is a drain pattern, and the second conductive pattern 15 is a source pattern. The first intermediate insulating layer 16 is provided with a first via hole 161 , and the second conductive pattern 15 is connected to the active layer pattern 12 through the first via hole 161 .

To sum up, in the TFT provided by the embodiment of the present invention, since the first intermediate insulating layer is provided between the first conductive pattern and the second conductive pattern, the first conductive pattern and the second conductive pattern are respectively the source pattern and the The drain pattern, so the source pattern and the drain pattern are formed by two patterning processes, thereby avoiding the existing problem of the source and drain being formed by one patterning process due to the distance between the source and the drain If the value is too small, the source and drain will be short-circuited, thereby effectively improving the yield rate of TFT products.

In practical applications, since the TFT can be a top-gate TFT or a bottom-gate TFT, the embodiments of the present invention take the following two implementation methods as examples for schematic illustration:

In the first possible implementation mode, when the TFT is a top-gate TFT, please refer to Figure 3-1 and Figure 3-2, Figure 3-1 is a top view of another TFT provided by the embodiment of the present invention, Fig. 3-2 is a cross-sectional view at CC' of Fig. 3-1. The TFT 10 may also include: a second intermediate insulating layer 17, the active layer pattern 12 in the TFT 10, the gate insulating layer 13, the gate pattern 11, the second intermediate insulating layer 17, the first conductive pattern 14, the first The intermediate insulating layer 16 and the second conductive pattern 15 are stacked in sequence. The second intermediate insulating layer 17 is provided with a second via hole 171 and a third via hole 172. At this time, the first conductive pattern 14 is connected to the active layer pattern 12 through the second via hole 171, and the second conductive pattern 15 is sequentially connected. It is connected with the active layer pattern 12 through the first via hole 161 and the third via hole 172 .

Optionally, when the gate insulating layer 13 may have a whole-layer structure, as shown in FIG. 3-1 and FIG. 3-2 , the gate insulating layer 13 may be provided with a fourth via hole 131 and a fifth via hole 132, At this time, the first conductive pattern 14 is connected to the active layer pattern 12 through the second via hole 171 and the fourth via hole 131 in sequence, and the second conductive pattern 15 is connected to the active layer pattern 12 through the first via hole 161, the third via hole 172 and the fifth via hole in sequence. The via hole 132 is connected with the active layer pattern. Optionally, as shown in FIG. 3-1, the orthographic projections of the first via hole 161, the third via hole 172 and the fifth via hole 132 overlap in the vertical direction, and the second via hole 171 and the fourth via hole 131 Orthographic projections along the vertical direction are superimposed, and the vertical direction is the stacking direction of each layer structure of the TFT, such as the direction perpendicular to the paper in Figure 3-1.

In the second possible way, when the TFT is a bottom-gate TFT, please refer to Figure 4-1 and Figure 4-2, Figure 4-1 is a top view of another TFT provided by the embodiment of the present invention, Fig. 4-2 is a cross-sectional view of 4-1 at BB'. In the TFT 10, the gate pattern 11, the gate insulating layer 13, the active layer pattern 12, the first conductive pattern 14, the first intermediate insulating layer 16 and the second conductive pattern 15 are stacked in sequence.

To sum up, in the TFT provided by the embodiment of the present invention, since the first intermediate insulating layer is provided between the first conductive pattern and the second conductive pattern, the first conductive pattern and the second conductive pattern are respectively the source pattern and the The drain pattern, so the source pattern and the drain pattern are formed by two patterning processes, thereby avoiding the existing problem of the source and drain being formed by one patterning process due to the distance between the source and the drain If the value is too small, the source and drain will be short-circuited, thereby effectively improving the product yield of the TFT.

The embodiment of the utility model also provides a method for manufacturing a TFT, which may include:

A gate pattern, an active layer pattern, a gate insulating layer, a first conductive pattern, a second conductive pattern and a first intermediate insulating layer are formed on the base substrate.

Wherein, the gate insulating layer is located between the gate pattern and the active layer pattern, and the first intermediate insulating layer is located between the first conductive pattern and the second conductive pattern; the first conductive pattern and the second conductive pattern are source pattern and Drain pattern: a first via hole is provided on the first intermediate insulating layer, and the second conductive pattern is connected with the active layer pattern through the first via hole.

In summary, in the TFT manufacturing method provided by the embodiment of the present invention, since the first intermediate insulating layer is provided between the first conductive pattern and the second conductive pattern, the first conductive pattern and the second conductive pattern are respectively source electrode pattern and drain pattern, so the source pattern and drain pattern are formed by two patterning processes, thereby avoiding the existing problem of forming the source and drain by one patterning process due to the gap between the source and the drain If the distance between them is too small, the source and drain will be short-circuited, thereby effectively improving the yield rate of TFT products.

In practical applications, since the TFT can be a top-gate TFT or a bottom-gate TFT, the manufacturing methods of the TFTs provided by the embodiments of the utility model are also different. The embodiments of the utility model are implemented in the following two ways: Example to illustrate:

In the first practicable manner, when the TFT is a top-gate TFT, the manufacturing method of the TFT may include: sequentially forming an active layer pattern, a gate insulating layer, a gate pattern, and a second intermediate layer on the base substrate. An insulating layer, a first conductive pattern, a first intermediate insulating layer and a second conductive pattern. Wherein, in order that the first conductive pattern can be connected with the active layer pattern, and the second conductive pattern can be connected with the active layer pattern, the first via hole is arranged on the first intermediate insulating layer, and the second via hole is arranged on the second intermediate insulating layer. There are a second via hole and a third via hole, and when the gate insulating layer is a whole-layer structure, a fourth via hole and a fifth via hole can be provided on the gate insulating layer, so that the first conductive pattern can pass through the second via hole in sequence. The via hole and the fourth via hole are connected to the active layer pattern, and the second conductive pattern can be connected to the active layer pattern through the first via hole, the third via hole and the fifth via hole in sequence. In the manufacturing process of the TFT, taking the connection between the second conductive pattern and the active layer pattern as an example, the fifth via hole can be formed while forming the gate insulating layer, and then the fourth via hole can be formed while forming the second intermediate insulating layer. hole, and finally form the first via hole while forming the first intermediate insulating layer, that is, the insulating layer in the TFT and the corresponding via hole are formed at the same time; the gate insulating layer, the second intermediate insulating layer, and the second insulating layer can also be formed sequentially. layer and the first intermediate insulating layer, and then sequentially form the first via hole, the third via hole and the fifth via hole, that is, first form all the insulating layers in the TFT, and then form the corresponding Via. The following embodiments are schematically illustrated by first forming all the insulating layers in the TFT, and then forming corresponding via holes on the insulating layers respectively.

For example, please refer to FIG. 5. FIG. 5 is a flow chart of a TFT manufacturing method provided by an embodiment of the present invention. The structure of the TFT manufactured by this method can refer to FIG. 3-2. The method may include:

Step 501, forming an active layer pattern on a base substrate.

Optionally, the material of the pattern of the active layer may be amorphous silicon or polycrystalline silicon.

For example, the active layer film can be formed on the base substrate by any one of various methods such as deposition, coating, sputtering, etc., and then a patterning process is performed on the active layer film to form an active layer pattern. A patterning process may include: photoresist coating, exposure, development, etching and photoresist stripping.

Step 502, forming a gate insulating layer on the pattern of the active layer.

Optionally, the material of the gate insulating layer may be silicon dioxide, silicon nitride or a mixed material of silicon dioxide and silicon nitride.

Exemplarily, the gate insulating layer may be formed on the base substrate on which the pattern of the active layer is formed by any one of various methods such as deposition, coating, and sputtering.

Step 503, forming a gate pattern on the gate insulating layer.

Optionally, the gate pattern may be formed using metal materials, for example, the gate pattern is made of metal molybdenum (abbreviated: Mo), metal copper (abbreviated: Cu), metal aluminum (abbreviated: Al) or alloy materials.

For example, the gate film can be formed on the base substrate with the gate insulating layer by any of various methods such as deposition, coating, sputtering, etc., and then a patterning process is performed on the gate film to form the gate Patterning, the one patterning process may include: photoresist coating, exposure, development, etching and photoresist stripping.

Step 504, forming a second intermediate insulating layer on the gate pattern.

Optionally, the material of the second intermediate insulating layer may be silicon dioxide, silicon nitride or a mixed material of silicon dioxide and silicon nitride.

For example, the second interlayer insulating layer can be formed on the base substrate on which the gate pattern is formed by any one of various methods such as deposition, coating, and sputtering.

Step 505, forming a first conductive pattern on the second intermediate insulating layer.

Optionally, the first conductive pattern may be a source pattern, and the first conductive pattern may be formed of a metal material, for example, the gate pattern is made of metal Mo, metal Cu, metal Al or an alloy material.

For example, the first conductive film can be formed on the base substrate with the second intermediate insulating layer by any one of deposition, coating, sputtering, etc., and then the first conductive film is patterned once The process forms the first conductive pattern, and the patterning process may include: photoresist coating, exposure, development, etching and photoresist stripping.

In the embodiment of the present utility model, in order to connect the first conductive pattern to the active layer pattern, before step 505, a patterning process may be performed on the second intermediate insulating layer, and then a second conductive pattern may be formed on the second intermediate insulating layer. via holes, so that the first conductive pattern can be connected to the active layer pattern through the second via hole. If the gate insulating layer has a whole-layer structure, for example, when it is necessary to form the TFT shown in FIG. etch time, and then the fourth via hole can be formed on the gate insulating layer after the second via hole is formed on the second intermediate insulating layer. At this time, the first conductive pattern can pass through the second via hole and the fourth via hole in sequence. Graphically connected to the active layer.

Step 506, forming a first intermediate insulating layer on the first conductive pattern.

Optionally, the material of the first intermediate insulating layer may be silicon dioxide, silicon nitride or a mixed material of silicon dioxide and silicon nitride.

For example, the first intermediate insulating layer can be formed on the base substrate on which the first conductive pattern is formed by any one of various methods such as deposition, coating, and sputtering.

Step 507, forming a second conductive pattern on the first intermediate insulating layer.

Optionally, the second conductive pattern may be a drain pattern, and the second conductive pattern may be formed of a metal material, for example, the gate pattern is made of metal Mo, metal Cu, metal Al or an alloy material.

For example, the second conductive film can be formed on the base substrate with the first intermediate insulating layer by any one of deposition, coating, sputtering, etc., and then the second conductive film is patterned once The second conductive pattern is formed by a process, and the one patterning process may include: photoresist coating, exposure, development, etching and photoresist stripping.

In the embodiment of the present invention, in order to connect the second conductive pattern to the active layer pattern, before step 507, a patterning process can be performed on the first intermediate insulating layer, and then the first intermediate insulating layer can be formed on the first intermediate insulating layer. A via hole is formed, and then a third via hole is formed on the two intermediate insulating layers, so that the second conductive pattern can be connected with the active layer pattern through the first via hole and the third via hole in sequence. If the gate insulating layer has a whole-layer structure, for example, when it is necessary to form the TFT shown in FIG. etch time, and then the first via hole can be formed on the first interlayer insulating layer first, then the third via hole is formed on the second interlayer insulating layer, and finally the fifth via hole is formed on the gate insulating layer. At this time, the first via hole The second conductive pattern can be connected with the active layer pattern through the first via hole, the third via hole and the fifth via hole in sequence.

In the second practicable manner, when the TFT is a bottom-gate TFT, the manufacturing method of the TFT may include: sequentially forming a gate pattern, a gate insulating layer, an active layer pattern, a first conductive pattern, the first intermediate insulating layer and the second conductive pattern.

For example, please refer to FIG. 6. FIG. 6 is a flowchart of another TFT manufacturing method provided by the embodiment of the present invention. The structure of the TFT manufactured by this method can refer to FIG. 4-2. The method may include:

Step 601, forming a gate pattern on a base substrate.

For this step 601, reference may be made to the corresponding process in the aforementioned step 503, which will not be repeated here in this embodiment of the present utility model.

Step 602, forming a gate insulating layer on the gate pattern.

For this step 602, reference may be made to the corresponding process in the aforementioned step 502, which will not be repeated in this embodiment of the present invention.

Step 603, forming an active layer pattern on the gate insulating layer.

For this step 603, reference may be made to the corresponding process in the foregoing step 501, which will not be repeated in this embodiment of the present invention.

Step 604, forming a first conductive pattern on the pattern of the active layer.

For this step 604, reference may be made to the corresponding process in the aforementioned step 505, which will not be repeated here in this embodiment of the present utility model.

Step 605, forming a first intermediate insulating layer on the first conductive pattern.

For this step 605, reference may be made to the corresponding process in the aforementioned step 506, which will not be repeated here in this embodiment of the present utility model.

Step 606, forming a second conductive pattern on the first intermediate insulating layer.

In this step 606, reference may be made to the corresponding process in the aforementioned step 507, which will not be repeated here in this embodiment of the present utility model.

In the embodiment of the present utility model, in order to connect the second conductive pattern to the active layer pattern, a patterning process can be performed on the first intermediate insulating layer before step 606, and then the first intermediate insulating layer can be formed on the first intermediate insulating layer. via holes, so that the second conductive pattern can be connected to the active layer pattern through the first via hole.

Those skilled in the art can clearly understand that for the convenience and brevity of the description, the specific principles of the TFT described above can refer to the corresponding content in the foregoing TFT embodiment, which will not be repeated here.

In summary, in the TFT manufacturing method provided by the embodiment of the present invention, since the first intermediate insulating layer is provided between the first conductive pattern and the second conductive pattern, the first conductive pattern and the second conductive pattern are respectively source electrode pattern and drain pattern, so the source pattern and drain pattern are formed by two patterning processes, thereby avoiding the existing problem of forming the source and drain by one patterning process due to the gap between the source and the drain If the distance between them is too small, the source and drain will be short-circuited, thereby effectively improving the yield rate of TFT products.

The embodiment of the utility model also provides an array substrate, as shown in Figure 7-1 and Figure 7-2, Figure 7-1 is a top view of an array substrate provided by the embodiment of the utility model, and Figure 7-2 is a diagram In the cross-sectional view at DD' in 7-1, the array substrate 20 may include: a base substrate 21 ; TFTs and pixel electrode patterns 22 are sequentially arranged on the base substrate 21 . It should be noted that the embodiment of the present utility model is schematically illustrated by taking the TFT in the array substrate 20 as the TFT shown in FIG. 3-2 as an example. In practical applications, the TFT can also be the For the TFT shown in Figure 4-2, the structure of the array substrate formed by the TFT shown in Figure 2-2 or Figure 4-2 is similar to the structure of the array substrate formed by the TFT shown in Figure 3-2. This will not be described in detail in the novel embodiment.

The pixel electrode 22 is electrically connected to one of the first conductive pattern 14 and the second conductive pattern 15. The following embodiments are all schematically illustrated by taking the electrical connection between the pixel electrode 22 and the first conductive pattern 14 as an example. For the pixel electrode 22 The situation of being electrically connected to the second conductive pattern 15 will not be described in detail.

Optionally, the first conductive pattern 14 may include: a source 141 , and the second conductive pattern 15 may include: a drain 151 .

It should be noted that the array substrate shown in FIG. 7-1 only shows the structure of the source, drain, gate and active layer of the TFT in the array substrate, and other structures (such as pixel electrodes) are not shown. 7-1 shows three pixels 30, and one TFT is arranged in each pixel 30.

In the prior art, in order to avoid a short circuit between the source and the drain in the TFT, when designing the TFT, it is necessary to consider the limit distance between the source and the drain. However, in the embodiment of the present invention, a first intermediate insulating layer is provided between the first conductive pattern and the second conductive pattern, so the first conductive pattern and the second conductive pattern are formed by two patterning processes, without Considering the limit distance between the source and the drain, it is possible to avoid the short circuit between the source and the drain, so the distance between the source and the drain can be designed to be smaller, and then a more High PPI array substrate.

To sum up, in the array substrate provided by the embodiment of the present invention, since the first intermediate insulating layer is provided between the first conductive pattern and the second conductive pattern, the first conductive pattern and the second conductive pattern are respectively source patterns and the drain pattern, so the source pattern and the drain pattern are formed by two patterning processes, thereby avoiding the existing patterning process when the source and the drain are formed due to the gap between the source and the drain If the distance is too small, the source and drain will be short-circuited, thereby effectively improving the product yield of the TFT. Moreover, under the premise of avoiding the short circuit between the source and the drain, the distance between the source and the drain can be effectively reduced, thereby improving the PPI of the array substrate.

Optionally, please refer to Figure 8-1 and Figure 8-2. Figure 8-1 is a top view of another array substrate provided by an embodiment of the present invention, and Figure 8-2 is a view of D-D' in Figure 8-1. The array substrate 20 may also include: a planar layer 23 disposed on the TFT; a sixth via hole 231 is disposed on the planar layer 23, and the pixel electrode pattern 22 may communicate with the first conductive layer through the sixth via hole 231. Figure 14 is electrically connected. In practical applications, a seventh via hole 162 may also be provided on the first intermediate insulating layer 16 in the TFT, and the pixel electrode pattern 22 may be electrically connected to the first conductive pattern 14 through the sixth via hole 231 and the seventh via hole 162 in turn. . It should be noted that the array substrate shown in Figure 8-1 only shows the structure of the source, drain, gate and active layer of the TFT in the array substrate, other structures (such as pixel electrodes and flat layers etc.) not shown.

Optionally, please refer to FIG. 8-2 and FIG. 8-3. FIG. 8-3 is a cross-sectional view at EE' in FIG. When injected into the array substrate 20, the gate pattern 11 cannot cover the active layer pattern 12 to play a light-shielding effect. In order to avoid very serious drift of the threshold voltage of the TFT, a light-shielding structure needs to be provided, so the array substrate 20 can also include : the light-shielding layer pattern 24 and the buffer layer 25, the light-shielding layer pattern 24, the buffer layer 25 and the TFT are stacked in sequence.

Optionally, as shown in FIG. 8-2 and FIG. 8-3 , the array substrate may further include: a passivation layer 26 and a common electrode pattern 27 disposed on the pixel electrode pattern 22 .

In the prior art, if the drain is connected to the data line in the array substrate, and the source is connected to the pixel electrode in the array substrate, in order to improve the PPI of the array substrate, the width of the source can also be reduced, for example, please refer to Fig. 9-1 and 9-2, Fig. 9-1 is a top view of an array substrate provided in the prior art, Fig. 9-2 is a cross-sectional view at FF' in Fig. 9-1, and Fig. 9-1 shows The array substrate shown only shows the structure of source 08a, source 08a, gate 06 and active layer pattern 04 in the array substrate, other structures (for example, pixel electrodes) are not shown, and FIG. 9-2 only shows The structure of the intermediate insulating layer 07, the flat layer 09, the source electrode 08a and part of the pixel electrode pattern 010 is shown, and other structures are not shown. A via hole 091 is provided on the flat layer 09. If the width of the source electrode 08a is reduced, in order to ensure sufficient overlap between the source electrode 08a and the pixel electrode pattern 010, the width of the via hole 091 can be increased, but at this time the pixel The electrode pattern 010 has a step difference at a or b, which is likely to cause a risk of breakage, resulting in a weak overlap between the source electrode 08a and the pixel electrode pattern 010, and eventually dark spots may appear after the display device is formed.

In order to avoid the risk of breaking the pixel electrode pattern 010, please refer to Figure 9-3 and Figure 9-4, Figure 9-3 is a top view of another array substrate provided by the prior art, Figure 9-4 is Figure 9-3 In the cross-sectional view at FF' in the figure, the width of the source electrode 08a can be increased, and the width of the via hole 091 can be reduced at the same time. At this time, not only the risk of breaking the pixel electrode pattern 010 can be avoided, but also the The PPI of the array substrate shown in FIG. 9-2 is the same as the PPI of the array substrate shown in FIG. 9-2. However, since the width of the via hole 091 is too small, when the via hole 091 is formed, the phenomenon that the via hole does not penetrate may occur. For example, please refer to FIG. 9-5. FIG. 9-5 is a via hole in the prior art The effect diagram of the phenomenon that the via hole does not penetrate through the 091. A part of the via hole 091 remains at the bottom of the 092, which will also cause a weak overlap between the source electrode 08a and the pixel electrode pattern 010. Finally, after the display device is formed, it is still possible. Dark spots will appear.

However, in the embodiment of the present invention, as shown in Fig. 8-1 and Fig. 8-2, since there is no need to consider the limit distance between the source 141 and the drain 151, the premise of ensuring that the PPI of the array substrate 20 is relatively high In this way, the width of the source electrode 141 can be increased, and the width of the sixth via hole 231 in the planar layer 23 can be increased, thereby ensuring sufficient overlap between the pixel electrode 22 and the source electrode 141, and avoiding the sixth via hole 231 has the phenomenon that the via hole does not penetrate, thereby effectively avoiding the phenomenon of dark spots in the subsequently formed display device.

Optionally, please refer to FIG. 10. FIG. 10 is a schematic structural diagram of another array substrate provided by an embodiment of the present invention. The gap between the orthographic projections on the base substrate is 0, and there is no overlapping area between the orthographic projections of the source 141 on the base substrate 21 and the orthographic projections of the drain 151 on the base substrate 21, that is, the source The distance between the source electrode 141 and the drain electrode 151 is 0. At this time, the distance between the source electrode 141 and the drain electrode 151 in the array substrate 20 can be minimized, and the PPI of the array substrate 20 can be maximized.

To sum up, in the array substrate provided by the embodiment of the present invention, since the first intermediate insulating layer is provided between the first conductive pattern and the second conductive pattern, the first conductive pattern and the second conductive pattern are respectively source patterns and the drain pattern, so the source pattern and the drain pattern are formed by two patterning processes, thereby avoiding the existing patterning process when the source and the drain are formed due to the gap between the source and the drain If the distance is too small, the source and drain will be short-circuited, thereby effectively improving the product yield of the TFT. And under the premise of avoiding the short circuit between the source and the drain, the distance between the source and the drain can be effectively reduced, thereby improving the PPI of the array substrate, and at the same time effectively avoiding the appearance of the subsequent display device. dark spot phenomenon.

The embodiment of the present utility model provides a method for manufacturing an array substrate. Please refer to FIG. 11. FIG. 11 is a flow chart of a method for manufacturing an array substrate provided by an embodiment of the present utility model. The method may include:

Step 1101 , forming a TFT on a base substrate.

Step 1102, forming a pixel electrode pattern on the TFT.

Wherein, the TFT may include: a gate pattern, an active layer pattern, and a gate insulating layer between the gate pattern and the active layer pattern; the TFT also includes: a first conductive pattern, a second conductive pattern, and a The first intermediate insulating layer between the pattern and the second conductive pattern; the first conductive pattern and the second conductive pattern are respectively a source pattern and a drain pattern; the first intermediate insulating layer is provided with a first via hole, and the second conductive pattern The pattern is connected to the active layer pattern through the first via hole; the pixel electrode pattern is electrically connected to one of the first conductive pattern and the second conductive pattern.

To sum up, in the array substrate provided by the embodiment of the present invention, since the first intermediate insulating layer is provided between the first conductive pattern and the second conductive pattern, the first conductive pattern and the second conductive pattern are respectively source patterns and the drain pattern, so the source pattern and the drain pattern are formed by two patterning processes, thereby avoiding the existing patterning process when the source and the drain are formed due to the gap between the source and the drain If the distance is too small, the source and drain will be short-circuited, thereby effectively improving the product yield of the TFT. Moreover, under the premise of avoiding the short circuit between the source and the drain, the distance between the source and the drain can be effectively reduced, thereby improving the PPI of the array substrate.

Please refer to FIG. 12. FIG. 12 is a flow chart of another method for manufacturing an array substrate provided by an embodiment of the present invention. The method may include:

Step 1201, forming a light-shielding layer pattern and a buffer layer sequentially on the base substrate.

As an example, the light-shielding layer film can be formed on the base substrate by any one of various methods such as deposition, coating, and sputtering, and then a patterning process is performed on the light-shielding layer film to form a light-shielding layer pattern. May include: photoresist coating, exposure, development, etching and photoresist stripping. Then, a buffer layer is formed on the base substrate with the pattern of the light-shielding layer formed by any one of various methods such as deposition, coating, and sputtering.

Step 1202, forming TFTs on the buffer layer.

For this step 1202, reference may be made to the corresponding processes in the foregoing steps 501 to 507, and details will not be repeated here in this embodiment of the present utility model.

Step 1203, forming a flat layer on the TFT.

Exemplarily, the planar layer can be formed on the base substrate on which the TFTs are formed by any one of various methods such as deposition, coating, and sputtering.

Step 1204, forming a pixel electrode pattern on the flat layer.

Optionally, the material of the pixel electrode pattern may be indium tin oxide (English: Indium Tin Oxide; abbreviation: ITO).

For example, the pixel electrode film can be formed on the base substrate on which the TFT is formed by any one of various methods such as deposition, coating, sputtering, etc., and then a patterning process is performed on the pixel electrode film to form a pixel electrode pattern, The one patterning process may include: photoresist coating, exposure, development, etching and photoresist stripping.

In the embodiment of the present invention, in order to electrically connect the pixel electrode pattern with one of the first conductive pattern and the second conductive pattern in the TFT, before step 1204, a patterning process can be performed on the flat layer, and then the flat layer can be A sixth via hole is formed on the flat layer, so that the pixel electrode pattern can be electrically connected to the second conductive pattern in the TFT through the sixth via hole; or, before step 1204, a patterning process can be performed on the flat layer, and the second patterning process can be added. The etching time in the process, and then the sixth via hole can be formed on the flat layer, and the seventh via hole can be formed on the first intermediate insulating layer in the TFT, so that the pixel electrode pattern can pass through the sixth via hole and the seventh via hole in sequence. The via hole is electrically connected with the first conductive pattern in the TFT.

Step 1205, sequentially forming a passivation layer and a common electrode pattern on the pixel electrode pattern.

Optionally, the material of the common electrode pattern can be ITO.

For example, the passivation layer can be formed on the base substrate on which the TFT is formed by any one of various methods such as deposition, coating, sputtering and the like. Then, on the array substrate formed with the passivation layer, a common electrode film is formed by any one of various methods such as deposition, coating, and sputtering, and then a patterning process is performed on the common electrode film to form a common electrode pattern. The patterning process may include: photoresist coating, exposure, development, etching and photoresist stripping.

It should be noted that, the above steps 1201 to 1205 can form a top-gate array substrate, for example, the array substrate shown in FIG. 8-2 can be formed. The embodiment of the present utility model can also form a bottom-gate array substrate. For example, TFTs can be formed on the base substrate. This process can refer to the corresponding processes in the aforementioned steps 601 to 606, and the embodiment of the present utility model is not repeated here. Repeat; then execute the above steps 1203 to 1205.

Those skilled in the art can clearly understand that for the convenience and brevity of the description, the specific principles of the array substrate described above can refer to the corresponding content in the foregoing embodiments of the array substrate, and will not be repeated here.

To sum up, in the manufacturing method of the array substrate provided by the embodiment of the present invention, since the first intermediate insulating layer is provided between the first conductive pattern and the second conductive pattern, the first conductive pattern and the second conductive pattern are respectively The source pattern and the drain pattern, so the source pattern and the drain pattern are formed by two patterning processes, thereby avoiding the existing source and drain formation by one patterning process, due to the The distance between them is too small, resulting in a short-circuit phenomenon between the source and the drain, thereby effectively improving the product yield of the TFT. And under the premise of avoiding the short circuit between the source and the drain, the distance between the source and the drain can be effectively reduced, thereby improving the PPI of the array substrate, and at the same time effectively avoiding the appearance of the subsequent display device. dark spot phenomenon.

The embodiment of the present utility model also provides a display device, which may include the array substrate shown in FIG. 7-2 , FIG. 8-2 or FIG. 10 . The display device may be any display panel such as a liquid crystal panel, an organic light-emitting diode (English: Organic Light-Emitting Diode; abbreviation: OLED), an electronic paper, a mobile phone, a tablet computer, a television set, a monitor, a notebook computer, a digital photo frame, a navigator, etc. A product or part with a display function.

Those of ordinary skill in the art can understand that all or part of the steps for implementing the above embodiments can be completed by hardware, and can also be completed by instructing related hardware through a program. The program can be stored in a computer-readable storage medium. The above-mentioned The storage medium mentioned may be a read-only memory, a magnetic disk or an optical disk, and the like.

The above descriptions are only preferred embodiments of the present utility model, and are not intended to limit the present utility model. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present utility model shall be included in this utility model. within the scope of protection of utility models.

Claims (10)

1. A thin film transistor, characterized in that, comprising: a gate pattern, an active layer pattern, and a gate insulating layer located between the gate pattern and the active layer pattern; The thin film transistor further includes: a first conductive pattern, a second conductive pattern, and a first intermediate insulating layer between the first conductive pattern and the second conductive pattern; Wherein, the first conductive pattern and the second conductive pattern are respectively a source pattern and a drain pattern; A first via hole is provided on the first intermediate insulating layer, and the second conductive pattern is connected to the active layer pattern through the first via hole. 2. The thin film transistor according to claim 1, characterized in that, The thin film transistor also includes: a second intermediate insulating layer; The active layer pattern, the gate insulating layer, the gate pattern, the second intermediate insulating layer, the first conductive pattern, the first intermediate insulating layer and the second conductive pattern are stacked in sequence set up; The second intermediate insulating layer is provided with a second via hole and a third via hole, the first conductive pattern is connected to the active layer pattern through the second via hole, and the second conductive pattern passes through the The first via hole and the third via hole are connected to the active layer pattern. 3. The thin film transistor according to claim 2, characterized in that, A fourth via hole and a fifth via hole are provided on the gate insulating layer, The first conductive pattern is sequentially connected to the active layer pattern through the second via hole and the fourth via hole, and the second conductive pattern is sequentially passed through the first via hole, the third via hole The hole and the fifth via are connected with the active layer pattern. 4. The thin film transistor according to claim 1, characterized in that, The gate pattern, the gate insulating layer, the active layer pattern, the first conductive pattern, the first intermediate insulating layer and the second conductive pattern are stacked in sequence. 5. An array substrate, characterized in that, comprising: Substrate substrate; Thin-film transistors and pixel electrode patterns are sequentially arranged on the base substrate, and the thin-film transistors are the thin-film transistors described in any one of claims 1 to 4; The pixel electrode pattern is electrically connected to one of the first conductive pattern and the second conductive pattern. 6. The array substrate according to claim 5, characterized in that, The array substrate further includes: a planar layer disposed on the thin film transistor; A sixth via hole is provided on the planar layer, and the pixel electrode pattern is electrically connected to one of the first conductive pattern and the second conductive pattern through the sixth via hole. 7. The array substrate according to claim 5, characterized in that, The array substrate also includes: a light-shielding layer pattern and a buffer layer; The pattern of the light-shielding layer, the buffer layer and the thin film transistor are sequentially stacked; Wherein, the thin film transistor further includes: a second intermediate insulating layer, the active layer pattern, the gate insulating layer, the gate pattern, the second intermediate insulating layer, the first conductive pattern, the The first intermediate insulating layer and the second conductive pattern are stacked in sequence. 8. The array substrate according to claim 5, characterized in that, The source pattern includes a source, the drain pattern includes a drain, The gap between the orthographic projection of the source on the substrate and the orthographic projection of the drain on the substrate is 0, and the orthographic projection of the source on the substrate is There is no overlapping area between the projection and the orthographic projection of the drain on the substrate. 9. The array substrate according to any one of claims 5 to 8, characterized in that, The array substrate further includes: a passivation layer and a common electrode pattern disposed on the pixel electrode pattern. 10 . A display device, comprising: the array substrate according to any one of claims 5 to 9 .